Changeset 71737 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Apr 7, 2018 9:42:19 PM (7 years ago)
- svn:sync-xref-src-repo-rev:
- 121839
- File:
-
- 1 edited
-
trunk/src/VBox/Devices/Audio/DevIchAc97.cpp (modified) (7 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/Audio/DevIchAc97.cpp
r71247 r71737 56 56 #define AC97_FIFO_MAX 256 57 57 58 #define AC97_SR_FIFOE RT_BIT(4) /* rwc, FIFO error. */59 #define AC97_SR_BCIS RT_BIT(3) /* rwc, Buffer completion interrupt status. */60 #define AC97_SR_LVBCI RT_BIT(2) /* rwc, Last valid buffer completion interrupt. */61 #define AC97_SR_CELV RT_BIT(1) /* ro, Current equals last valid. */62 #define AC97_SR_DCH RT_BIT(0) /* ro, Controller halted. */63 #define AC97_SR_VALID_MASK (RT_BIT(5) - 1)58 #define AC97_SR_FIFOE RT_BIT(4) /**< rwc, FIFO error. */ 59 #define AC97_SR_BCIS RT_BIT(3) /**< rwc, Buffer completion interrupt status. */ 60 #define AC97_SR_LVBCI RT_BIT(2) /**< rwc, Last valid buffer completion interrupt. */ 61 #define AC97_SR_CELV RT_BIT(1) /**< ro, Current equals last valid. */ 62 #define AC97_SR_DCH RT_BIT(0) /**< ro, Controller halted. */ 63 #define AC97_SR_VALID_MASK (RT_BIT(5) - 1) 64 64 #define AC97_SR_WCLEAR_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 65 #define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV)66 #define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI)67 68 #define AC97_CR_IOCE RT_BIT(4) /* rw, Interrupt On Completion Enable. */69 #define AC97_CR_FEIE RT_BIT(3) /* rw FIFO Error Interrupt Enable. */70 #define AC97_CR_LVBIE RT_BIT(2) /* rw Last Valid Buffer Interrupt Enable. */71 #define AC97_CR_RR RT_BIT(1) /* rw Reset Registers. */72 #define AC97_CR_RPBM RT_BIT(0) /* rw Run/Pause Bus Master. */65 #define AC97_SR_RO_MASK (AC97_SR_DCH | AC97_SR_CELV) 66 #define AC97_SR_INT_MASK (AC97_SR_FIFOE | AC97_SR_BCIS | AC97_SR_LVBCI) 67 68 #define AC97_CR_IOCE RT_BIT(4) /**< rw, Interrupt On Completion Enable. */ 69 #define AC97_CR_FEIE RT_BIT(3) /**< rw FIFO Error Interrupt Enable. */ 70 #define AC97_CR_LVBIE RT_BIT(2) /**< rw Last Valid Buffer Interrupt Enable. */ 71 #define AC97_CR_RR RT_BIT(1) /**< rw Reset Registers. */ 72 #define AC97_CR_RPBM RT_BIT(0) /**< rw Run/Pause Bus Master. */ 73 73 #define AC97_CR_VALID_MASK (RT_BIT(5) - 1) 74 74 #define AC97_CR_DONT_CLEAR_MASK (AC97_CR_IOCE | AC97_CR_FEIE | AC97_CR_LVBIE) 75 75 76 #define AC97_GC_WR 4 /* rw Warm reset. */77 #define AC97_GC_CR 2 /* rw Cold reset. */76 #define AC97_GC_WR 4 /**< rw Warm reset. */ 77 #define AC97_GC_CR 2 /**< rw Cold reset. */ 78 78 #define AC97_GC_VALID_MASK (RT_BIT(6) - 1) 79 79 80 #define AC97_GS_MD3 RT_BIT(17) /* rw */81 #define AC97_GS_AD3 RT_BIT(16) /* rw */82 #define AC97_GS_RCS RT_BIT(15) /* rwc */83 #define AC97_GS_B3S12 RT_BIT(14) /* ro */84 #define AC97_GS_B2S12 RT_BIT(13) /* ro */85 #define AC97_GS_B1S12 RT_BIT(12) /* ro */86 #define AC97_GS_S1R1 RT_BIT(11) /* rwc */87 #define AC97_GS_S0R1 RT_BIT(10) /* rwc */88 #define AC97_GS_S1CR RT_BIT(9) /* ro */89 #define AC97_GS_S0CR RT_BIT(8) /* ro */90 #define AC97_GS_MINT RT_BIT(7) /* ro */91 #define AC97_GS_POINT RT_BIT(6) /* ro */92 #define AC97_GS_PIINT RT_BIT(5) /* ro */93 #define AC97_GS_RSRVD (RT_BIT(4) |RT_BIT(3))94 #define AC97_GS_MOINT RT_BIT(2) /* ro */95 #define AC97_GS_MIINT RT_BIT(1) /* ro */96 #define AC97_GS_GSCI RT_BIT(0) /* rwc */97 #define AC97_GS_RO_MASK ( AC97_GS_B3S12 |\98 AC97_GS_B2S12 |\99 AC97_GS_B1S12 |\100 AC97_GS_S1CR |\101 AC97_GS_S0CR |\102 AC97_GS_MINT |\103 AC97_GS_POINT |\104 AC97_GS_PIINT |\105 AC97_GS_RSRVD |\106 AC97_GS_MOINT |\107 AC97_GS_MIINT)80 #define AC97_GS_MD3 RT_BIT(17) /**< rw */ 81 #define AC97_GS_AD3 RT_BIT(16) /**< rw */ 82 #define AC97_GS_RCS RT_BIT(15) /**< rwc */ 83 #define AC97_GS_B3S12 RT_BIT(14) /**< ro */ 84 #define AC97_GS_B2S12 RT_BIT(13) /**< ro */ 85 #define AC97_GS_B1S12 RT_BIT(12) /**< ro */ 86 #define AC97_GS_S1R1 RT_BIT(11) /**< rwc */ 87 #define AC97_GS_S0R1 RT_BIT(10) /**< rwc */ 88 #define AC97_GS_S1CR RT_BIT(9) /**< ro */ 89 #define AC97_GS_S0CR RT_BIT(8) /**< ro */ 90 #define AC97_GS_MINT RT_BIT(7) /**< ro */ 91 #define AC97_GS_POINT RT_BIT(6) /**< ro */ 92 #define AC97_GS_PIINT RT_BIT(5) /**< ro */ 93 #define AC97_GS_RSRVD (RT_BIT(4) | RT_BIT(3)) 94 #define AC97_GS_MOINT RT_BIT(2) /**< ro */ 95 #define AC97_GS_MIINT RT_BIT(1) /**< ro */ 96 #define AC97_GS_GSCI RT_BIT(0) /**< rwc */ 97 #define AC97_GS_RO_MASK ( AC97_GS_B3S12 \ 98 | AC97_GS_B2S12 \ 99 | AC97_GS_B1S12 \ 100 | AC97_GS_S1CR \ 101 | AC97_GS_S0CR \ 102 | AC97_GS_MINT \ 103 | AC97_GS_POINT \ 104 | AC97_GS_PIINT \ 105 | AC97_GS_RSRVD \ 106 | AC97_GS_MOINT \ 107 | AC97_GS_MIINT) 108 108 #define AC97_GS_VALID_MASK (RT_BIT(18) - 1) 109 #define AC97_GS_WCLEAR_MASK (AC97_GS_RCS |AC97_GS_S1R1|AC97_GS_S0R1|AC97_GS_GSCI)109 #define AC97_GS_WCLEAR_MASK (AC97_GS_RCS | AC97_GS_S1R1 | AC97_GS_S0R1 | AC97_GS_GSCI) 110 110 111 111 /** @name Buffer Descriptor (BD). … … 550 550 #ifndef VBOX_DEVICE_STRUCT_TESTCASE 551 551 552 553 /********************************************************************************************************************************* 554 * Internal Functions * 555 *********************************************************************************************************************************/ 552 556 DECLINLINE(PAC97STREAM) ichac97GetStreamFromIdx(PAC97STATE pThis, uint32_t uIdx); 553 557 static int ichac97StreamCreate(PAC97STATE pThis, PAC97STREAM pStream, uint8_t u8Strm); … … 590 594 #endif 591 595 596 597 592 598 static void ichac97WarmReset(PAC97STATE pThis) 593 599 { … … 613 619 switch (uIndex) 614 620 { 615 case AC97SOUNDSOURCE_PI_INDEX: return pThis->pSinkLineIn; break;616 case AC97SOUNDSOURCE_PO_INDEX: return pThis->pSinkOut; break;617 case AC97SOUNDSOURCE_MC_INDEX: return pThis->pSinkMicIn; break;618 default: 621 case AC97SOUNDSOURCE_PI_INDEX: return pThis->pSinkLineIn; 622 case AC97SOUNDSOURCE_PO_INDEX: return pThis->pSinkOut; 623 case AC97SOUNDSOURCE_MC_INDEX: return pThis->pSinkMicIn; 624 default: break; 619 625 } 620 626 … … 672 678 uint32_t old_mask = pRegs->sr & AC97_SR_INT_MASK; 673 679 674 static uint32_t const masks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT };675 676 680 if (new_mask ^ old_mask) 677 681 { … … 701 705 if (fSignal) 702 706 { 707 static uint32_t const s_aMasks[] = { AC97_GS_PIINT, AC97_GS_POINT, AC97_GS_MINT }; 703 708 if (iIRQL) 704 pThis->glob_sta |= masks[pStream->u8SD];709 pThis->glob_sta |= s_aMasks[pStream->u8SD]; 705 710 else 706 pThis->glob_sta &= ~ masks[pStream->u8SD];711 pThis->glob_sta &= ~s_aMasks[pStream->u8SD]; 707 712 708 713 LogFlowFunc(("Setting IRQ level=%d\n", iIRQL)); … … 845 850 LogFunc(("[SD%RU8] pStream=%p\n", u8Strm, pStream)); 846 851 852 Assert(u8Strm < 3); 847 853 pStream->u8SD = u8Strm; 848 854
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