Index: /trunk/include/VBox/vmm/hm_svm.h
===================================================================
--- /trunk/include/VBox/vmm/hm_svm.h	(revision 71926)
+++ /trunk/include/VBox/vmm/hm_svm.h	(revision 71927)
@@ -514,6 +514,6 @@
 typedef struct
 {
+    uint16_t    u16Reserved0;
     uint16_t    u16Reserved1;
-    uint16_t    u16Reserved2;
     uint32_t    u32Limit;       /**< Only lower 16 bits are implemented. */
     uint64_t    u64Base;
@@ -561,5 +561,5 @@
         uint32_t    u1VIrqPending       : 1;    /* V_IRQ */
         uint32_t    u1VGif              : 1;    /* VGIF */
-        uint32_t    u6Reserved0         : 6;
+        uint32_t    u6Reserved          : 6;
         uint32_t    u4VIntrPrio         : 4;    /* V_INTR_PRIO */
         uint32_t    u1IgnoreTPR         : 1;    /* V_IGN_TPR */
@@ -567,5 +567,5 @@
         uint32_t    u1VIntrMasking      : 1;    /* V_INTR_MASKING */
         uint32_t    u1VGifEnable        : 1;    /* VGIF enable */
-        uint32_t    u5Reserved1         : 5;
+        uint32_t    u5Reserved          : 5;
         uint32_t    u1AvicEnable        : 1;    /* AVIC enable */
         uint32_t    u8VIntrVector       : 8;    /* V_INTR_VECTOR */
@@ -598,13 +598,13 @@
         uint32_t    u1Type              : 1;   /**< Bit 0: 0 = out, 1 = in */
         uint32_t    u1Reserved          : 1;   /**< Bit 1: Reserved */
-        uint32_t    u1STR               : 1;   /**< Bit 2: String I/O (1) or not (0). */
-        uint32_t    u1REP               : 1;   /**< Bit 3: Repeat prefixed string I/O. */
-        uint32_t    u1OP8               : 1;   /**< Bit 4: 8-bit operand. */
-        uint32_t    u1OP16              : 1;   /**< Bit 5: 16-bit operand. */
-        uint32_t    u1OP32              : 1;   /**< Bit 6: 32-bit operand. */
-        uint32_t    u1ADDR16            : 1;   /**< Bit 7: 16-bit address size. */
-        uint32_t    u1ADDR32            : 1;   /**< Bit 8: 32-bit address size. */
-        uint32_t    u1ADDR64            : 1;   /**< Bit 9: 64-bit address size. */
-        uint32_t    u3SEG               : 3;   /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
+        uint32_t    u1Str               : 1;   /**< Bit 2: String I/O (1) or not (0). */
+        uint32_t    u1Rep               : 1;   /**< Bit 3: Repeat prefixed string I/O. */
+        uint32_t    u1Op8               : 1;   /**< Bit 4: 8-bit operand. */
+        uint32_t    u1Op16              : 1;   /**< Bit 5: 16-bit operand. */
+        uint32_t    u1Op32              : 1;   /**< Bit 6: 32-bit operand. */
+        uint32_t    u1Addr16            : 1;   /**< Bit 7: 16-bit address size. */
+        uint32_t    u1Addr32            : 1;   /**< Bit 8: 32-bit address size. */
+        uint32_t    u1Addr64            : 1;   /**< Bit 9: 64-bit address size. */
+        uint32_t    u3Seg               : 3;   /**< Bits 12:10: Effective segment number. Added w/ decode assist in APM v3.17. */
         uint32_t    u3Reserved          : 3;
         uint32_t    u16Port             : 16;  /**< Bits 31:16: Port number. */
@@ -659,7 +659,7 @@
     struct
     {
+        uint64_t    u12Reserved0        : 12;
+        uint64_t    u40Addr             : 40;
         uint64_t    u12Reserved1        : 12;
-        uint64_t    u40Addr             : 40;
-        uint64_t    u12Reserved2        : 12;
     } n;
     uint64_t    u;
@@ -693,5 +693,5 @@
         uint32_t    u1Sev          :  1;
         uint32_t    u1SevEs        :  1;
-        uint32_t    u29Reserved0   : 29;
+        uint32_t    u29Reserved    : 29;
     } n;
     uint64_t    u;
@@ -708,5 +708,5 @@
         uint32_t    u1IntShadow    :  1;
         uint32_t    u1GuestIntMask :  1;
-        uint32_t    u30Reserved0   : 30;
+        uint32_t    u30Reserved    : 30;
     } n;
     uint64_t    u;
@@ -723,5 +723,5 @@
         uint32_t    u1LbrVirt          :  1;
         uint32_t    u1VirtVmsaveVmload :  1;
-        uint32_t    u30Reserved1       : 30;
+        uint32_t    u30Reserved        : 30;
     } n;
     uint64_t    u;
@@ -751,5 +751,5 @@
     uint64_t        u64InterceptCtrl;
     /** Offset 0x14-0x3f - Reserved. */
-    uint8_t         u8Reserved[0x3c - 0x14];
+    uint8_t         u8Reserved0[0x3c - 0x14];
     /** Offset 0x3c - PAUSE filter threshold.  */
     uint16_t        u16PauseFilterThreshold;
@@ -781,5 +781,5 @@
     SVMAVIC         AvicBar;
     /** Offset 0xa0-0xa7 - Reserved. */
-    uint8_t         u8Reserved2[0xA8 - 0xA0];
+    uint8_t         u8Reserved1[0xA8 - 0xA0];
     /** Offset 0xa8 - Event injection. */
     SVMEVENT        EventInject;
@@ -800,5 +800,5 @@
     SVMAVIC         AvicBackingPagePtr;
     /** Offset 0xe8-0xef - Reserved. */
-    uint8_t         u8Reserved3[0xF0 - 0xE8];
+    uint8_t         u8Reserved2[0xF0 - 0xE8];
     /** Offset 0xf0 - AVIC LOGICAL_TABLE pointer. */
     SVMAVIC         AvicLogicalTablePtr;
@@ -818,5 +818,5 @@
 AssertCompileMemberOffset(SVMVMCBCTRL, u32InterceptXcpt,        0x08);
 AssertCompileMemberOffset(SVMVMCBCTRL, u64InterceptCtrl,        0x0c);
-AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved,              0x14);
+AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved0,             0x14);
 AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterThreshold, 0x3c);
 AssertCompileMemberOffset(SVMVMCBCTRL, u16PauseFilterCount,     0x3e);
@@ -833,5 +833,5 @@
 AssertCompileMemberOffset(SVMVMCBCTRL, NestedPagingCtrl,        0x90);
 AssertCompileMemberOffset(SVMVMCBCTRL, AvicBar,                 0x98);
-AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2,             0xa0);
+AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved1,             0xa0);
 AssertCompileMemberOffset(SVMVMCBCTRL, EventInject,             0xa8);
 AssertCompileMemberOffset(SVMVMCBCTRL, u64NestedPagingCR3,      0xb0);
@@ -842,5 +842,5 @@
 AssertCompileMemberOffset(SVMVMCBCTRL, abInstr,                 0xd1);
 AssertCompileMemberOffset(SVMVMCBCTRL, AvicBackingPagePtr,      0xe0);
-AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved3,             0xe8);
+AssertCompileMemberOffset(SVMVMCBCTRL, u8Reserved2,             0xe8);
 AssertCompileMemberOffset(SVMVMCBCTRL, AvicLogicalTablePtr,     0xf0);
 AssertCompileMemberOffset(SVMVMCBCTRL, AvicPhysicalTablePtr,    0xf8);
@@ -874,13 +874,13 @@
     SVMSELREG   TR;
     /** Offset 0x4A0-0x4CA - Reserved. */
-    uint8_t     u8Reserved4[0x4CB - 0x4A0];
+    uint8_t     u8Reserved0[0x4CB - 0x4A0];
     /** Offset 0x4CB - CPL. */
     uint8_t     u8CPL;
     /** Offset 0x4CC-0x4CF - Reserved. */
-    uint8_t     u8Reserved5[0x4D0 - 0x4CC];
+    uint8_t     u8Reserved1[0x4D0 - 0x4CC];
     /** Offset 0x4D0 - EFER. */
     uint64_t    u64EFER;
     /** Offset 0x4D8-0x547 - Reserved. */
-    uint8_t     u8Reserved6[0x548 - 0x4D8];
+    uint8_t     u8Reserved2[0x548 - 0x4D8];
     /** Offset 0x548 - CR4. */
     uint64_t    u64CR4;
@@ -898,9 +898,9 @@
     uint64_t    u64RIP;
     /** Offset 0x580-0x5D7 - Reserved. */
-    uint8_t     u8Reserved7[0x5D8 - 0x580];
+    uint8_t     u8Reserved3[0x5D8 - 0x580];
     /** Offset 0x5D8 - RSP. */
     uint64_t    u64RSP;
     /** Offset 0x5E0-0x5F7 - Reserved. */
-    uint8_t     u8Reserved8[0x5F8 - 0x5E0];
+    uint8_t     u8Reserved4[0x5F8 - 0x5E0];
     /** Offset 0x5F8 - RAX. */
     uint64_t    u64RAX;
@@ -924,5 +924,5 @@
     uint64_t    u64CR2;
     /** Offset 0x648-0x667 - Reserved. */
-    uint8_t     u8Reserved9[0x668 - 0x648];
+    uint8_t     u8Reserved5[0x668 - 0x648];
     /** Offset 0x668 - PAT (Page Attribute Table) MSR. */
     uint64_t    u64PAT;
@@ -954,9 +954,9 @@
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, IDTR,            0x480 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, TR,              0x490 - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4,     0x4a0 - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved0,     0x4a0 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8CPL,           0x4cb - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5,     0x4cc - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved1,     0x4cc - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64EFER,         0x4d0 - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved6,     0x4d8 - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved2,     0x4d8 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR4,          0x548 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR3,          0x550 - 0x400);
@@ -966,7 +966,7 @@
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RFlags,       0x570 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RIP,          0x578 - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved7,     0x580 - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved3,     0x580 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RSP,          0x5d8 - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved8,     0x5e0 - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved4,     0x5e0 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64RAX,          0x5f8 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64STAR,         0x600 - 0x400);
@@ -979,5 +979,5 @@
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64SysEnterEIP,  0x638 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64CR2,          0x640 - 0x400);
-AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved9,     0x648 - 0x400);
+AssertCompileMemberOffset(SVMVMCBSTATESAVE, u8Reserved5,     0x648 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64PAT,          0x668 - 0x400);
 AssertCompileMemberOffset(SVMVMCBSTATESAVE, u64DBGCTL,       0x670 - 0x400);
@@ -996,9 +996,9 @@
     SVMVMCBCTRL ctrl;
     /** Offset 0x100-0x3FF - Reserved. */
-    uint8_t     u8Reserved3[0x400 - 0x100];
+    uint8_t     u8Reserved0[0x400 - 0x100];
     /** Offset 0x400 - State save area. */
     SVMVMCBSTATESAVE guest;
     /** Offset 0x698-0xFFF- Reserved. */
-    uint8_t     u8Reserved10[0x1000 - 0x698];
+    uint8_t     u8Reserved1[0x1000 - 0x698];
 } SVMVMCB;
 #pragma pack()
@@ -1008,7 +1008,7 @@
 typedef const SVMVMCB *PCSVMVMCB;
 AssertCompileMemberOffset(SVMVMCB, ctrl,         0x00);
-AssertCompileMemberOffset(SVMVMCB, u8Reserved3,  0x100);
+AssertCompileMemberOffset(SVMVMCB, u8Reserved0,  0x100);
 AssertCompileMemberOffset(SVMVMCB, guest,        0x400);
-AssertCompileMemberOffset(SVMVMCB, u8Reserved10, 0x698);
+AssertCompileMemberOffset(SVMVMCB, u8Reserved1,  0x698);
 AssertCompileSize(SVMVMCB, 0x1000);
 
@@ -1059,5 +1059,5 @@
     /** Cache of the LBR virtualization control. */
     uint32_t            u1LbrVirt      :  1;
-    uint32_t            u31Reserved0   : 30;
+    uint32_t            u30Reserved    : 30;
     uint32_t            u32Reserved1;
     /** @} */
Index: /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp	(revision 71926)
+++ /trunk/src/VBox/VMM/VMMAll/HMSVMAll.cpp	(revision 71927)
@@ -435,7 +435,7 @@
             pIoExitInfo->u         = s_auIoOpSize[cbReg & 7];
             pIoExitInfo->u        |= s_auIoAddrSize[(cAddrSizeBits >> 4) & 7];
-            pIoExitInfo->n.u1STR   = fStrIo;
-            pIoExitInfo->n.u1REP   = fRep;
-            pIoExitInfo->n.u3SEG   = iEffSeg & 7;
+            pIoExitInfo->n.u1Str   = fStrIo;
+            pIoExitInfo->n.u1Rep   = fRep;
+            pIoExitInfo->n.u3Seg   = iEffSeg & 7;
             pIoExitInfo->n.u1Type  = enmIoType;
             pIoExitInfo->n.u16Port = u16Port;
Index: /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 71926)
+++ /trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp	(revision 71927)
@@ -3913,5 +3913,5 @@
         Log4(("ctrl.IntCtrl.u1VIrqPending            %#x\n",      pVmcb->ctrl.IntCtrl.n.u1VIrqPending));
         Log4(("ctrl.IntCtrl.u1VGif                   %#x\n",      pVmcb->ctrl.IntCtrl.n.u1VGif));
-        Log4(("ctrl.IntCtrl.u6Reserved0              %#x\n",      pVmcb->ctrl.IntCtrl.n.u6Reserved0));
+        Log4(("ctrl.IntCtrl.u6Reserved0              %#x\n",      pVmcb->ctrl.IntCtrl.n.u6Reserved));
         Log4(("ctrl.IntCtrl.u4VIntrPrio              %#x\n",      pVmcb->ctrl.IntCtrl.n.u4VIntrPrio));
         Log4(("ctrl.IntCtrl.u1IgnoreTPR              %#x\n",      pVmcb->ctrl.IntCtrl.n.u1IgnoreTPR));
@@ -3919,5 +3919,5 @@
         Log4(("ctrl.IntCtrl.u1VIntrMasking           %#x\n",      pVmcb->ctrl.IntCtrl.n.u1VIntrMasking));
         Log4(("ctrl.IntCtrl.u1VGifEnable             %#x\n",      pVmcb->ctrl.IntCtrl.n.u1VGifEnable));
-        Log4(("ctrl.IntCtrl.u5Reserved1              %#x\n",      pVmcb->ctrl.IntCtrl.n.u5Reserved1));
+        Log4(("ctrl.IntCtrl.u5Reserved1              %#x\n",      pVmcb->ctrl.IntCtrl.n.u5Reserved));
         Log4(("ctrl.IntCtrl.u8VIntrVector            %#x\n",      pVmcb->ctrl.IntCtrl.n.u8VIntrVector));
         Log4(("ctrl.IntCtrl.u24Reserved              %#x\n",      pVmcb->ctrl.IntCtrl.n.u24Reserved));
@@ -4992,7 +4992,7 @@
     const uint8_t     cbReg         = (pIoExitInfo->u  >> SVM_IOIO_OP_SIZE_SHIFT)   & 7;
     const uint8_t     cAddrSizeBits = ((pIoExitInfo->u >> SVM_IOIO_ADDR_SIZE_SHIFT) & 7) << 4;
-    const uint8_t     iEffSeg       = pIoExitInfo->n.u3SEG;
-    const bool        fRep          = pIoExitInfo->n.u1REP;
-    const bool        fStrIo        = pIoExitInfo->n.u1STR;
+    const uint8_t     iEffSeg       = pIoExitInfo->n.u3Seg;
+    const bool        fRep          = pIoExitInfo->n.u1Rep;
+    const bool        fStrIo        = pIoExitInfo->n.u1Str;
 
     return HMSvmIsIOInterceptActive(pvIoBitmap, u16Port, enmIoType, cbReg, cAddrSizeBits, iEffSeg, fRep, fStrIo,
@@ -6863,5 +6863,5 @@
     VBOXSTRICTRC rcStrict;
     bool fUpdateRipAlready = false;
-    if (IoExitInfo.n.u1STR)
+    if (IoExitInfo.n.u1Str)
     {
 #ifdef VBOX_WITH_2ND_IEM_STEP
@@ -6882,8 +6882,8 @@
             if (cbInstr <= 15 && cbInstr >= 1)
             {
-                Assert(cbInstr >= 1U + IoExitInfo.n.u1REP);
+                Assert(cbInstr >= 1U + IoExitInfo.n.u1Rep);
                 if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
                 {
-                    /* Don't know exactly how to detect whether u3SEG is valid, currently
+                    /* Don't know exactly how to detect whether u3Seg is valid, currently
                        only enabling it for Bulldozer and later with NRIP.  OS/2 broke on
                        2384 Opterons when only checking NRIP. */
@@ -6892,11 +6892,11 @@
                         && pVM->cpum.ro.GuestFeatures.enmMicroarch >= kCpumMicroarch_AMD_15h_First)
                     {
-                        AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_DS || cbInstr > 1U + IoExitInfo.n.u1REP,
-                                  ("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3SEG, cbInstr, IoExitInfo.n.u1REP));
-                        rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
-                                                        IoExitInfo.n.u3SEG, true /*fIoChecked*/);
+                        AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_DS || cbInstr > 1U + IoExitInfo.n.u1Rep,
+                                  ("u32Seg=%d cbInstr=%d u1REP=%d", IoExitInfo.n.u3Seg, cbInstr, IoExitInfo.n.u1Rep));
+                        rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
+                                                        IoExitInfo.n.u3Seg, true /*fIoChecked*/);
                     }
-                    else if (cbInstr == 1U + IoExitInfo.n.u1REP)
-                        rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
+                    else if (cbInstr == 1U + IoExitInfo.n.u1Rep)
+                        rcStrict = IEMExecStringIoWrite(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
                                                         X86_SREG_DS, true /*fIoChecked*/);
                     else
@@ -6906,6 +6906,6 @@
                 else
                 {
-                    AssertMsg(IoExitInfo.n.u3SEG == X86_SREG_ES /*=0*/, ("%#x\n", IoExitInfo.n.u3SEG));
-                    rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1REP, (uint8_t)cbInstr,
+                    AssertMsg(IoExitInfo.n.u3Seg == X86_SREG_ES /*=0*/, ("%#x\n", IoExitInfo.n.u3Seg));
+                    rcStrict = IEMExecStringIoRead(pVCpu, cbValue, enmAddrMode, IoExitInfo.n.u1Rep, (uint8_t)cbInstr,
                                                    true /*fIoChecked*/);
                     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitIOStringRead);
@@ -6955,5 +6955,5 @@
     {
         /* IN/OUT - I/O instruction. */
-        Assert(!IoExitInfo.n.u1REP);
+        Assert(!IoExitInfo.n.u1Rep);
 
         if (IoExitInfo.n.u1Type == SVM_IOIO_WRITE)
