- Timestamp:
- May 4, 2018 10:15:36 PM (7 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r72065 r72128 1557 1557 */ 1558 1558 RTGCUINTREG uGstDr7 = CPUMGetGuestDR7(pVCpu); 1559 /** @todo This isn't correct. BPs work without setting LE and GE under AMD-V. They are also documented as unsupported by P6+. 1560 * The LE|GE flags does have an effect in real mode on AMD-V with instruction fetch breakpoints, they seem to work a little like traps rather than faults. */ 1559 1561 if (!(uGstDr7 & (X86_DR7_LE | X86_DR7_GE))) 1560 1562 uGstDr7 = 0;
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