- Timestamp:
- May 23, 2018 1:50:39 PM (7 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
r71912 r72299 13501 13501 * 13502 13502 * It is important to reflect what the VM-exit gave us (preserving the interruption-type) rather than use 13503 * hmR0VmxSetPendingXcptDB() as the #DB could've been raised while executing ICEBP and not the 'normal' #DB.13504 * Thus it -may- trigger different handling in the CPU (like skipped DPL checks). See @bugref{6398}.13503 * hmR0VmxSetPendingXcptDB() as the #DB could've been raised while executing ICEBP (INT1) and not the 13504 * regular #DB. Thus it -may- trigger different handling in the CPU (like skipped DPL checks), see @bugref{6398}. 13505 13505 * 13506 * Since ICEBP isn't documented on Intel, see AMD spec. 15.20 "Event Injection". 13506 * Intel re-documented ICEBP/INT1 on May 2018 previously documented as part of Intel 386, 13507 * see Intel spec. 24.8.3 "VM-Entry Controls for Event Injection". 13507 13508 */ 13508 13509 rc = hmR0VmxReadExitIntInfoVmcs(pVmxTransient);
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