Changeset 72386 in vbox
- Timestamp:
- May 29, 2018 2:59:15 PM (7 years ago)
- svn:sync-xref-src-repo-rev:
- 122846
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp
r72358 r72386 1154 1154 iReg++; 1155 1155 1156 #if 0 /** @todo Why can't we write these on Intel systems? Not that we really care... */ 1156 1157 const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pGVM->pVM); 1157 1158 if (enmCpuVendor != CPUMCPUVENDOR_AMD) … … 1166 1167 iReg++; 1167 1168 } 1169 #endif 1168 1170 } 1169 1171 … … 1456 1458 } 1457 1459 1460 #ifdef LOG_ENABLED 1458 1461 const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pGVM->pVM); 1462 #endif 1459 1463 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS) 1460 1464 { … … 1476 1480 pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF0000; 1477 1481 pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF8000; 1482 #if 0 /** @todo why can't we read HvX64RegisterIa32MiscEnable? */ 1478 1483 if (enmCpuVendor != CPUMCPUVENDOR_AMD) 1479 {1480 1484 pInput->Names[iReg++] = HvX64RegisterIa32MiscEnable; 1485 #endif 1481 1486 #ifdef LOG_ENABLED 1487 if (enmCpuVendor != CPUMCPUVENDOR_AMD) 1482 1488 pInput->Names[iReg++] = HvX64RegisterIa32FeatureControl; 1483 1489 #endif 1484 }1485 1490 } 1486 1491 … … 2043 2048 iReg++; 2044 2049 2050 #if 0 /** @todo why can't we even read HvX64RegisterIa32MiscEnable? */ 2045 2051 if (enmCpuVendor != CPUMCPUVENDOR_AMD) 2046 2052 { … … 2050 2056 pCtxMsrs->msr.MiscEnable = paValues[iReg].Reg64; 2051 2057 iReg++; 2058 } 2059 #endif 2052 2060 #ifdef LOG_ENABLED 2061 if (enmCpuVendor != CPUMCPUVENDOR_AMD) 2062 { 2053 2063 Assert(pInput->Names[iReg] == HvX64RegisterIa32FeatureControl); 2054 2064 if (paValues[iReg].Reg64 != CPUMGetGuestIa32FeatureControl(pVCpu)) 2055 2065 Log7(("NEM/%u: MSR FEATURE_CONTROL changed %RX64 -> %RX64 (!!)\n", pVCpu->idCpu, CPUMGetGuestIa32FeatureControl(pVCpu), paValues[iReg].Reg64)); 2056 2066 iReg++; 2067 } 2057 2068 #endif 2058 }2059 2060 /** @todo we don't save state for HvX64RegisterIa32FeatureControl */2061 2069 } 2062 2070
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