Changeset 72392 in vbox for trunk/src/VBox

Timestamp:

May 30, 2018 12:27:17 PM (7 years ago)

Author:

vboxsync

Message:

NEM/win: TSC_AUX and APIC_BASE work. bugref:9044

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/APICAll.cpp (modified) (1 diff)
• VMMAll/NEMAllNativeTemplate-win.cpp.h (modified) (4 diffs)
• VMMR0/NEMR0Native-win.cpp (modified) (7 diffs)
• VMMR3/NEMR3Native-win.cpp (modified) (4 diffs)
• include/NEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/APICAll.cpp

@@ -2174 +2174 @@
  *
  * @returns Strict VBox status code.
+ * @retval  VINF_SUCCESS
+ * @retval  VINF_CPUM_R3_MSR_WRITE
+ * @retval  VERR_CPUM_RAISE_GP_0
+ *
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   u64BaseMsr  The value to set.

trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

@@ -1256 +1256 @@
     }
 
-    if (rc == VERR_NEM_CHANGE_PGM_MODE || rc == VERR_NEM_FLUSH_TLB)
+    if (rc == VERR_NEM_CHANGE_PGM_MODE || rc == VERR_NEM_FLUSH_TLB || rc == VERR_NEM_UPDATE_APIC_BASE)
     {
         Log4(("%s/%u: nemR0WinImportState -> %Rrc\n", pszCaller, pGVCpu->idCpu, -rc));
@@ -1796 +1796 @@
             Log(("UnrecovExit/%u: %04x:%08RX64/%s: RFL=%#RX64 -> VINF_SUCCESS\n", pVCpu->idCpu, pMsgHdr->CsSegment.Selector,
                  pMsgHdr->Rip, nemHCWinExecStateToLogStr(pMsgHdr), pMsgHdr->Rflags ));
+            pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT; /* Make sure to reset pending #DB(0). */
             return VINF_SUCCESS;
         }
@@ -2367 +2368 @@
         if (RT_SUCCESS(rc2))
             pCtx->fExtrn = 0;
-        else if (rc2 == VERR_NEM_CHANGE_PGM_MODE || rc2 == VERR_NEM_FLUSH_TLB)
+        else if (rc2 == VERR_NEM_CHANGE_PGM_MODE || rc2 == VERR_NEM_FLUSH_TLB || rc2 == VERR_NEM_UPDATE_APIC_BASE)
         {
             pCtx->fExtrn = 0;
@@ -2374 +2375 @@
             else
             {
-                pVCpu->nem.s.rcPgmPending = -rc2;
-                LogFlow(("NEM/%u: rcPgmPending=%Rrc (rcStrict=%Rrc)\n", pVCpu->idCpu, rc2, VBOXSTRICTRC_VAL(rcStrict) ));
+                pVCpu->nem.s.rcPending = -rc2;
+                LogFlow(("NEM/%u: rcPending=%Rrc (rcStrict=%Rrc)\n", pVCpu->idCpu, rc2, VBOXSTRICTRC_VAL(rcStrict) ));
             }
         }

trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp

@@ -1153 +1153 @@
         pInput->Elements[iReg].Value.Reg64          = pCtxMsrs->msr.MtrrFix4K_F8000;
         iReg++;
+        HV_REGISTER_ASSOC_ZERO_PADDING_AND_HI64(&pInput->Elements[iReg]);
+        pInput->Elements[iReg].Name                 = HvX64RegisterTscAux;
+        pInput->Elements[iReg].Value.Reg64          = pCtxMsrs->msr.TscAux;
+        iReg++;
 
 #if 0 /** @todo Why can't we write these on Intel systems? Not that we really care... */
@@ -1480 +1484 @@
         pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF0000;
         pInput->Names[iReg++] = HvX64RegisterMtrrFix4kF8000;
+        pInput->Names[iReg++] = HvX64RegisterTscAux;
 #if 0 /** @todo why can't we read HvX64RegisterIa32MiscEnable? */
         if (enmCpuVendor != CPUMCPUVENDOR_AMD)
@@ -1947 +1952 @@
         iReg++;
     }
+    bool fUpdateApicBase = false;
     if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
     {
@@ -1956 +1962 @@
                   pVCpu->idCpu, uOldBase, paValues[iReg].Reg64, paValues[iReg].Reg64 ^ uOldBase));
             VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
-            Assert(rc2 == VINF_SUCCESS); NOREF(rc2);
+            if (rc2 == VINF_CPUM_R3_MSR_WRITE)
+            {
+                pVCpu->nem.s.uPendingApicBase = paValues[iReg].Reg64;
+                fUpdateApicBase = true;
+            }
+            else
+                AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", VBOXSTRICTRC_VAL(rc2), paValues[iReg].Reg64));
         }
         iReg++;
@@ -2046 +2058 @@
             Log7(("NEM/%u: MSR MTRR_FIX16K_F8000 changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.MtrrFix4K_F8000, paValues[iReg].Reg64));
         pCtxMsrs->msr.MtrrFix4K_F8000 = paValues[iReg].Reg64;
+        iReg++;
+
+        Assert(pInput->Names[iReg] == HvX64RegisterTscAux);
+        if (paValues[iReg].Reg64 != pCtxMsrs->msr.TscAux )
+            Log7(("NEM/%u: MSR TSC_AUX changed %RX64 -> %RX64\n", pVCpu->idCpu, pCtxMsrs->msr.TscAux, paValues[iReg].Reg64));
+        pCtxMsrs->msr.TscAux = paValues[iReg].Reg64;
         iReg++;
 
@@ -2119 +2137 @@
 
     /* Typical. */
-    if (!fMaybeChangedMode && !fFlushTlb)
+    if (!fMaybeChangedMode && !fFlushTlb && !fUpdateApicBase)
         return VINF_SUCCESS;
 
@@ -2141 +2159 @@
         LogFlow(("nemR0WinImportState: -> VERR_NEM_FLUSH_TLB!\n"));
         rc = VERR_NEM_FLUSH_TLB; /* Calling PGMFlushTLB w/o long jump setup doesn't work, ring-3 does it. */
+    }
+
+    if (fUpdateApicBase && rc == VINF_SUCCESS)
+    {
+        LogFlow(("nemR0WinImportState: -> VERR_NEM_UPDATE_APIC_BASE!\n"));
+        rc = VERR_NEM_UPDATE_APIC_BASE;
     }
 

trunk/src/VBox/VMM/VMMR3/NEMR3Native-win.cpp

@@ -1101 +1101 @@
 
     /*
+     * Some state init.
+     */
+    for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
+    {
+        PNEMCPU pNemCpu = &pVM->aCpus[iCpu].nem.s;
+        pNemCpu->uPendingApicBase = UINT64_MAX;
+    }
+
+    /*
      * Error state.
      * The error message will be non-empty on failure and 'rc' will be set too.
@@ -2037 +2046 @@
         if (RT_SUCCESS(rcStrict))
         {
-            /* We deal with VINF_NEM_CHANGE_PGM_MODE and VINF_NEM_FLUSH_TLB here, since we're running
-               the risk of getting these while we already got another RC (I/O ports). */
-            VBOXSTRICTRC rcPgmPending = pVCpu->nem.s.rcPgmPending;
-            pVCpu->nem.s.rcPgmPending = VINF_SUCCESS;
+            /*
+             * We deal with VINF_NEM_CHANGE_PGM_MODE, VINF_NEM_FLUSH_TLB and
+             * VINF_NEM_UPDATE_APIC_BASE  here, since we're running the risk of
+             * getting these while we already got another RC (I/O ports).
+             *
+             * The APIC base update and a PGM update can happen at the same time, so
+             * we don't depend on the status code for that and always checks it first.
+             */
+            /* APIC base: */
+            if (pVCpu->nem.s.uPendingApicBase != UINT64_MAX)
+            {
+                LogFlow(("nemR3NativeRunGC: calling APICSetBaseMsr(,%RX64)...\n", pVCpu->nem.s.uPendingApicBase));
+                VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, pVCpu->nem.s.uPendingApicBase);
+                AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", VBOXSTRICTRC_VAL(rc2), pVCpu->nem.s.uPendingApicBase));
+                pVCpu->nem.s.uPendingApicBase = UINT64_MAX;
+            }
+
+            /* Status codes: */
+            VBOXSTRICTRC rcPending = pVCpu->nem.s.rcPending;
+            pVCpu->nem.s.rcPending = VINF_SUCCESS;
             if (   rcStrict == VINF_NEM_CHANGE_PGM_MODE
                 || rcStrict == VINF_PGM_CHANGE_MODE
-                || rcPgmPending == VINF_NEM_CHANGE_PGM_MODE )
+                || rcPending == VINF_NEM_CHANGE_PGM_MODE )
             {
                 LogFlow(("nemR3NativeRunGC: calling PGMChangeMode...\n"));
@@ -2060 +2085 @@
                 }
             }
-            else if (rcStrict == VINF_NEM_FLUSH_TLB || rcPgmPending == VINF_NEM_FLUSH_TLB)
+            else if (rcStrict == VINF_NEM_FLUSH_TLB || rcPending == VINF_NEM_FLUSH_TLB)
             {
                 LogFlow(("nemR3NativeRunGC: calling PGMFlushTLB...\n"));
@@ -2077 +2102 @@
                 }
             }
+            else if (rcStrict == VINF_NEM_UPDATE_APIC_BASE || rcPending == VERR_NEM_UPDATE_APIC_BASE)
+                continue;
             else
-                AssertMsg(rcPgmPending == VINF_SUCCESS, ("rcPgmPending=%Rrc\n", VBOXSTRICTRC_VAL(rcPgmPending) ));
+                AssertMsg(rcPending == VINF_SUCCESS, ("rcPending=%Rrc\n", VBOXSTRICTRC_VAL(rcPending) ));
         }
         LogFlow(("nemR3NativeRunGC: returns %Rrc\n", VBOXSTRICTRC_VAL(rcStrict) ));

trunk/src/VBox/VMM/include/NEMInternal.h

@@ -195 +195 @@
     bool                        fLastInterruptShadow : 1;
     bool                        afPadding[1];
+    /** Pending APIC base value.
+     * This is set to UINT64_MAX when not pending  */
+    uint64_t                    uPendingApicBase;
 # ifdef NEM_WIN_USE_OUR_OWN_RUN_API
-    /** Pending VERR_NEM_CHANGE_PGM_MODE or VERR_NEM_FLUSH_TLB. */
-    int32_t                     rcPgmPending;
+    /** Pending VINF_NEM_CHANGE_PGM_MODE, VINF_NEM_FLUSH_TLB or VINF_NEM_UPDATE_APIC_BASE. */
+    int32_t                     rcPending;
     /** The VID_MSHAGN_F_XXX flags.
      * Either VID_MSHAGN_F_HANDLE_MESSAGE | VID_MSHAGN_F_GET_NEXT_MESSAGE or zero. */