Changeset 72560 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jun 15, 2018 11:00:02 AM (6 years ago)

Author:

vboxsync

Message:

EM,HM: Replaced HM exit history with the EM one. VT-x now reads TSC on every exit even when VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT is set. VT-x needed an API for updating the PC as RIP and CS are fetched from the VMCB. bugref:9044

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (4 diffs)
• HMVMXR0.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -1040 +1040 @@
     pVmcbCtrl->u64MSRPMPhysAddr = pVCpu->hm.s.svm.HCPhysMsrBitmap;
 
-    /* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
-    Assert(!pVCpu->hm.s.idxExitHistoryFree);
-    HMCPU_EXIT_HISTORY_RESET(pVCpu);
-
     /* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
     Assert(pVmcbCtrl->u32VmcbCleanBits == 0);
@@ -1061 +1057 @@
         memcpy(pbMsrBitmapCur, pbMsrBitmap, SVM_MSRPM_PAGES << X86_PAGE_4K_SHIFT);
         pVmcbCtrlCur->u64MSRPMPhysAddr = pVCpuCur->hm.s.svm.HCPhysMsrBitmap;
-
-        /* Initialize the #VMEXIT history array with end-of-array markers (UINT16_MAX). */
-        Assert(!pVCpuCur->hm.s.idxExitHistoryFree);
-        HMCPU_EXIT_HISTORY_RESET(pVCpuCur);
 
         /* Initially all VMCB clean bits MBZ indicating that everything should be loaded from the VMCB in memory. */
@@ -4584 +4576 @@
 
     pSvmTransient->u64ExitCode  = pVmcbCtrl->u64ExitCode;       /* Save the #VMEXIT reason. */
-    HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmcbCtrl->u64ExitCode);      /* Update the #VMEXIT history array. */
     pVmcbCtrl->u32VmcbCleanBits       = HMSVM_VMCB_CLEAN_ALL;   /* Mark the VMCB-state cache as unmodified by VMM. */
     pSvmTransient->fVectoringDoublePF = false;                  /* Vectoring double page-fault needs to be determined later. */
@@ -4611 +4602 @@
         }
     }
+
+    EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_SVM, pSvmTransient->u64ExitCode & EMEXIT_F_TYPE_MASK),
+                     pMixedCtx->cs.u64Base + pMixedCtx->rip, uHostTsc);
 }
 

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -2844 +2844 @@
         Log4(("VMXR0SetupVM: pVCpu=%p idCpu=%RU32\n", pVCpu, pVCpu->idCpu));
 
-       /* Initialize the VM-exit history array with end-of-array markers (UINT16_MAX). */
-        Assert(!pVCpu->hm.s.idxExitHistoryFree);
-        HMCPU_EXIT_HISTORY_RESET(pVCpu);
-
         /* Set revision dword at the beginning of the VMCS structure. */
         *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo);
@@ -3653 +3649 @@
         Log4(("Load[%RU32]: VMX_VMCS_GUEST_RIP=%#RX64 fContextUseFlags=%#RX32\n", pVCpu->idCpu, pMixedCtx->rip,
               HMCPU_CF_VALUE(pVCpu)));
+
+        /* Update the exit history entry with the correct CS.BASE + RIP or just RIP. */
+        if (HMCPU_CF_IS_SET(pVCpu, HM_CHANGED_GUEST_SEGMENT_REGS))
+            EMR0HistoryUpdatePC(pVCpu, pMixedCtx->cs.u64Base + pMixedCtx->rip, true);
+        else
+            EMR0HistoryUpdatePC(pVCpu, pMixedCtx->rip, false);
     }
     return rc;
@@ -4594 +4596 @@
         Log4(("Load[%RU32]: CS=%#RX16 Base=%#RX64 Limit=%#RX32 Attr=%#RX32\n", pVCpu->idCpu, pMixedCtx->cs.Sel,
               pMixedCtx->cs.u64Base, pMixedCtx->cs.u32Limit, pMixedCtx->cs.Attr.u));
+
+        /* Update the exit history entry with the correct CS.BASE + RIP. */
+        if (HMCPU_CF_IS_PENDING(pVCpu, HM_CHANGED_GUEST_RIP))
+            EMR0HistoryUpdatePC(pVCpu, pMixedCtx->cs.u64Base + pMixedCtx->rip, true);
     }
 
@@ -9208 +9214 @@
 {
     NOREF(pVM);
+    uint64_t uHostTsc = ASMReadTSC();
 
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
@@ -9219 +9226 @@
 
     if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
-        TMCpuTickSetLastSeen(pVCpu, ASMReadTSC() + pVCpu->hm.s.vmx.u64TSCOffset);
+        TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.u64TSCOffset);
 
     STAM_PROFILE_ADV_STOP_START(&pVCpu->hm.s.StatInGC, &pVCpu->hm.s.StatExit1, x);
@@ -9261 +9268 @@
          *
          * See Intel spec. 26.7 "VM-Entry failures during or after loading guest state".
+         *
+         * Note! We don't have CS or RIP at this point.  Will probably address that later
+         *       by amending the history entry added here.
          */
-        HMCPU_EXIT_HISTORY_ADD(pVCpu, pVmxTransient->uExitReason);
+        EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FLAGS_AND_TYPE(EMEXIT_F_KIND_SVM, pVmxTransient->uExitReason & EMEXIT_F_TYPE_MASK),
+                         UINT64_MAX, uHostTsc);
 
         if (!pVmxTransient->fVMEntryFailed)