Changeset 72592 in vbox for trunk/include/VBox

Timestamp:

Jun 18, 2018 12:24:43 PM (7 years ago)

Author:

vboxsync

Message:

IEM: Defined IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK and IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK for IEMExecDecodedXxxx APIs. Currently only asserted for Rdtsc and Rdtscp. bugref:6973

File:

• trunk/include/VBox/vmm/iem.h (modified) (1 diff)

trunk/include/VBox/vmm/iem.h

@@ -179 +179 @@
 /** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.
  * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */
-#define IEM_CPUMCTX_EXTRN_MUST_MASK    (  CPUMCTX_EXTRN_GPRS_MASK \
-                                        | CPUMCTX_EXTRN_RIP \
-                                        | CPUMCTX_EXTRN_RFLAGS \
-                                        | CPUMCTX_EXTRN_SS \
-                                        | CPUMCTX_EXTRN_CS \
-                                        | CPUMCTX_EXTRN_CR0 \
-                                        | CPUMCTX_EXTRN_CR3 \
-                                        | CPUMCTX_EXTRN_CR4 \
-                                        | CPUMCTX_EXTRN_APIC_TPR \
-                                        | CPUMCTX_EXTRN_EFER \
-                                        | CPUMCTX_EXTRN_DR7 )
+#define IEM_CPUMCTX_EXTRN_MUST_MASK                (  CPUMCTX_EXTRN_GPRS_MASK \
+                                                    | CPUMCTX_EXTRN_RIP \
+                                                    | CPUMCTX_EXTRN_RFLAGS \
+                                                    | CPUMCTX_EXTRN_SS \
+                                                    | CPUMCTX_EXTRN_CS \
+                                                    | CPUMCTX_EXTRN_CR0 \
+                                                    | CPUMCTX_EXTRN_CR3 \
+                                                    | CPUMCTX_EXTRN_CR4 \
+                                                    | CPUMCTX_EXTRN_APIC_TPR \
+                                                    | CPUMCTX_EXTRN_EFER \
+                                                    | CPUMCTX_EXTRN_DR7 )
 /** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.
  * IEM will import missing bits, callers are encouraged to make these registers
  * available prior to injection calls if fetching state anyway.  */
-#define IEM_CPUMCTX_EXTRN_XCPT_MASK    (  IEM_CPUMCTX_EXTRN_MUST_MASK \
-                                        | CPUMCTX_EXTRN_CR2 \
-                                        | CPUMCTX_EXTRN_SREG_MASK \
-                                        | CPUMCTX_EXTRN_TABLE_MASK )
+#define IEM_CPUMCTX_EXTRN_XCPT_MASK                (  IEM_CPUMCTX_EXTRN_MUST_MASK \
+                                                    | CPUMCTX_EXTRN_CR2 \
+                                                    | CPUMCTX_EXTRN_SREG_MASK \
+                                                    | CPUMCTX_EXTRN_TABLE_MASK )
+/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
+ * IEMExecDecoded API not using memory.  IEM will ASSUME the caller of IEM
+ * APIs has ensured these are already present.
+ * @note ASSUMES execution engine has checked for instruction breakpoints
+ *       during decoding. */
+#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK (  CPUMCTX_EXTRN_RIP \
+                                                    | CPUMCTX_EXTRN_RFLAGS \
+                                                    | CPUMCTX_EXTRN_SS   /* for CPL */ \
+                                                    | CPUMCTX_EXTRN_CS   /* for mode */ \
+                                                    | CPUMCTX_EXTRN_CR0  /* for mode */ \
+                                                    | CPUMCTX_EXTRN_EFER /* for mode */ )
+/** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any
+ * IEMExecDecoded API using memory.  IEM will ASSUME the caller of IEM
+ * APIs has ensured these are already present.
+ * @note ASSUMES execution engine has checked for instruction breakpoints
+ *       during decoding. */
+#define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK    (  IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
+                                                    | CPUMCTX_EXTRN_CR3 /* for page tables */ \
+                                                    | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \
+                                                    | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )