VirtualBox

Changeset 72684 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 26, 2018 12:34:57 AM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
123201
Message:

NEM/win: Assert correct register values in messages from Hyper-V. Adjusted for instruction length field width. bugref:9044

File:
1 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

    r72655 r72684  
    3030            } while (0)
    3131
     32/** @def NEMWIN_ASSERT_MSG_REG_VAL
     33 * Asserts the correctness of a register value in a message/context.
     34 */
     35#if 0
     36# define NEMWIN_NEED_GET_REGISTER
     37# if defined(IN_RING0) || defined(NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS)
     38#  define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_pGVCpu, a_enmReg, a_Expr, a_Msg) \
     39    do { \
     40        HV_REGISTER_VALUE TmpVal; \
     41        nemHCWinGetRegister(a_pVCpu, a_pGVCpu, a_enmReg, &TmpVal); \
     42        AssertMsg(a_Expr, a_Msg); \
     43    } while (0)
     44# else
     45#  define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_pGVCpu, a_enmReg, a_Expr, a_Msg) \
     46    do { \
     47        WHV_REGISTER_VALUE TmpVal; \
     48        nemR3WinGetRegister(a_pVCpu, a_enmReg, &TmpVal); \
     49        AssertMsg(a_Expr, a_Msg); \
     50    } while (0)
     51# endif
     52#else
     53# define NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_pGVCpu, a_enmReg, a_Expr, a_Msg) do { } while (0)
     54#endif
     55
     56/** @def NEMWIN_ASSERT_MSG_REG_VAL
     57 * Asserts the correctness of a 64-bit register value in a message/context.
     58 */
     59#define NEMWIN_ASSERT_MSG_REG_VAL64(a_pVCpu, a_pGVCpu, a_enmReg, a_u64Val) \
     60    NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_pGVCpu, a_enmReg, (a_u64Val) == TmpVal.Reg64, \
     61                              (#a_u64Val "=%#RX64, expected %#RX64\n", (a_u64Val), TmpVal.Reg64))
     62/** @def NEMWIN_ASSERT_MSG_REG_VAL
     63 * Asserts the correctness of a segment register value in a message/context.
     64 */
     65#define NEMWIN_ASSERT_MSG_REG_SEG(a_pVCpu, a_pGVCpu, a_enmReg, a_SReg) \
     66    NEMWIN_ASSERT_MSG_REG_VAL(a_pVCpu, a_pGVCpu, a_enmReg, \
     67                                 (a_SReg).Base       == TmpVal.Segment.Base \
     68                              && (a_SReg).Limit      == TmpVal.Segment.Limit \
     69                              && (a_SReg).Selector   == TmpVal.Segment.Selector \
     70                              && (a_SReg).Attributes == TmpVal.Segment.Attributes, \
     71                              ( #a_SReg "=%#RX16 {%#RX64 LB %#RX32,%#RX16} expected %#RX16 {%#RX64 LB %#RX32,%#RX16}\n", \
     72                               (a_SReg).Selector, (a_SReg).Base, (a_SReg).Limit, (a_SReg).Attributes, \
     73                               TmpVal.Segment.Selector, TmpVal.Segment.Base, TmpVal.Segment.Limit, TmpVal.Segment.Attributes))
     74
    3275
    3376/*********************************************************************************************************************************
    … …  
    4689NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
    4790                                           uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged);
     91
    4892
    4993
    … …  
    12191263}
    12201264
     1265#ifdef NEMWIN_NEED_GET_REGISTER
     1266# if defined(IN_RING0) || defined(NEM_WIN_USE_HYPERCALLS_FOR_REGISTERS)
     1267/** Worker for assertion macro. */
     1268NEM_TMPL_STATIC int nemHCWinGetRegister(PVMCPU pVCpu, PGVMCPU pGVCpu, uint32_t enmReg, HV_REGISTER_VALUE *pRetValue)
     1269{
     1270    RT_ZERO(*pRetValue);
     1271#  ifdef IN_RING3
     1272    RT_NOREF(pVCpu, pGVCpu, enmReg);
     1273    return VERR_NOT_IMPLEMENTED;
     1274#  else
     1275    NOREF(pVCpu);
     1276
     1277    /*
     1278     * Hypercall parameters.
     1279     */
     1280    HV_INPUT_GET_VP_REGISTERS *pInput = (HV_INPUT_GET_VP_REGISTERS *)pGVCpu->nem.s.HypercallData.pbPage;
     1281    AssertPtrReturn(pInput, VERR_INTERNAL_ERROR_3);
     1282    AssertReturn(g_pfnHvlInvokeHypercall, VERR_NEM_MISSING_KERNEL_API);
     1283
     1284    pInput->PartitionId = pGVCpu->pGVM->nem.s.idHvPartition;
     1285    pInput->VpIndex     = pGVCpu->idCpu;
     1286    pInput->fFlags      = 0;
     1287    pInput->Names[0]    = (HV_REGISTER_NAME)enmReg;
     1288
     1289    size_t const cbInput = RT_ALIGN_Z(RT_OFFSETOF(HV_INPUT_GET_VP_REGISTERS, Names[1]), 32);
     1290    HV_REGISTER_VALUE *paValues = (HV_REGISTER_VALUE *)((uint8_t *)pInput + cbInput);
     1291    RT_BZERO(paValues, sizeof(paValues[0]) * 1);
     1292
     1293    /*
     1294     * Make the hypercall and copy out the value.
     1295     */
     1296    uint64_t uResult = g_pfnHvlInvokeHypercall(HV_MAKE_CALL_INFO(HvCallGetVpRegisters, 1),
     1297                                               pGVCpu->nem.s.HypercallData.HCPhysPage,
     1298                                               pGVCpu->nem.s.HypercallData.HCPhysPage + cbInput);
     1299    AssertLogRelMsgReturn(uResult == HV_MAKE_CALL_REP_RET(1), ("uResult=%RX64 cRegs=%#x\n", uResult, 1),
     1300                          VERR_NEM_GET_REGISTERS_FAILED);
     1301
     1302    *pRetValue = paValues[0];
     1303    return VINF_SUCCESS;
     1304#  endif
     1305}
     1306# else
     1307/** Worker for assertion macro. */
     1308NEM_TMPL_STATIC int nemR3WinGetRegister(PVMCPU a_pVCpu, uint32_t a_enmReg, WHV_REGISTER_VALUE pValue)
     1309{
     1310    RT_ZERO(*pRetValue);
     1311    RT_NOREF(pVCpu, pGVCpu, enmReg);
     1312    return VERR_NOT_IMPLEMENTED;
     1313}
     1314# endif
     1315#endif
     1316
    12211317
    12221318#ifdef LOG_ENABLED
    … …  
    13221418    if (LogIs3Enabled())
    13231419    {
    1324 # ifdef IN_RING3
     1420# if 0 // def IN_RING3 - causes lazy state import assertions all over CPUM.
    13251421        char szRegs[4096];
    13261422        DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
    … …  
    14331529 * @param   pCtx            The CPU context to update.
    14341530 * @param   pExitCtx        The exit context.
     1531 * @param   cbMinInstr      The minimum instruction length, or 1 if not unknown.
    14351532 */
    1436 DECLINLINE(void) nemHCWinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx, HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr)
     1533DECLINLINE(void) nemHCWinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx,
     1534                                                   HV_X64_INTERCEPT_MESSAGE_HEADER const *pMsgHdr, uint8_t cbMinInstr)
    14371535{
    14381536    Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
    14391537
    14401538    /* Advance the RIP. */
    1441     Assert(pMsgHdr->InstructionLength > 0 && pMsgHdr->InstructionLength < 16);
     1539    Assert(pMsgHdr->InstructionLength >= cbMinInstr);
    14421540    pCtx->rip += pMsgHdr->InstructionLength;
    14431541    pCtx->rflags.Bits.u1RF = 0;
    … …  
    14581556 * @param   pCtx            The CPU context to update.
    14591557 * @param   pExitCtx        The exit context.
     1558 * @param   cbMinInstr      The minimum instruction length, or 1 if not unknown.
    14601559 */
    1461 DECLINLINE(void) nemR3WinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx, WHV_VP_EXIT_CONTEXT const *pExitCtx)
     1560DECLINLINE(void) nemR3WinAdvanceGuestRipAndClearRF(PVMCPU pVCpu, PCPUMCTX pCtx,
     1561                                                   WHV_VP_EXIT_CONTEXT const *pExitCtx, uint8_t cbMinInstr)
    14621562{
    14631563    Assert(!(pCtx->fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS)));
    14641564
    14651565    /* Advance the RIP. */
    1466     Assert(pExitCtx->InstructionLength > 0 && pExitCtx->InstructionLength < 16);
     1566    Assert(pExitCtx->InstructionLength > cbMinInstr);
    14671567    pCtx->rip += pExitCtx->InstructionLength;
    14681568    pCtx->rflags.Bits.u1RF = 0;
    … …  
    18461946           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
    18471947           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE);
    1848     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
    18491948
    18501949    /*
    … …  
    18541953        pCtx->fExtrn &= ~CPUMCTX_EXTRN_NEM_WIN_EVENT_INJECT;
    18551954
    1856 #if 0 /* Experiment: 20K -> 34K exit/s. */
     1955# if 0 /* Experiment: 20K -> 34K exit/s. */
    18571956    if (   pMsg->Header.ExecutionState.EferLma
    18581957        && pMsg->Header.CsSegment.Long
    … …  
    18701969        }
    18711970    }
    1872 #endif
     1971# endif
    18731972
    18741973    /*
    … …  
    19722071    uint64_t const uHostTsc = ASMReadTSC();
    19732072    Assert(pExit->MemoryAccess.AccessInfo.AccessType != 3);
    1974     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    19752073
    19762074    /*
    … …  
    20702168nemHCWinHandleMessageIoPort(PVM pVM, PVMCPU pVCpu, HV_X64_IO_PORT_INTERCEPT_MESSAGE const *pMsg, PCPUMCTX pCtx, PGVMCPU pGVCpu)
    20712169{
     2170    /*
     2171     * Assert message sanity.
     2172     */
    20722173    Assert(   pMsg->AccessInfo.AccessSize == 1
    20732174           || pMsg->AccessInfo.AccessSize == 2
    … …  
    20752176    Assert(   pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
    20762177           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
    2077     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
     2178    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterCs, pMsg->Header.CsSegment);
     2179    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRip, pMsg->Header.Rip);
     2180    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRflags, pMsg->Header.Rflags);
     2181    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);
     2182    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRax, pMsg->Rax);
     2183    if (pMsg->AccessInfo.StringOp)
     2184    {
     2185        NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterDs,  pMsg->DsSegment);
     2186        NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterEs,  pMsg->EsSegment);
     2187        NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRcx, pMsg->Rcx);
     2188        NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRsi, pMsg->Rsi);
     2189        NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRdi, pMsg->Rdi);
     2190    }
    20782191
    20792192    /*
    … …  
    21152228                      pMsg->PortNumber, (uint32_t)pMsg->Rax & fAndMask, pMsg->AccessInfo.AccessSize, VBOXSTRICTRC_VAL(rcStrict) ));
    21162229                if (IOM_SUCCESS(rcStrict))
    2117                     nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
     2230                    nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header, 1);
    21182231# ifdef IN_RING0
    21192232                else if (   rcStrict == VINF_IOM_R3_IOPORT_WRITE
    … …  
    21442257                    pCtx->fExtrn &= ~CPUMCTX_EXTRN_RAX;
    21452258                    Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pMsg->Rax, pCtx->rax));
    2146                     nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
     2259                    nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header, 1);
    21472260                }
    21482261                else
    … …  
    22752388           || pExit->IoPortAccess.AccessInfo.AccessSize == 2
    22762389           || pExit->IoPortAccess.AccessInfo.AccessSize == 4);
    2277     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    22782390
    22792391    /*
    … …  
    23182430                {
    23192431                    nemR3WinCopyStateFromX64Header(pVCpu, pCtx, &pExit->VpContext);
    2320                     nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext);
     2432                    nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext, 1);
    23212433                }
    23222434            }
    … …  
    23382450                    Log4(("IOExit/%u: RAX %#RX64 -> %#RX64\n", pVCpu->idCpu, pExit->IoPortAccess.Rax, pCtx->rax));
    23392451                    nemR3WinCopyStateFromX64Header(pVCpu, pCtx, &pExit->VpContext);
    2340                     nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext);
     2452                    nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext, 1);
    23412453                }
    23422454            }
    … …  
    24492561           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ   // READ & WRITE are probably not used here
    24502562           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
    2451     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
    24522563    AssertMsg(pMsg->Type == HvX64PendingInterrupt || pMsg->Type == HvX64PendingNmi, ("%#x\n", pMsg->Type));
    24532564
    … …  
    24842595     * Assert message sanity.
    24852596     */
    2486     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    24872597    AssertMsg(   pExit->InterruptWindow.DeliverableType == WHvX64PendingInterrupt
    24882598              || pExit->InterruptWindow.DeliverableType == WHvX64PendingNmi,
    … …  
    25222632                                                        PGVMCPU pGVCpu)
    25232633{
    2524     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
     2634    /* Check message register value sanity. */
     2635    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterCs, pMsg->Header.CsSegment);
     2636    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRip, pMsg->Header.Rip);
     2637    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRflags, pMsg->Header.Rflags);
     2638    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);
     2639    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRax, pMsg->Rax);
     2640    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRcx, pMsg->Rcx);
     2641    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRdx, pMsg->Rdx);
     2642    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRbx, pMsg->Rbx);
     2643
     2644    /* Do exit history. */
    25252645    PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID),
    25262646                                            pMsg->Header.Rip + pMsg->Header.CsSegment.Base, ASMReadTSC());
    … …  
    25552675
    25562676        /* Move RIP and we're done. */
    2557         nemHCWinAdvanceGuestRipAndClearRF(pVCpu, &pVCpu->cpum.GstCtx, &pMsg->Header);
     2677        nemHCWinAdvanceGuestRipAndClearRF(pVCpu, &pVCpu->cpum.GstCtx, &pMsg->Header, 2);
    25582678
    25592679        return VINF_SUCCESS;
    … …  
    26032723nemR3WinHandleExitCpuId(PVM pVM, PVMCPU pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit)
    26042724{
    2605     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    26062725    PCEMEXITREC pExitRec = EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_CPUID),
    26072726                                            pExit->VpContext.Rip + pExit->VpContext.Cs.Base, ASMReadTSC());
    … …  
    26362755
    26372756        /* Move RIP and we're done. */
    2638         nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pVCpu->cpum.GstCtx, &pExit->VpContext);
     2757        nemR3WinAdvanceGuestRipAndClearRF(pVCpu, &pVCpu->cpum.GstCtx, &pExit->VpContext, 2);
    26392758
    26402759        RT_NOREF_PV(pVM);
    … …  
    26842803     * A wee bit of sanity first.
    26852804     */
    2686     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
    26872805    Assert(   pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
    26882806           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE);
     2807    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterCs, pMsg->Header.CsSegment);
     2808    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRip, pMsg->Header.Rip);
     2809    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRflags, pMsg->Header.Rflags);
     2810    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);
     2811    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRax, pMsg->Rax);
     2812    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRdx, pMsg->Rdx);
    26892813
    26902814    /*
    … …  
    27252849                    if (rcStrict == VINF_SUCCESS)
    27262850                    {
    2727                         nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
     2851                        nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header, 2);
    27282852                        return VINF_SUCCESS;
    27292853                    }
    … …  
    27542878                        pCtx->rdx = uValue >> 32;
    27552879                        pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
    2756                         nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header);
     2880                        nemHCWinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pMsg->Header, 2);
    27572881                        return VINF_SUCCESS;
    27582882                    }
    … …  
    28312955nemR3WinHandleExitMsr(PVM pVM, PVMCPU pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit, PCPUMCTX pCtx)
    28322956{
    2833     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    2834 
    28352957    /*
    28362958     * Check CPL as that's common to both RDMSR and WRMSR.
    … …  
    28702992                    if (rcStrict == VINF_SUCCESS)
    28712993                    {
    2872                         nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext);
     2994                        nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext, 2);
    28732995                        return VINF_SUCCESS;
    28742996                    }
    … …  
    28933015                        pCtx->rdx = uValue >> 32;
    28943016                        pCtx->fExtrn &= ~(CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RDX);
    2895                         nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext);
     3017                        nemR3WinAdvanceGuestRipAndClearRF(pVCpu, pCtx, &pExit->VpContext, 2);
    28963018                        return VINF_SUCCESS;
    28973019                    }
    … …  
    30883210     * Assert sanity.
    30893211     */
    3090     AssertMsg(pMsg->Header.InstructionLength < 0x10, ("%#x\n", pMsg->Header.InstructionLength));
    30913212    Assert(   pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_READ
    30923213           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_WRITE
    30933214           || pMsg->Header.InterceptAccessType == HV_INTERCEPT_ACCESS_EXECUTE);
     3215    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterCs, pMsg->Header.CsSegment);
     3216    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRip, pMsg->Header.Rip);
     3217    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRflags, pMsg->Header.Rflags);
     3218    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterCr8, (uint64_t)pMsg->Header.Cr8);
     3219    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterDs,  pMsg->DsSegment);
     3220    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterSs,  pMsg->SsSegment);
     3221    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRax, pMsg->Rax);
     3222    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRcx, pMsg->Rcx);
     3223    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRdx, pMsg->Rdx);
     3224    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRbx, pMsg->Rbx);
     3225    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRsp, pMsg->Rsp);
     3226    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRbp, pMsg->Rbp);
     3227    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRsi, pMsg->Rsi);
     3228    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRdi, pMsg->Rdi);
     3229    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR8,  pMsg->R8);
     3230    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR9,  pMsg->R9);
     3231    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR10, pMsg->R10);
     3232    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR11, pMsg->R11);
     3233    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR12, pMsg->R12);
     3234    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR13, pMsg->R13);
     3235    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR14, pMsg->R14);
     3236    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterR15, pMsg->R15);
    30943237
    30953238    /*
    … …  
    31933336nemR3WinHandleExitException(PVM pVM, PVMCPU pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit, PCPUMCTX pCtx)
    31943337{
    3195     /*
    3196      * Assert sanity.
    3197      */
    3198     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    3199 
    32003338    /*
    32013339     * Get most of the register state since we'll end up making IEM inject the
    … …  
    33093447                                                                         PCPUMCTX pCtx, PGVMCPU pGVCpu)
    33103448{
    3311     AssertMsg(pMsgHdr->InstructionLength < 0x10, ("%#x\n", pMsgHdr->InstructionLength));
     3449    /* Check message register value sanity. */
     3450    NEMWIN_ASSERT_MSG_REG_SEG(  pVCpu, pGVCpu, HvX64RegisterCs, pMsgHdr->CsSegment);
     3451    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRip, pMsgHdr->Rip);
     3452    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterRflags, pMsgHdr->Rflags);
     3453    NEMWIN_ASSERT_MSG_REG_VAL64(pVCpu, pGVCpu, HvX64RegisterCr8, (uint64_t)pMsgHdr->Cr8);
    33123454
    33133455# if 0
    … …  
    33653507nemR3WinHandleExitUnrecoverableException(PVM pVM, PVMCPU pVCpu, WHV_RUN_VP_EXIT_CONTEXT const *pExit, PCPUMCTX pCtx)
    33663508{
    3367     AssertMsg(pExit->VpContext.InstructionLength < 0x10, ("%#x\n", pExit->VpContext.InstructionLength));
    3368 
    33693509# if 0
    33703510    /*
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