VirtualBox

Changeset 72744 in vbox for trunk/include/VBox


Ignore:
Timestamp:
Jun 29, 2018 7:36:19 AM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
123280
Message:

VMM: Extend HM changed flags. ​bugref:9193 [HM, CPUM]

Location:
trunk/include/VBox/vmm
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/hm.h

    r72643 r72744  
    217217VMMR0_INT_DECL(bool)            HMR0SuspendPending(void);
    218218VMMR0_INT_DECL(int)             HMR0InvalidatePage(PVMCPU pVCpu, RTGCPTR GCVirt);
    219 VMMR0_INT_DECL(int)             HMR0ImportStateOnDemand(PVMCPU pVCpu, PCPUMCTX pCtx, uint64_t fWhat);
     219VMMR0_INT_DECL(int)             HMR0ImportStateOnDemand(PVMCPU pVCpu, uint64_t fWhat);
    220220
    221221# if HC_ARCH_BITS == 32 && defined(VBOX_WITH_64_BITS_GUESTS)
    … …  
    224224VMMR0_INT_DECL(int)             HMR0TestSwitcher3264(PVM pVM);
    225225# endif
    226 
    227 VMMR0_INT_DECL(int)             HMR0EnsureCompleteBasicContext(PVMCPU pVCpu, PCPUMCTX pMixedCtx);
    228226
    229227/** @} */

  • trunk/include/VBox/vmm/hm_svm.h

    r72643 r72744  
    11041104    do \
    11051105    { \
    1106         Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID);  \
    1107         Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel);    \
    1108         (a_pVmcbStateSave)->a_REG.u16Sel    = (a_pCtx)->a_reg.Sel;      \
    1109         (a_pVmcbStateSave)->a_REG.u32Limit  = (a_pCtx)->a_reg.u32Limit; \
    1110         (a_pVmcbStateSave)->a_REG.u64Base   = (a_pCtx)->a_reg.u64Base;  \
    1111         (a_pVmcbStateSave)->a_REG.u16Attr   = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
     1106        Assert((a_pCtx)->a_reg.fFlags & CPUMSELREG_FLAGS_VALID);       \
     1107        Assert((a_pCtx)->a_reg.ValidSel == (a_pCtx)->a_reg.Sel);       \
     1108        (a_pVmcbStateSave)->a_REG.u16Sel   = (a_pCtx)->a_reg.Sel;      \
     1109        (a_pVmcbStateSave)->a_REG.u32Limit = (a_pCtx)->a_reg.u32Limit; \
     1110        (a_pVmcbStateSave)->a_REG.u64Base  = (a_pCtx)->a_reg.u64Base;  \
     1111        (a_pVmcbStateSave)->a_REG.u16Attr  = HMSVM_CPU_2_VMCB_SEG_ATTR((a_pCtx)->a_reg.Attr.u); \
    11121112    } while (0)
    11131113
    … …  
    11261126    do \
    11271127    { \
    1128         (a_pCtx)->a_reg.Sel       = (a_pVmcbStateSave)->a_REG.u16Sel;   \
    1129         (a_pCtx)->a_reg.ValidSel  = (a_pVmcbStateSave)->a_REG.u16Sel;   \
    1130         (a_pCtx)->a_reg.fFlags    = CPUMSELREG_FLAGS_VALID;    \
    1131         (a_pCtx)->a_reg.u32Limit  = (a_pVmcbStateSave)->a_REG.u32Limit; \
    1132         (a_pCtx)->a_reg.u64Base   = (a_pVmcbStateSave)->a_REG.u64Base;  \
    1133         (a_pCtx)->a_reg.Attr.u    = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
     1128        (a_pCtx)->a_reg.Sel      = (a_pVmcbStateSave)->a_REG.u16Sel;   \
     1129        (a_pCtx)->a_reg.ValidSel = (a_pVmcbStateSave)->a_REG.u16Sel;   \
     1130        (a_pCtx)->a_reg.fFlags   = CPUMSELREG_FLAGS_VALID;             \
     1131        (a_pCtx)->a_reg.u32Limit = (a_pVmcbStateSave)->a_REG.u32Limit; \
     1132        (a_pCtx)->a_reg.u64Base  = (a_pVmcbStateSave)->a_REG.u64Base;  \
     1133        (a_pCtx)->a_reg.Attr.u   = HMSVM_VMCB_2_CPU_SEG_ATTR((a_pVmcbStateSave)->a_REG.u16Attr); \
    11341134    } while (0)
    11351135

  • trunk/include/VBox/vmm/hm_vmx.h

    r72643 r72744  
    5858 */
    5959
    60 /** @def HMVMXCPU_GST_SET_UPDATED
    61  * Sets a guest-state-updated flag.
    62  *
    63  * @param   pVCpu   The cross context virtual CPU structure.
    64  * @param   fFlag   The flag to set.
    65  */
    66 #define HMVMXCPU_GST_SET_UPDATED(pVCpu, fFlag)        (ASMAtomicUoOrU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlag)))
    67 
    68 /** @def HMVMXCPU_GST_IS_SET
    69  * Checks if all the flags in the specified guest-state-updated set is pending.
    70  *
    71  * @param   pVCpu   The cross context virtual CPU structure.
    72  * @param   fFlag   The flag to check.
    73  */
    74 #define HMVMXCPU_GST_IS_SET(pVCpu, fFlag)             ((ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlag)) == (fFlag))
    75 
    76 /** @def HMVMXCPU_GST_IS_UPDATED
    77  * Checks if one or more of the flags in the specified guest-state-updated set
    78  * is updated.
    79  *
    80  * @param   pVCpu   The cross context virtual CPU structure.
    81  * @param   fFlags  The flags to check for.
    82  */
    83 #define HMVMXCPU_GST_IS_UPDATED(pVCpu, fFlags)        RT_BOOL(ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState) & (fFlags))
    84 
    85 /** @def HMVMXCPU_GST_RESET_TO
    86  * Resets the guest-state-updated flags to the specified value.
    87  *
    88  * @param   pVCpu   The cross context virtual CPU structure.
    89  * @param   fFlags  The new value.
    90  */
    91 #define HMVMXCPU_GST_RESET_TO(pVCpu, fFlags)          (ASMAtomicUoWriteU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState, (fFlags)))
    92 
    93 /** @def HMVMXCPU_GST_VALUE
    94  * Returns the current guest-state-updated flags value.
    95  *
    96  * @param   pVCpu   The cross context virtual CPU structure.
    97  */
    98 #define HMVMXCPU_GST_VALUE(pVCpu)                     (ASMAtomicUoReadU32(&(pVCpu)->hm.s.vmx.fUpdatedGuestState))
    99 
    10060/** @name Host-state restoration flags.
    10161 * @note If you change these values don't forget to update the assembly
    … …  
    10363 * @{
    10464 */
    105 #define VMX_RESTORE_HOST_SEL_DS               RT_BIT(0)
    106 #define VMX_RESTORE_HOST_SEL_ES               RT_BIT(1)
    107 #define VMX_RESTORE_HOST_SEL_FS               RT_BIT(2)
    108 #define VMX_RESTORE_HOST_SEL_GS               RT_BIT(3)
    109 #define VMX_RESTORE_HOST_SEL_TR               RT_BIT(4)
    110 #define VMX_RESTORE_HOST_GDTR                 RT_BIT(5)
    111 #define VMX_RESTORE_HOST_IDTR                 RT_BIT(6)
    112 #define VMX_RESTORE_HOST_GDT_READ_ONLY        RT_BIT(7)
    113 #define VMX_RESTORE_HOST_REQUIRED             RT_BIT(8)
    114 #define VMX_RESTORE_HOST_GDT_NEED_WRITABLE    RT_BIT(9)
     65#define VMX_RESTORE_HOST_SEL_DS                                 RT_BIT(0)
     66#define VMX_RESTORE_HOST_SEL_ES                                 RT_BIT(1)
     67#define VMX_RESTORE_HOST_SEL_FS                                 RT_BIT(2)
     68#define VMX_RESTORE_HOST_SEL_GS                                 RT_BIT(3)
     69#define VMX_RESTORE_HOST_SEL_TR                                 RT_BIT(4)
     70#define VMX_RESTORE_HOST_GDTR                                   RT_BIT(5)
     71#define VMX_RESTORE_HOST_IDTR                                   RT_BIT(6)
     72#define VMX_RESTORE_HOST_GDT_READ_ONLY                          RT_BIT(7)
     73#define VMX_RESTORE_HOST_REQUIRED                               RT_BIT(8)
     74#define VMX_RESTORE_HOST_GDT_NEED_WRITABLE                      RT_BIT(9)
    11575/** @} */
    11676
    … …  
    150110 */
    151111/** The host MSRs have been saved. */
    152 #define VMX_LAZY_MSRS_SAVED_HOST              RT_BIT(0)
     112#define VMX_LAZY_MSRS_SAVED_HOST                                RT_BIT(0)
    153113/** The guest MSRs are loaded and in effect. */
    154 #define VMX_LAZY_MSRS_LOADED_GUEST            RT_BIT(1)
     114#define VMX_LAZY_MSRS_LOADED_GUEST                              RT_BIT(1)
    155115/** @} */
    156116
    … …  
    466426#define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX                   12
    467427#define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX                   13
    468 #define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX                14
    469 #define VMX_VMCS_MAX_CACHE_IDX                                  (VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX + 1)
     428#define VMX_VMCS_RO_EXIT_QUAL_CACHE_IDX                         14
     429#define VMX_VMCS_MAX_CACHE_IDX                                  (VMX_VMCS_RO_EXIT_QUAL_CACHE_IDX + 1)
    470430#define VMX_VMCS_GUEST_CR3_CACHE_IDX                            15
    471431#define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX                    (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
    … …  
    606566/** Pointer to a const EPT Page Directory Pointer Table. */
    607567typedef const EPTPDPT *PCEPTPDPT;
    608 
    609568
    610569/**
    … …  
    705664typedef const EPTPD *PCEPTPD;
    706665
    707 
    708666/**
    709667 * EPT Page Table Entry. Bit view.
    … …  
    712670{
    713671    /** 0 - Present bit.
    714      * @remark This is a convenience "misnomer".  The bit actually indicates
    715      *         read access and the CPU will consider an entry with any of the
    716      *         first three bits set as present.  Since all our valid entries
    717      *         will have this bit set, it can be used as a present indicator
    718      *         and allow some code sharing. */
     672     * @remarks This is a convenience "misnomer". The bit actually indicates read access
     673     *          and the CPU will consider an entry with any of the first three bits set
     674     *          as present.  Since all our valid entries will have this bit set, it can
     675     *          be used as a present indicator and allow some code sharing. */
    719676    uint64_t    u1Present       : 1;
    720677    /** 1 - Writable bit. */
    … …  
    13851342/** @} */
    13861343
     1344
    13871345/** @name VMX_VMCS_CTRL_PROC_EXEC
    13881346 * @{
    … …  
    14311389#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL         RT_BIT(31)
    14321390/** @} */
     1391
    14331392
    14341393/** @name VMX_VMCS_CTRL_PROC_EXEC2
    … …  
    15421501#define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO                    0x4404
    15431502#define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE              0x4406
    1544 #define VMX_VMCS32_RO_IDT_INFO                                  0x4408
    1545 #define VMX_VMCS32_RO_IDT_ERROR_CODE                            0x440A
     1503#define VMX_VMCS32_RO_IDT_VECTORING_INFO                        0x4408
     1504#define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE                  0x440A
    15461505#define VMX_VMCS32_RO_EXIT_INSTR_LENGTH                         0x440C
    15471506#define VMX_VMCS32_RO_EXIT_INSTR_INFO                           0x440E
    15481507/** @} */
    15491508
     1509
    15501510/** @name VMX_VMCS32_RO_EXIT_REASON
    15511511 * @{
    … …  
    15531513#define VMX_EXIT_REASON_BASIC(a)                                ((a) & 0xffff)
    15541514/** @} */
     1515
    15551516
    15561517/** @name VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO
    … …  
    15781539/** @} */
    15791540
     1541
    15801542/** @name VMX_VMCS_RO_EXIT_INTERRUPTION_INFO_TYPE
    15811543 * @{
    … …  
    15881550#define VMX_EXIT_INTERRUPTION_INFO_TYPE_SW_XCPT                 6
    15891551/** @} */
     1552
    15901553
    15911554/** @name VMX_VMCS32_RO_IDT_VECTORING_INFO
    … …  
    16001563#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a)                ((a) & ~RT_BIT(12))
    16011564/** @} */
     1565
    16021566
    16031567/** @name VMX_VMCS_RO_IDT_VECTORING_INFO_TYPE
    … …  
    16711635/** @} */
    16721636
     1637
    16731638/** @name Natural width control fields
    16741639 * @{
    … …  
    17011666 */
    17021667/** 0-2:  Debug register number */
    1703 #define VMX_EXIT_QUALIFICATION_DRX_REGISTER(a)                  ((a) & 7)
     1668#define VMX_EXIT_QUAL_DRX_REGISTER(a)                  ((a) & 7)
    17041669/** 3:    Reserved; cleared to 0. */
    1705 #define VMX_EXIT_QUALIFICATION_DRX_RES1(a)                      (((a) >> 3) & 1)
     1670#define VMX_EXIT_QUAL_DRX_RES1(a)                      (((a) >> 3) & 1)
    17061671/** 4:    Direction of move (0 = write, 1 = read) */
    1707 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION(a)                 (((a) >> 4) & 1)
     1672#define VMX_EXIT_QUAL_DRX_DIRECTION(a)                 (((a) >> 4) & 1)
    17081673/** 5-7:  Reserved; cleared to 0. */
    1709 #define VMX_EXIT_QUALIFICATION_DRX_RES2(a)                      (((a) >> 5) & 7)
     1674#define VMX_EXIT_QUAL_DRX_RES2(a)                      (((a) >> 5) & 7)
    17101675/** 8-11: General purpose register number. */
    1711 #define VMX_EXIT_QUALIFICATION_DRX_GENREG(a)                    (((a) >> 8) & 0xF)
     1676#define VMX_EXIT_QUAL_DRX_GENREG(a)                    (((a) >> 8) & 0xF)
    17121677/** Rest: reserved. */
    17131678/** @} */
    17141679
    1715 /** @name VMX_EXIT_QUALIFICATION_DRX_DIRECTION values
    1716  * @{
    1717  */
    1718 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_WRITE              0
    1719 #define VMX_EXIT_QUALIFICATION_DRX_DIRECTION_READ               1
    1720 /** @} */
    1721 
     1680
     1681/** @name VMX_EXIT_QUAL_DRX_DIRECTION values
     1682 * @{
     1683 */
     1684#define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE              0
     1685#define VMX_EXIT_QUAL_DRX_DIRECTION_READ               1
     1686/** @} */
    17221687
    17231688
    … …  
    17261691 */
    17271692/** 0-3:   Control register number (0 for CLTS & LMSW) */
    1728 #define VMX_EXIT_QUALIFICATION_CRX_REGISTER(a)                  ((a) & 0xF)
     1693#define VMX_EXIT_QUAL_CRX_REGISTER(a)                  ((a) & 0xF)
    17291694/** 4-5:   Access type. */
    1730 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS(a)                    (((a) >> 4) & 3)
     1695#define VMX_EXIT_QUAL_CRX_ACCESS(a)                    (((a) >> 4) & 3)
    17311696/** 6:     LMSW operand type */
    1732 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_OP(a)                   (((a) >> 6) & 1)
     1697#define VMX_EXIT_QUAL_CRX_LMSW_OP(a)                   (((a) >> 6) & 1)
    17331698/** 7:     Reserved; cleared to 0. */
    1734 #define VMX_EXIT_QUALIFICATION_CRX_RES1(a)                      (((a) >> 7) & 1)
     1699#define VMX_EXIT_QUAL_CRX_RES1(a)                      (((a) >> 7) & 1)
    17351700/** 8-11:  General purpose register number (0 for CLTS & LMSW). */
    1736 #define VMX_EXIT_QUALIFICATION_CRX_GENREG(a)                    (((a) >> 8) & 0xF)
     1701#define VMX_EXIT_QUAL_CRX_GENREG(a)                    (((a) >> 8) & 0xF)
    17371702/** 12-15: Reserved; cleared to 0. */
    1738 #define VMX_EXIT_QUALIFICATION_CRX_RES2(a)                      (((a) >> 12) & 0xF)
     1703#define VMX_EXIT_QUAL_CRX_RES2(a)                      (((a) >> 12) & 0xF)
    17391704/** 16-31: LMSW source data (else 0). */
    1740 #define VMX_EXIT_QUALIFICATION_CRX_LMSW_DATA(a)                 (((a) >> 16) & 0xFFFF)
     1705#define VMX_EXIT_QUAL_CRX_LMSW_DATA(a)                 (((a) >> 16) & 0xFFFF)
    17411706/* Rest: reserved. */
    17421707/** @} */
    17431708
    1744 /** @name VMX_EXIT_QUALIFICATION_CRX_ACCESS
    1745  * @{
    1746  */
    1747 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE                 0
    1748 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_READ                  1
    1749 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_CLTS                  2
    1750 #define VMX_EXIT_QUALIFICATION_CRX_ACCESS_LMSW                  3
    1751 /** @} */
    1752 
    1753 /** @name VMX_EXIT_QUALIFICATION_TASK_SWITCH
    1754  * @{
    1755  */
    1756 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_SELECTOR(a)          ((a) & 0xffff)
    1757 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE(a)              (((a) >> 30) & 0x3)
     1709
     1710/** @name VMX_EXIT_QUAL_CRX_ACCESS
     1711 * @{
     1712 */
     1713#define VMX_EXIT_QUAL_CRX_ACCESS_WRITE                 0
     1714#define VMX_EXIT_QUAL_CRX_ACCESS_READ                  1
     1715#define VMX_EXIT_QUAL_CRX_ACCESS_CLTS                  2
     1716#define VMX_EXIT_QUAL_CRX_ACCESS_LMSW                  3
     1717/** @} */
     1718
     1719
     1720/** @name VMX_EXIT_QUAL_TASK_SWITCH
     1721 * @{
     1722 */
     1723#define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a)          ((a) & 0xffff)
     1724#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a)              (((a) >> 30) & 0x3)
    17581725/** Task switch caused by a call instruction. */
    1759 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_CALL            0
     1726#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL            0
    17601727/** Task switch caused by an iret instruction. */
    1761 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IRET            1
     1728#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET            1
    17621729/** Task switch caused by a jmp instruction. */
    1763 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_JMP             2
     1730#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP             2
    17641731/** Task switch caused by an interrupt gate. */
    1765 #define VMX_EXIT_QUALIFICATION_TASK_SWITCH_TYPE_IDT             3
     1732#define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT             3
    17661733/** @} */
    17671734
    … …  
    17711738 */
    17721739/** Set if the violation was caused by a data read. */
    1773 #define VMX_EXIT_QUALIFICATION_EPT_DATA_READ                    RT_BIT(0)
     1740#define VMX_EXIT_QUAL_EPT_DATA_READ                    RT_BIT(0)
    17741741/** Set if the violation was caused by a data write. */
    1775 #define VMX_EXIT_QUALIFICATION_EPT_DATA_WRITE                   RT_BIT(1)
     1742#define VMX_EXIT_QUAL_EPT_DATA_WRITE                   RT_BIT(1)
    17761743/** Set if the violation was caused by an instruction fetch. */
    1777 #define VMX_EXIT_QUALIFICATION_EPT_INSTR_FETCH                  RT_BIT(2)
     1744#define VMX_EXIT_QUAL_EPT_INSTR_FETCH                  RT_BIT(2)
    17781745/** AND of the present bit of all EPT structures. */
    1779 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_PRESENT                RT_BIT(3)
     1746#define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT                RT_BIT(3)
    17801747/** AND of the write bit of all EPT structures. */
    1781 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_WRITE                  RT_BIT(4)
     1748#define VMX_EXIT_QUAL_EPT_ENTRY_WRITE                  RT_BIT(4)
    17821749/** AND of the execute bit of all EPT structures. */
    1783 #define VMX_EXIT_QUALIFICATION_EPT_ENTRY_EXECUTE                RT_BIT(5)
     1750#define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE                RT_BIT(5)
    17841751/** Set if the guest linear address field contains the faulting address. */
    1785 #define VMX_EXIT_QUALIFICATION_EPT_GUEST_ADDR_VALID             RT_BIT(7)
     1752#define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID             RT_BIT(7)
    17861753/** If bit 7 is one: (reserved otherwise)
    17871754 *  1 - violation due to physical address access.
    17881755 *  0 - violation caused by page walk or access/dirty bit updates
    17891756 */
    1790 #define VMX_EXIT_QUALIFICATION_EPT_TRANSLATED_ACCESS            RT_BIT(8)
     1757#define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS            RT_BIT(8)
    17911758/** @} */
    17921759
    … …  
    17961763 */
    17971764/** 0-2:   IO operation width. */
    1798 #define VMX_EXIT_QUALIFICATION_IO_WIDTH(a)                      ((a) & 7)
     1765#define VMX_EXIT_QUAL_IO_WIDTH(a)                      ((a) & 7)
    17991766/** 3:     IO operation direction. */
    1800 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION(a)                  (((a) >> 3) & 1)
     1767#define VMX_EXIT_QUAL_IO_DIRECTION(a)                  (((a) >> 3) & 1)
    18011768/** 4:     String IO operation (INS / OUTS). */
    1802 #define VMX_EXIT_QUALIFICATION_IO_IS_STRING(a)                  RT_BOOL((a) & RT_BIT_64(4))
     1769#define VMX_EXIT_QUAL_IO_IS_STRING(a)                  RT_BOOL((a) & RT_BIT_64(4))
    18031770/** 5:     Repeated IO operation. */
    1804 #define VMX_EXIT_QUALIFICATION_IO_IS_REP(a)                     RT_BOOL((a) & RT_BIT_64(5))
     1771#define VMX_EXIT_QUAL_IO_IS_REP(a)                     RT_BOOL((a) & RT_BIT_64(5))
    18051772/** 6:     Operand encoding. */
    1806 #define VMX_EXIT_QUALIFICATION_IO_ENCODING(a)                   (((a) >> 6) & 1)
     1773#define VMX_EXIT_QUAL_IO_ENCODING(a)                   (((a) >> 6) & 1)
    18071774/** 16-31: IO Port (0-0xffff). */
    1808 #define VMX_EXIT_QUALIFICATION_IO_PORT(a)                       (((a) >> 16) & 0xffff)
     1775#define VMX_EXIT_QUAL_IO_PORT(a)                       (((a) >> 16) & 0xffff)
    18091776/* Rest reserved. */
    18101777/** @} */
    18111778
    1812 /** @name VMX_EXIT_QUALIFICATION_IO_DIRECTION
    1813  * @{
    1814  */
    1815 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_OUT                 0
    1816 #define VMX_EXIT_QUALIFICATION_IO_DIRECTION_IN                  1
    1817 /** @} */
    1818 
    1819 
    1820 /** @name VMX_EXIT_QUALIFICATION_IO_ENCODING
    1821  * @{
    1822  */
    1823 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_DX                   0
    1824 #define VMX_EXIT_QUALIFICATION_IO_ENCODING_IMM                  1
    1825 /** @} */
     1779
     1780/** @name VMX_EXIT_QUAL_IO_DIRECTION
     1781 * @{
     1782 */
     1783#define VMX_EXIT_QUAL_IO_DIRECTION_OUT                 0
     1784#define VMX_EXIT_QUAL_IO_DIRECTION_IN                  1
     1785/** @} */
     1786
     1787
     1788/** @name VMX_EXIT_QUAL_IO_ENCODING
     1789 * @{
     1790 */
     1791#define VMX_EXIT_QUAL_IO_ENCODING_DX                   0
     1792#define VMX_EXIT_QUAL_IO_ENCODING_IMM                  1
     1793/** @} */
     1794
    18261795
    18271796/** @name VMX_EXIT_APIC_ACCESS
    … …  
    18291798 */
    18301799/** 0-11:   If the APIC-access VM-exit is due to a linear access, the offset of access within the APIC page. */
    1831 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_OFFSET(a)            ((a) & 0xfff)
     1800#define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a)            ((a) & 0xfff)
    18321801/** 12-15:  Access type. */
    1833 #define VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE(a)              (((a) & 0xf000) >> 12)
     1802#define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a)              (((a) & 0xf000) >> 12)
    18341803/* Rest reserved. */
    18351804/** @} */
    18361805
    18371806
    1838 /** @name VMX_EXIT_QUALIFICATION_APIC_ACCESS_TYPE return values
     1807/** @name VMX_EXIT_QUAL_APIC_ACCESS_TYPE return values
    18391808 * @{
    18401809 */
    … …  
    18521821#define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR                     15
    18531822/** @} */
     1823
    18541824
    18551825/** @name VMX_XDTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information
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