Changeset 72988 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Jul 9, 2018 2:27:49 AM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

123540

Message:

VMM/HMVMXR0, HMSVMR0: Eliminate hidden parameters from a few macros and other minor nits.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (4 diffs)
• HMVMXR0.cpp (modified) (63 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -3116 +3116 @@
 static int hmR0SvmLeaveSession(PVMCPU pVCpu)
 {
-    HM_DISABLE_PREEMPT();
+    HM_DISABLE_PREEMPT(pVCpu);
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -3181 +3181 @@
         VMMRZCallRing3RemoveNotification(pVCpu);
         VMMRZCallRing3Disable(pVCpu);
-        HM_DISABLE_PREEMPT();
+        HM_DISABLE_PREEMPT(pVCpu);
 
         /* Import the entire guest state. */
@@ -6725 +6725 @@
             /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
             VMMRZCallRing3Disable(pVCpu);
-            HM_DISABLE_PREEMPT();
+            HM_DISABLE_PREEMPT(pVCpu);
 
             /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
@@ -6956 +6956 @@
                 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
                 VMMRZCallRing3Disable(pVCpu);
-                HM_DISABLE_PREEMPT();
+                HM_DISABLE_PREEMPT(pVCpu);
 
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatDRxIoCheck);

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -144 +144 @@
 
 /** Assert that preemption is disabled or covered by thread-context hooks. */
-#define HMVMX_ASSERT_PREEMPT_SAFE()                 Assert(   VMMR0ThreadCtxHookIsEnabled(pVCpu)   \
+#define HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu)          Assert(   VMMR0ThreadCtxHookIsEnabled((a_pVCpu))   \
                                                            || !RTThreadPreemptIsEnabled(NIL_RTTHREAD))
 
 /** Assert that we haven't migrated CPUs when thread-context hooks are not
  *  used. */
-#define HMVMX_ASSERT_CPU_SAFE()                     AssertMsg(   VMMR0ThreadCtxHookIsEnabled(pVCpu) \
-                                                              || pVCpu->hm.s.idEnteredCpu == RTMpCpuId(), \
+#define HMVMX_ASSERT_CPU_SAFE(a_pVCpu)              AssertMsg(   VMMR0ThreadCtxHookIsEnabled((a_pVCpu)) \
+                                                              || (a_pVCpu)->hm.s.idEnteredCpu == RTMpCpuId(), \
                                                               ("Illegal migration! Entered on CPU %u Current %u\n", \
-                                                              pVCpu->hm.s.idEnteredCpu, RTMpCpuId()))
+                                                              (a_pVCpu)->hm.s.idEnteredCpu, RTMpCpuId()))
 
 /** Asserts that the given CPUMCTX_EXTRN_XXX bits are present in the guest-CPU
@@ -4991 +4991 @@
     Assert(pVCpu);
     Assert(pVmxTransient);
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
 
     Log4Func(("VM-entry failure: %Rrc\n", rcVMRun));
@@ -6892 +6892 @@
 static int hmR0VmxLeaveSession(PVMCPU pVCpu)
 {
-    HM_DISABLE_PREEMPT();
-    HMVMX_ASSERT_CPU_SAFE();
+    HM_DISABLE_PREEMPT(pVCpu);
+    HMVMX_ASSERT_CPU_SAFE(pVCpu);
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
@@ -6956 +6956 @@
 {
     Assert(pVCpu);
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
 
     if (RT_UNLIKELY(rcExit == VERR_VMX_INVALID_VMCS_PTR))
@@ -7085 +7085 @@
     Assert(pvUser);
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
 
     VMMRZCallRing3Disable(pVCpu);
@@ -7296 +7296 @@
 static VBOXSTRICTRC hmR0VmxInjectPendingEvent(PVMCPU pVCpu, uint32_t fIntrState, bool fStepping)
 {
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
 
@@ -7982 +7982 @@
 {
     AssertPtr(pVCpu);
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
 
     LogFlowFunc(("pVCpu=%p\n", pVCpu));
@@ -8115 +8115 @@
 static VBOXSTRICTRC hmR0VmxExportGuestStateOptimal(PVMCPU pVCpu)
 {
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
     Assert(VMMR0IsLogFlushDisabled(pVCpu));
@@ -8653 +8653 @@
     {
         Assert(!HMR0SuspendPending());
-        HMVMX_ASSERT_CPU_SAFE();
+        HMVMX_ASSERT_CPU_SAFE(pVCpu);
 
         /* Preparatory work for running guest code, this may force us to return
@@ -9757 +9757 @@
     {
         Assert(!HMR0SuspendPending());
-        HMVMX_ASSERT_CPU_SAFE();
+        HMVMX_ASSERT_CPU_SAFE(pVCpu);
         bool fStepping = pVCpu->hm.s.fSingleInstruction;
 
@@ -10022 +10022 @@
     Assert(VMMRZCallRing3IsEnabled(pVCpu));
     Assert(!ASMAtomicUoReadU64(&pCtx->fExtrn));
-    HMVMX_ASSERT_PREEMPT_SAFE();
+    HMVMX_ASSERT_PREEMPT_SAFE(pVCpu);
 
     VMMRZCallRing3SetNotification(pVCpu, hmR0VmxCallRing3Callback, pCtx);
@@ -10153 +10153 @@
     } while (0)
 
-# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
+# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
     do { \
-        AssertPtr(pVCpu); \
-        AssertPtr(pVmxTransient); \
-        Assert(pVmxTransient->fVMEntryFailed == false); \
+        AssertPtr((a_pVCpu)); \
+        AssertPtr((a_pVmxTransient)); \
+        Assert((a_pVmxTransient)->fVMEntryFailed == false); \
         Assert(ASMIntAreEnabled()); \
-        HMVMX_ASSERT_PREEMPT_SAFE(); \
+        HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
         HMVMX_ASSERT_PREEMPT_CPUID_VAR(); \
-        Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", pVCpu->idCpu)); \
-        HMVMX_ASSERT_PREEMPT_SAFE(); \
-        if (VMMR0IsLogFlushDisabled(pVCpu)) \
+        Log4Func(("vcpu[%RU32] -v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v-v\n", (a_pVCpu)->idCpu)); \
+        HMVMX_ASSERT_PREEMPT_SAFE(a_pVCpu); \
+        if (VMMR0IsLogFlushDisabled((a_pVCpu))) \
             HMVMX_ASSERT_PREEMPT_CPUID(); \
         HMVMX_STOP_EXIT_DISPATCH_PROF(); \
     } while (0)
 
-# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() \
+# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
     do { \
         Log4Func(("\n")); \
     } while (0)
-#else /* nonstrict builds: */
-# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS() \
+#else
+# define HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) \
     do { \
         HMVMX_STOP_EXIT_DISPATCH_PROF(); \
-        RT_NOREF2(pVCpu, pVmxTransient); \
+        RT_NOREF2((a_pVCpu), (a_pVmxTransient)); \
     } while (0)
-# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS() do { } while (0)
+# define HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(a_pVCpu, a_pVmxTransient) do { } while (0)
 #endif
 
@@ -10850 +10850 @@
 HMVMX_EXIT_DECL hmR0VmxExitExtInt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitExtInt);
     /* Windows hosts (32-bit and 64-bit) have DPC latency issues. See @bugref{6853}. */
@@ -10864 +10864 @@
 HMVMX_EXIT_DECL hmR0VmxExitXcptOrNmi(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitXcptNmi, y3);
 
@@ -10999 +10999 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitIntWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* Indicate that we no longer need to VM-exit when the guest is ready to receive interrupts, it is now ready. */
@@ -11015 +11015 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitNmiWindow(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)))
     {
@@ -11052 +11052 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitWbinvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
 }
@@ -11062 +11062 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitInvd(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     return hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
 }
@@ -11072 +11072 @@
 HMVMX_EXIT_DECL hmR0VmxExitCpuid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /*
@@ -11127 +11127 @@
 HMVMX_EXIT_DECL hmR0VmxExitGetsec(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc  = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR4);
     AssertRCReturn(rc, rc);
@@ -11144 +11144 @@
 HMVMX_EXIT_DECL hmR0VmxExitRdtsc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
     rc    |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
@@ -11173 +11173 @@
 HMVMX_EXIT_DECL hmR0VmxExitRdtscp(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc = hmR0VmxImportGuestState(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_TSC_AUX);
     rc    |= hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
@@ -11202 +11202 @@
 HMVMX_EXIT_DECL hmR0VmxExitRdpmc(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
     AssertRCReturn(rc, rc);
@@ -11228 +11228 @@
 HMVMX_EXIT_DECL hmR0VmxExitVmcall(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     VBOXSTRICTRC rcStrict = VERR_VMX_IPE_3;
@@ -11271 +11271 @@
 HMVMX_EXIT_DECL hmR0VmxExitInvlpg(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(!pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging || pVCpu->hm.s.fUsingDebugLoop);
 
@@ -11300 +11300 @@
 HMVMX_EXIT_DECL hmR0VmxExitMonitor(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
     AssertRCReturn(rc, rc);
@@ -11324 +11324 @@
 HMVMX_EXIT_DECL hmR0VmxExitMwait(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     int rc = hmR0VmxImportGuestState(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_SS);
     AssertRCReturn(rc, rc);
@@ -11367 +11367 @@
      * See Intel spec. 33.15.5 "Enabling the Dual-Monitor Treatment".
      */
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     AssertMsgFailed(("Unexpected RSM VM-exit\n"));
     HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
@@ -11387 +11387 @@
      * See Intel spec. 25.3 "Other Causes of VM-Exits"
      */
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     AssertMsgFailed(("Unexpected SMI VM-exit\n"));
     HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
@@ -11399 +11399 @@
 {
     /* Same treatment as VMX_EXIT_SMI. See comment in hmR0VmxExitSmi(). */
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     AssertMsgFailed(("Unexpected IO SMI VM-exit\n"));
     HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
@@ -11415 +11415 @@
      * See Intel spec. 25.3 "Other Causes of VM-exits".
      */
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     AssertMsgFailed(("Unexpected SIPI VM-exit\n"));
     HMVMX_UNEXPECTED_EXIT_RET(pVCpu, pVmxTransient);
@@ -11434 +11434 @@
      * See Intel spec. "23.8 Restrictions on VMX operation".
      */
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     return VINF_SUCCESS;
 }
@@ -11445 +11445 @@
 HMVMX_EXIT_DECL hmR0VmxExitTripleFault(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     return VINF_EM_RESET;
 }
@@ -11455 +11455 @@
 HMVMX_EXIT_DECL hmR0VmxExitHlt(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
 
@@ -11480 +11480 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitSetPendingXcptUD(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     hmR0VmxSetPendingXcptUD(pVCpu);
     return VINF_SUCCESS;
@@ -11491 +11491 @@
 HMVMX_EXIT_DECL hmR0VmxExitPreemptTimer(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* If the preemption-timer has expired, reinitialize the preemption timer on next VM-entry. */
@@ -11509 +11509 @@
 HMVMX_EXIT_DECL hmR0VmxExitXsetbv(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
@@ -11531 +11531 @@
 HMVMX_EXIT_DECL hmR0VmxExitInvpcid(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     /** @todo Use VM-exit instruction information. */
     return VERR_EM_INTERPRETER;
@@ -11633 +11633 @@
 HMVMX_EXIT_DECL hmR0VmxExitXdtrAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
@@ -11649 +11649 @@
 HMVMX_EXIT_DECL hmR0VmxExitRdrand(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
@@ -11664 +11664 @@
 HMVMX_EXIT_DECL hmR0VmxExitRdmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /** @todo Optimize this: We currently drag in in the whole MSR state
@@ -11723 +11723 @@
 HMVMX_EXIT_DECL hmR0VmxExitWrmsr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /** @todo Optimize this: We currently drag in in the whole MSR state
@@ -11853 +11853 @@
 HMVMX_EXIT_DECL hmR0VmxExitPause(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     /** @todo The guest has likely hit a contended spinlock. We might want to
      *        poke a schedule different guest VCPU. */
@@ -11866 +11866 @@
 HMVMX_EXIT_NSRC_DECL hmR0VmxExitTprBelowThreshold(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
 
@@ -11890 +11890 @@
 HMVMX_EXIT_DECL hmR0VmxExitMovCRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitMovCRx, y2);
 
@@ -11899 +11899 @@
 
     VBOXSTRICTRC rcStrict;
-    PVM      pVM  = pVCpu->CTX_SUFF(pVM);
+    PVM pVM  = pVCpu->CTX_SUFF(pVM);
     RTGCUINTPTR const uExitQualification = pVmxTransient->uExitQualification;
     uint32_t const uAccessType           = VMX_EXIT_QUAL_CRX_ACCESS(uExitQualification);
@@ -12055 +12055 @@
 HMVMX_EXIT_DECL hmR0VmxExitIoInstr(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_PROFILE_ADV_START(&pVCpu->hm.s.StatExitIO, y1);
 
@@ -12214 +12214 @@
                 /* We're playing with the host CPU state here, make sure we don't preempt or longjmp. */
                 VMMRZCallRing3Disable(pVCpu);
-                HM_DISABLE_PREEMPT();
+                HM_DISABLE_PREEMPT(pVCpu);
 
                 bool fIsGuestDbgActive = CPUMR0DebugStateMaybeSaveGuest(pVCpu, true /* fDr6 */);
@@ -12294 +12294 @@
 HMVMX_EXIT_DECL hmR0VmxExitTaskSwitch(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* Check if this task-switch occurred while delivery an event through the guest IDT. */
@@ -12345 +12345 @@
 HMVMX_EXIT_DECL hmR0VmxExitMtf(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
     pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
@@ -12360 +12360 @@
 HMVMX_EXIT_DECL hmR0VmxExitApicAccess(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitApicAccess);
@@ -12440 +12440 @@
 HMVMX_EXIT_DECL hmR0VmxExitMovDRx(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /* We should -not- get this VM-exit if the guest's debug registers were active. */
@@ -12462 +12462 @@
         /* We're playing with the host CPU state here, make sure we can't preempt or longjmp. */
         VMMRZCallRing3Disable(pVCpu);
-        HM_DISABLE_PREEMPT();
+        HM_DISABLE_PREEMPT(pVCpu);
 
         /* Save the host & load the guest debug state, restart execution of the MOV DRx instruction. */
@@ -12528 +12528 @@
 HMVMX_EXIT_DECL hmR0VmxExitEptMisconfig(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
 
@@ -12613 +12613 @@
 HMVMX_EXIT_DECL hmR0VmxExitEptViolation(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     Assert(pVCpu->CTX_SUFF(pVM)->hm.s.fNestedPaging);
 
@@ -12691 +12691 @@
 static int hmR0VmxExitXcptMF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestMF);
 
@@ -12721 +12721 @@
 static int hmR0VmxExitXcptBP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestBP);
 
@@ -12750 +12750 @@
 static int hmR0VmxExitXcptAC(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
     /*
@@ -12771 +12771 @@
 static int hmR0VmxExitXcptDB(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestDB);
 
@@ -12796 +12796 @@
          */
         VMMRZCallRing3Disable(pVCpu);
-        HM_DISABLE_PREEMPT();
+        HM_DISABLE_PREEMPT(pVCpu);
 
         pCtx->dr[6] &= ~X86_DR6_B_MASK;
@@ -12857 +12857 @@
 static int hmR0VmxExitXcptGP(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitGuestGP);
 
@@ -13159 +13159 @@
 static int hmR0VmxExitXcptGeneric(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 #ifndef HMVMX_ALWAYS_TRAP_ALL_XCPTS
     AssertMsg(pVCpu->hm.s.fUsingDebugLoop || pVCpu->hm.s.vmx.RealMode.fRealOnV86Active,
@@ -13190 +13190 @@
 static int hmR0VmxExitXcptPF(PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
 {
-    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS();
+    HMVMX_VALIDATE_EXIT_XCPT_HANDLER_PARAMS(pVCpu, pVmxTransient);
     PVM pVM = pVCpu->CTX_SUFF(pVM);
     int rc = hmR0VmxReadExitQualificationVmcs(pVCpu, pVmxTransient);