Changeset 73243 in vbox for trunk/src/VBox/Devices/Serial

Timestamp:

Jul 19, 2018 3:08:34 PM (7 years ago)

Author:

vboxsync

Message:

Devices/Serial: Add missing implementation for character timeout indication when the FIFO is enabled, add 16750 implementation which provides 64byte FIFOs, additional number of bug fixes

Location:

trunk/src/VBox/Devices/Serial

Files:

• DevSerialNew.cpp (modified) (4 diffs)
• DrvCharNew.cpp (modified) (1 diff)
• DrvHostSerialNew.cpp (modified) (1 diff)
• UartCore.cpp (modified) (39 diffs)
• UartCore.h (modified) (7 diffs)

trunk/src/VBox/Devices/Serial/DevSerialNew.cpp

@@ -125 +125 @@
 
 
+/**
+ * Returns the matching UART type from the given string.
+ *
+ * @returns UART type based on the given string or UARTTYPE_INVALID if an invalid type was passed.
+ * @param   pszUartType         The UART type.
+ */
+static UARTTYPE serialR3GetUartTypeFromString(const char *pszUartType)
+{
+    if (!RTStrCmp(pszUartType, "15450"))
+        return UARTTYPE_16450;
+    else if (!RTStrCmp(pszUartType, "15550A"))
+        return UARTTYPE_16550A;
+    else if (!RTStrCmp(pszUartType, "16750"))
+        return UARTTYPE_16750;
+
+    AssertLogRelMsgFailedReturn(("Unknown UART type \"%s\" specified", pszUartType),
+                                UARTTYPE_INVALID);
+}
+
+
 /* -=-=-=-=-=-=-=-=- PDMDEVREG -=-=-=-=-=-=-=-=- */
 
@@ -209 +229 @@
                                     "R0Enabled\0"
                                     "YieldOnLSRRead\0"
-                                    "Enable16550A\0"
+                                    "UartType\0"
                                     ))
     {
@@ -263 +283 @@
                                 N_("Configuration error: Failed to get the \"IOBase\" value"));
 
-    bool f16550AEnabled = true;
-    rc = CFGMR3QueryBoolDef(pCfg, "Enable16550A", &f16550AEnabled, true);
-    if (RT_FAILURE(rc))
-        return PDMDEV_SET_ERROR(pDevIns, rc,
-                                N_("Configuration error: Failed to get the \"Enable16550A\" value"));
+    char *pszUartType;
+    rc = CFGMR3QueryStringAllocDef(pCfg, "UartType", &pszUartType, "16550A");
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: failed to read \"UartType\" as string"));
+
+    UARTTYPE enmUartType = serialR3GetUartTypeFromString(pszUartType);
+
+    if (enmUartType != UARTTYPE_INVALID)
+        LogRel(("Serial#%d: emulating %s (IOBase: %04x IRQ: %u)\n",
+                pDevIns->iInstance, pszUartType, uIoBase, uIrq));
+
+    MMR3HeapFree(pszUartType);
+
+    if (enmUartType == UARTTYPE_INVALID)
+        return PDMDEV_SET_ERROR(pDevIns, VERR_INVALID_PARAMETER,
+                                N_("Configuration error: \"UartType\" contains invalid type"));
 
     pThis->uIrq     = uIrq;
     pThis->PortBase = uIoBase;
-
-    LogRel(("Serial#%d: emulating %s (IOBase: %04x IRQ: %u)\n",
-            pDevIns->iInstance, f16550AEnabled ? "16550A" : "16450", uIoBase, uIrq));
 
     /*
@@ -330 +359 @@
 
     /* Init the UART core structure. */
-    rc = uartR3Init(&pThis->UartCore, pDevIns, f16550AEnabled ? UARTTYPE_16550A : UARTTYPE_16450, 0,
+    rc = uartR3Init(&pThis->UartCore, pDevIns, enmUartType, 0,
                     fYieldOnLSRRead ? UART_CORE_YIELD_ON_LSR_READ : 0, serialIrqReq, pfnSerialIrqReqR0, pfnSerialIrqReqRC);
 

trunk/src/VBox/Devices/Serial/DrvCharNew.cpp

@@ -231 +231 @@
                     AssertRC(rc);
 
-                    ASMAtomicSubZ(&pThis->cbAvailWr, cbFetched);
-                    pThis->cbTxUsed += cbFetched;
+                    if (cbFetched > 0)
+                    {
+                        ASMAtomicSubZ(&pThis->cbAvailWr, cbFetched);
+                        pThis->cbTxUsed += cbFetched;
+                    }
+                    else
+                    {
+                        /* The guest reset the send queue and there is no data available anymore. */
+                        pThis->cbAvailWr = 0;
+                    }
                 }
 

trunk/src/VBox/Devices/Serial/DrvHostSerialNew.cpp

@@ -400 +400 @@
                     AssertRC(rc);
 
-                    ASMAtomicSubZ(&pThis->cbAvailWr, cbFetched);
-                    pThis->cbTxUsed += cbFetched;
-                }
-
-                size_t cbProcessed = 0;
-                rc = RTSerialPortWriteNB(pThis->hSerialPort, &pThis->abTxBuf[0], pThis->cbTxUsed, &cbProcessed);
-                if (RT_SUCCESS(rc))
-                {
-                    pThis->cbTxUsed -= cbProcessed;
-                    if (pThis->cbTxUsed)
+                    if (cbFetched > 0)
                     {
-                        /* Move the data in the TX buffer to the front to fill the end again. */
-                        memmove(&pThis->abTxBuf[0], &pThis->abTxBuf[cbProcessed], pThis->cbTxUsed);
+                        ASMAtomicSubZ(&pThis->cbAvailWr, cbFetched);
+                        pThis->cbTxUsed += cbFetched;
                     }
                     else
-                        pThis->pDrvSerialPort->pfnDataSentNotify(pThis->pDrvSerialPort);
-                    STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbProcessed);
+                    {
+                        /* The guest reset the send queue and there is no data available anymore. */
+                        pThis->cbAvailWr = 0;
+                    }
                 }
-                else
+
+                if (pThis->cbTxUsed)
                 {
-                    LogRelMax(10, ("HostSerial#%d: Sending data failed even though the serial port is marked as writeable (rc=%Rrc)\n",
-                                   pThis->pDrvIns->iInstance, rc));
-                    break;
+                    size_t cbProcessed = 0;
+                    rc = RTSerialPortWriteNB(pThis->hSerialPort, &pThis->abTxBuf[0], pThis->cbTxUsed, &cbProcessed);
+                    if (RT_SUCCESS(rc))
+                    {
+                        pThis->cbTxUsed -= cbProcessed;
+                        if (pThis->cbTxUsed)
+                        {
+                            /* Move the data in the TX buffer to the front to fill the end again. */
+                            memmove(&pThis->abTxBuf[0], &pThis->abTxBuf[cbProcessed], pThis->cbTxUsed);
+                        }
+                        else
+                            pThis->pDrvSerialPort->pfnDataSentNotify(pThis->pDrvSerialPort);
+                        STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbProcessed);
+                    }
+                    else
+                    {
+                        LogRelMax(10, ("HostSerial#%d: Sending data failed even though the serial port is marked as writeable (rc=%Rrc)\n",
+                                       pThis->pDrvIns->iInstance, rc));
+                        break;
+                    }
                 }
             }

trunk/src/VBox/Devices/Serial/UartCore.cpp

@@ -23 +23 @@
 *********************************************************************************************************************************/
 #define LOG_GROUP LOG_GROUP_DEV_SERIAL
+#include <VBox/vmm/tm.h>
 #include <iprt/uuid.h>
 #include <iprt/assert.h>
@@ -50 +51 @@
 /** Enable modem status interrupt. */
 # define UART_REG_IER_EDSSI                  RT_BIT(3)
+/** Sleep mode enable. */
+# define UART_REG_IER_SLEEP_MODE_EN          RT_BIT(4)
+/** Low power mode enable. */
+# define UART_REG_IER_LP_MODE_EN             RT_BIT(5)
 /** Mask of writeable bits. */
 # define UART_REG_IER_MASK_WR                0x0f
+/** Mask of writeable bits for 16750+. */
+# define UART_REG_IER_MASK_WR_16750          0x3f
 
 /** The IIR register index (from the base of the port range). */
@@ -71 +78 @@
 /** Modem Status interrupt. */
 #  define UART_REG_IIR_ID_MS                 0x0
+/** 64 byte FIFOs enabled (15750+ only). */
+# define UART_REG_IIR_64BYTE_FIFOS_EN        RT_BIT(5)
 /** FIFOs enabled. */
 # define UART_REG_IIR_FIFOS_EN               0xc0
@@ -86 +95 @@
 /** DMA Mode Select. */
 # define UART_REG_FCR_DMA_MODE_SEL           RT_BIT(3)
+/** 64 Byte FIFO enable (15750+ only). */
+# define UART_REG_FCR_64BYTE_FIFO_EN         RT_BIT(5)
 /** Receiver level interrupt trigger. */
 # define UART_REG_FCR_RCV_LVL_IRQ_MASK       0xc0
@@ -101 +112 @@
 # define UART_REG_FCR_MASK_WR                0xcf
 /** Mask of sticky bits. */
-# define UART_REG_FCR_MASK_STICKY            0xc9
+# define UART_REG_FCR_MASK_STICKY            0xe9
 
 /** The LCR register index (from the base of the port range). */
@@ -134 +145 @@
 /** Loopback connection. */
 # define UART_REG_MCR_LOOP                   RT_BIT(4)
-/** Mask of writeable bits. */
+/** Flow Control Enable (15750+ only). */
+# define UART_REG_MCR_AFE                    RT_BIT(5)
+/** Mask of writeable bits (15450 and 15550A). */
 # define UART_REG_MCR_MASK_WR                0x1f
+/** Mask of writeable bits (15750+). */
+# define UART_REG_MCR_MASK_WR_15750          0x3f
 
 /** The LSR register index (from the base of the port range). */
@@ -198 +213 @@
 *   Global Variables                                                                                                             *
 *********************************************************************************************************************************/
+
 #ifdef IN_RING3
+/**
+ * FIFO ITL levels.
+ */
+static struct
+{
+    /** ITL level for a 16byte FIFO. */
+    uint8_t                     cbItl16;
+    /** ITL level for a 64byte FIFO. */
+    uint8_t                     cbItl64;
+} s_aFifoItl[] =
+{
+    /* cbItl16     cbItl64 */
+    {     1,          1    },
+    {     4,         16    },
+    {     8,         32    },
+    {    14,         56    }
+};
+
+
 /**
  * String versions of the parity enum.
@@ -258 +293 @@
         && (pThis->uRegIer & UART_REG_IER_ELSI))
         uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RCL);
+    else if (   (pThis->uRegIer & UART_REG_IER_ERBFI)
+             && pThis->fIrqCtiPending)
+        uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_CTI);
     else if (   (pThis->uRegLsr & UART_REG_LSR_DR)
              && (pThis->uRegIer & UART_REG_IER_ERBFI)
@@ -270 +308 @@
         uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_MS);
 
-    /** @todo Character timeout indication for FIFO mode. */
-
     LogFlowFunc(("    uRegIirNew=%#x uRegIir=%#x\n", uRegIirNew, pThis->uRegIir));
 
@@ -291 +327 @@
     if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
         uRegIirNew |= UART_REG_IIR_FIFOS_EN;
+    if (pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN)
+        uRegIirNew |= UART_REG_IIR_64BYTE_FIFOS_EN;
 
     pThis->uRegIir = uRegIirNew;
@@ -319 +357 @@
 DECLINLINE(size_t) uartFifoFreeGet(PUARTFIFO pFifo)
 {
-    return UART_FIFO_LENGTH - pFifo->cbUsed;
+    return pFifo->cbMax - pFifo->cbUsed;
 }
 
@@ -333 +371 @@
 DECLINLINE(bool) uartFifoPut(PUARTFIFO pFifo, bool fOvrWr, uint8_t bData)
 {
-    if (fOvrWr || pFifo->cbUsed < UART_FIFO_LENGTH)
+    if (fOvrWr || pFifo->cbUsed < pFifo->cbMax)
     {
         pFifo->abBuf[pFifo->offWrite] = bData;
-        pFifo->offWrite = (pFifo->offWrite + 1) % UART_FIFO_LENGTH;
+        pFifo->offWrite = (pFifo->offWrite + 1) % pFifo->cbMax;
     }
 
     bool fOverFlow = false;
-    if (pFifo->cbUsed < UART_FIFO_LENGTH)
+    if (pFifo->cbUsed < pFifo->cbMax)
         pFifo->cbUsed++;
     else
@@ -346 +384 @@
         fOverFlow = true;
         if (fOvrWr) /* Advance the read position to account for the lost character. */
-           pFifo->offRead = (pFifo->offRead + 1) % UART_FIFO_LENGTH;
+           pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
     }
 
@@ -366 +404 @@
     {
         bRet = pFifo->abBuf[pFifo->offRead];
-        pFifo->offRead = (pFifo->offRead + 1) % UART_FIFO_LENGTH;
+        pFifo->offRead = (pFifo->offRead + 1) % pFifo->cbMax;
         pFifo->cbUsed--;
     }
@@ -390 +428 @@
     while (cbCopy)
     {
-        size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(UART_FIFO_LENGTH - pFifo->offRead));
+        size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offRead));
         memcpy(pbDst, &pFifo->abBuf[pFifo->offRead], cbThisCopy);
 
-        pFifo->offRead = (pFifo->offRead + cbThisCopy) % UART_FIFO_LENGTH;
+        pFifo->offRead = (pFifo->offRead + cbThisCopy) % pFifo->cbMax;
         pFifo->cbUsed -= cbThisCopy;
         pbDst    += cbThisCopy;
@@ -420 +458 @@
     while (cbCopy)
     {
-        size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(UART_FIFO_LENGTH - pFifo->offWrite));
+        size_t cbThisCopy = RT_MIN(cbCopy, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
         memcpy(&pFifo->abBuf[pFifo->offWrite], pbSrc, cbThisCopy);
 
-        pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % UART_FIFO_LENGTH;
+        pFifo->offWrite = (pFifo->offWrite + cbThisCopy) % pFifo->cbMax;
         pFifo->cbUsed += cbThisCopy;
         pbSrc    += cbThisCopy;
@@ -474 +512 @@
         uint32_t uBps = 115200 / pThis->uRegDivisor; /* This is for PC compatible serial port with a 1.8432 MHz crystal. */
         unsigned cDataBits = UART_REG_LCR_WLS_GET(pThis->uRegLcr) + 5;
+        uint32_t cFrameBits = cDataBits;
         PDMSERIALSTOPBITS enmStopBits = PDMSERIALSTOPBITS_ONE;
         PDMSERIALPARITY enmParity = PDMSERIALPARITY_NONE;
@@ -480 +519 @@
         {
             enmStopBits = cDataBits == 5 ? PDMSERIALSTOPBITS_ONEPOINTFIVE : PDMSERIALSTOPBITS_TWO;
+            cFrameBits += 2;
         }
+        else
+            cFrameBits++;
 
         if (pThis->uRegLcr & UART_REG_LCR_PEN)
@@ -504 +546 @@
                                      pThis->uRegLcr & (UART_REG_LCR_EPS | UART_REG_LCR_PAR_STICK)));
             }
+
+            cFrameBits++;
         }
+
+        uint64_t uTimerFreq = TMTimerGetFreq(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
+        pThis->cSymbolXferTicks = (uTimerFreq / uBps) * cFrameBits;
 
         LogFlowFunc(("Changing parameters to: %u,%s,%u,%s\n",
@@ -513 +560 @@
             LogRelMax(10, ("Serial#%d: Failed to change parameters to %u,%s,%u,%s -> %Rrc\n",
                            pThis->pDevInsR3->iInstance, uBps, s_aszParity[enmParity], cDataBits, s_aszStopBits[enmStopBits], rc));
+
+        /* Changed parameters will flush all receive queues, so there won't be any data to read even if indicated. */
+        ASMAtomicWriteU32(&pThis->cbAvailRdr, 0);
+        UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
     }
 }
@@ -558 +609 @@
     while (cbFilled < cbFill)
     {
-        size_t cbThisRead = RT_MIN(cbFill, (uint8_t)(UART_FIFO_LENGTH - pFifo->offWrite));
+        size_t cbThisRead = RT_MIN(cbFill - cbFilled, (uint8_t)(pFifo->cbMax - pFifo->offWrite));
         size_t cbRead = 0;
         int rc = pThis->pDrvSerial->pfnReadRdr(pThis->pDrvSerial, &pFifo->abBuf[pFifo->offWrite], cbThisRead, &cbRead);
         /*Assert(RT_SUCCESS(rc) && cbRead == cbThisRead);*/ RT_NOREF(rc);
 
-        pFifo->offWrite = (pFifo->offWrite + cbRead) % UART_FIFO_LENGTH;
+        pFifo->offWrite = (pFifo->offWrite + cbRead) % pFifo->cbMax;
         pFifo->cbUsed   += cbRead;
         cbFilled        += cbRead;
@@ -577 +628 @@
     }
 
+    Assert(cbFilled <= pThis->cbAvailRdr);
     ASMAtomicSubU32(&pThis->cbAvailRdr, cbFilled);
 }
@@ -609 +661 @@
 static void uartR3DataFetch(PUARTCORE pThis)
 {
-    if (pThis->uRegFcr % UART_REG_FCR_FIFO_EN)
+    if (pThis->uRegFcr & UART_REG_FCR_FIFO_EN)
         uartR3RecvFifoFill(pThis);
     else
@@ -713 +765 @@
     else
     {
-        pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
+        if (pThis->enmType < UARTTYPE_16750)
+            pThis->uRegIer = uVal & UART_REG_IER_MASK_WR;
+        else
+            pThis->uRegIer = uVal & UART_REG_IER_MASK_WR_16750;
         uartIrqUpdate(pThis);
     }
@@ -730 +785 @@
 DECLINLINE(int) uartRegFcrWrite(PUARTCORE pThis, uint8_t uVal)
 {
+#ifndef IN_RING3
+    RT_NOREF(pThis, uVal);
+    return VINF_IOM_R3_IOPORT_WRITE;
+#else
     int rc = VINF_SUCCESS;
-
     if (   pThis->enmType >= UARTTYPE_16550A
         && uVal != pThis->uRegFcr)
@@ -741 +799 @@
             uartFifoClear(&pThis->FifoRecv);
 
-            /* Fill in the next data. */
-            if (ASMAtomicReadU32(&pThis->cbAvailRdr))
-            {
-#ifndef IN_RING3
-                rc = VINF_IOM_R3_IOPORT_WRITE;
-#else
-                uartR3DataFetch(pThis);
-#endif
-            }
+            /*
+             * If the FIFO is about to be enabled and the DR bit is ready we have an unacknowledged
+             * byte in the RBR register which will be lost so we have to adjust the available bytes.
+             */
+            if (   ASMAtomicReadU32(&pThis->cbAvailRdr) > 0
+                && (pThis->uRegFcr & UART_REG_FCR_FIFO_EN))
+                ASMAtomicDecU32(&pThis->cbAvailRdr);
+
+            /* Clear the DR bit too. */
+            UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
         }
 
@@ -755 +814 @@
         {
             if (uVal & UART_REG_FCR_RCV_FIFO_RST)
+            {
+                TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
+                pThis->fIrqCtiPending = false;
                 uartFifoClear(&pThis->FifoRecv);
+            }
             if (uVal & UART_REG_FCR_XMIT_FIFO_RST)
                 uartFifoClear(&pThis->FifoXmit);
 
+            /*
+             * The 64byte FIFO enable bit is only changeable for 16750
+             * and if the DLAB bit in LCR is set.
+             */
+            if (   pThis->enmType < UARTTYPE_16750
+                || !(pThis->uRegLcr & UART_REG_LCR_DLAB))
+                uVal &= ~UART_REG_FCR_64BYTE_FIFO_EN;
+            else /* Use previous value. */
+                uVal |= pThis->uRegFcr & UART_REG_FCR_64BYTE_FIFO_EN;
+
+            if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
+            {
+                pThis->FifoRecv.cbMax = 64;
+                pThis->FifoXmit.cbMax = 64;
+            }
+            else
+            {
+                pThis->FifoRecv.cbMax = 16;
+                pThis->FifoXmit.cbMax = 16;
+            }
+
             if (uVal & UART_REG_FCR_FIFO_EN)
             {
-                switch (UART_REG_FCR_RCV_LVL_IRQ_GET(uVal))
-                {
-                    case UART_REG_FCR_RCV_LVL_IRQ_1:
-                        pThis->FifoRecv.cbItl = 1;
-                        break;
-                    case UART_REG_FCR_RCV_LVL_IRQ_4:
-                        pThis->FifoRecv.cbItl = 4;
-                        break;
-                    case UART_REG_FCR_RCV_LVL_IRQ_8:
-                        pThis->FifoRecv.cbItl = 8;
-                        break;
-                    case UART_REG_FCR_RCV_LVL_IRQ_14:
-                        pThis->FifoRecv.cbItl = 14;
-                        break;
-                    default:
-                        /* Should never occur as all cases are handled earlier. */
-                        AssertMsgFailed(("Impossible to hit!\n"));
-                }
+                uint8_t idxItl = UART_REG_FCR_RCV_LVL_IRQ_GET(uVal);
+                if (uVal & UART_REG_FCR_64BYTE_FIFO_EN)
+                    pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl64;
+                else
+                    pThis->FifoRecv.cbItl = s_aFifoItl[idxItl].cbItl16;
             }
 
@@ -785 +856 @@
             uartIrqUpdate(pThis);
         }
+
+        /* Fill in the next data. */
+        if (ASMAtomicReadU32(&pThis->cbAvailRdr))
+            uartR3DataFetch(pThis);
     }
 
     return rc;
+#endif
 }
 
@@ -837 +913 @@
     int rc = VINF_SUCCESS;
 
-    uVal &= UART_REG_MCR_MASK_WR;
+    if (pThis->enmType < UARTTYPE_16750)
+        uVal &= UART_REG_MCR_MASK_WR;
+    else
+        uVal &= UART_REG_MCR_MASK_WR_15750;
     if (pThis->uRegMcr != uVal)
     {
@@ -913 +992 @@
             {
                 *puVal = uartFifoGet(&pThis->FifoRecv);
+                pThis->fIrqCtiPending = false;
                 if (!pThis->FifoRecv.cbUsed)
+                {
+                    TMTimerStop(pThis->CTX_SUFF(pTimerRcvFifoTimeout));
                     UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_DR);
+                }
+                else
+                {
+                    uint64_t tsCtiFire = TMTimerGet(pThis->CTX_SUFF(pTimerRcvFifoTimeout)) + pThis->cSymbolXferTicks * 4;
+                    TMTimerSet(pThis->CTX_SUFF(pTimerRcvFifoTimeout), tsCtiFire);
+                }
                 uartIrqUpdate(pThis);
             }
@@ -924 +1012 @@
             if (pThis->uRegLsr & UART_REG_LSR_DR)
             {
+                Assert(pThis->cbAvailRdr);
                 uint32_t cbAvail = ASMAtomicDecU32(&pThis->cbAvailRdr);
                 if (!cbAvail)
@@ -1097 +1186 @@
 DECLHIDDEN(int) uartRegWrite(PUARTCORE pThis, uint32_t uReg, uint32_t u32, size_t cb)
 {
+    AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
+
     int rc = PDMCritSectEnter(&pThis->CritSect, VINF_IOM_R3_IOPORT_WRITE);
     if (rc != VINF_SUCCESS)
@@ -1104 +1195 @@
     LogFlowFunc(("pThis=%#p uReg=%u{%s} u32=%#x cb=%u\n",
                  pThis, uReg, uartRegIdx2Str(pThis, idxReg, true /*fWrite*/), u32, cb));
-
-    AssertMsgReturn(cb == 1, ("uReg=%#x cb=%d u32=%#x\n", uReg, cb, u32), VINF_SUCCESS);
 
     uint8_t uVal = (uint8_t)u32;
@@ -1186 +1275 @@
 
 #ifdef IN_RING3
+
+/* -=-=-=-=-=-=-=-=- Timer callbacks -=-=-=-=-=-=-=-=- */
+
+/**
+ * @callback_method_impl{FNTMTIMERDEV, Fifo timer function.}
+ */
+static DECLCALLBACK(void) uartR3RcvFifoTimeoutTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
+{
+    RT_NOREF(pDevIns, pTimer);
+    PUARTCORE pThis = (PUARTCORE)pvUser;
+    Assert(PDMCritSectIsOwner(&pThis->CritSect));
+    if (pThis->FifoRecv.cbUsed)
+    {
+        pThis->fIrqCtiPending = true;
+        uartIrqUpdate(pThis);
+    }
+}
+
 
 /* -=-=-=-=-=-=-=-=- PDMISERIALPORT on LUN#0 -=-=-=-=-=-=-=-=- */
@@ -1266 +1373 @@
     else
     {
-        AssertMsgFailed(("There is no data to read!\n"));
+        /*
+         * This can happen if there was data in the FIFO when the connection was closed,
+         * idicate this condition to the lower driver by returning 0 bytes.
+         */
         *pcbRead = 0;
     }
@@ -1324 +1434 @@
 {
     RT_NOREF(offDelta);
-    pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
+    pThis->pDevInsRC              = PDMDEVINS_2_RCPTR(pThis->pDevInsR3);
+    pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
 }
 
@@ -1330 +1441 @@
 DECLHIDDEN(void) uartR3Reset(PUARTCORE pThis)
 {
-    pThis->uRegDivisor = 0x0c; /* Default to 9600 Baud. */
-    pThis->uRegRbr     = 0;
-    pThis->uRegThr     = 0;
-    pThis->uRegIer     = 0;
-    pThis->uRegIir     = UART_REG_IIR_IP_NO_INT;
-    pThis->uRegFcr     = 0;
-    pThis->uRegLcr     = 0; /* 5 data bits, no parity, 1 stop bit. */
-    pThis->uRegMcr     = 0;
-    pThis->uRegLsr     = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
-    pThis->uRegMsr     = 0; /* Updated below. */
-    pThis->uRegScr     = 0;
-
+    pThis->uRegDivisor    = 0x0c; /* Default to 9600 Baud. */
+    pThis->uRegRbr        = 0;
+    pThis->uRegThr        = 0;
+    pThis->uRegIer        = 0;
+    pThis->uRegIir        = UART_REG_IIR_IP_NO_INT;
+    pThis->uRegFcr        = 0;
+    pThis->uRegLcr        = 0; /* 5 data bits, no parity, 1 stop bit. */
+    pThis->uRegMcr        = 0;
+    pThis->uRegLsr        = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
+    pThis->uRegMsr        = 0; /* Updated below. */
+    pThis->uRegScr        = 0;
+    pThis->fIrqCtiPending = false;
+
+    /* Standard FIFO size for 15550A. */
+    pThis->FifoXmit.cbMax = 16;
+    pThis->FifoRecv.cbMax = 16;
     uartFifoClear(&pThis->FifoXmit);
     uartFifoClear(&pThis->FifoRecv);
@@ -1438 +1553 @@
     pThis->ISerialPort.pfnNotifyBrk             = uartR3NotifyBrk;
 
-    rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Serial#%d", iLUN);
+    rc = PDMDevHlpCritSectInit(pDevInsR3, &pThis->CritSect, RT_SRC_POS, "Uart{%s#%d}#%d",
+                               pDevInsR3->pReg->szName, pDevInsR3->iInstance, iLUN);
     AssertRCReturn(rc, rc);
 
@@ -1467 +1583 @@
     }
 
+    /*
+     * Create the receive FIFO character timeout indicator timer.
+     */
+    rc = PDMDevHlpTMTimerCreate(pDevInsR3, TMCLOCK_VIRTUAL, uartR3RcvFifoTimeoutTimer, pThis,
+                                TMTIMER_FLAGS_NO_CRIT_SECT, "UART Rcv FIFO Timer",
+                                &pThis->pTimerRcvFifoTimeoutR3);
+    AssertRCReturn(rc, rc);
+
+    rc = TMR3TimerSetCritSect(pThis->pTimerRcvFifoTimeoutR3, &pThis->CritSect);
+    AssertRCReturn(rc, rc);
+
+    pThis->pTimerRcvFifoTimeoutR0 = TMTimerR0Ptr(pThis->pTimerRcvFifoTimeoutR3);
+    pThis->pTimerRcvFifoTimeoutRC = TMTimerRCPtr(pThis->pTimerRcvFifoTimeoutR3);
+
     uartR3Reset(pThis);
     return VINF_SUCCESS;

trunk/src/VBox/Devices/Serial/UartCore.h

@@ -20 +20 @@
 #define ___UartCore_h
 
+#include <VBox/types.h>
 #include <VBox/vmm/pdmdev.h>
 #include <VBox/vmm/pdmserialifs.h>
@@ -30 +31 @@
 *********************************************************************************************************************************/
 
-/** Size of a FIFO. */
-#define UART_FIFO_LENGTH                     16
+/** Maximum size of a FIFO. */
+#define UART_FIFO_LENGTH_MAX                 128
 
 
@@ -67 +68 @@
     /** 16550A UART type. */
     UARTTYPE_16550A,
-    /** 32bit hack. */
+    /** 16750 UART type. */
+    UARTTYPE_16750,
+        /** 32bit hack. */
     UARTTYPE_32BIT_HACK = 0x7fffffff
 } UARTTYPE;
@@ -77 +80 @@
 typedef struct UARTFIFO
 {
+    /** Fifo size configured. */
+    uint8_t                         cbMax;
     /** Current amount of bytes used. */
     uint8_t                         cbUsed;
@@ -86 +91 @@
     uint8_t                         cbItl;
     /** The data in the FIFO. */
-    uint8_t                         abBuf[UART_FIFO_LENGTH];
+    uint8_t                         abBuf[UART_FIFO_LENGTH_MAX];
+    /** Alignment to a 4 byte boundary. */
+    uint8_t                         au8Alignment0[3];
 } UARTFIFO;
 /** Pointer to a FIFO. */
@@ -123 +130 @@
     UARTTYPE                        enmType;
 
+    /** R3 timer pointer fo the character timeout indication. */
+    PTMTIMERR3                      pTimerRcvFifoTimeoutR3;
     /** R3 interrupt request callback of the owning device. */
     R3PTRTYPE(PFNUARTCOREIRQREQ)    pfnUartIrqReqR3;
+    /** R0 timer pointer fo the character timeout indication. */
+    PTMTIMERR0                      pTimerRcvFifoTimeoutR0;
     /** R0 interrupt request callback of the owning device. */
     R0PTRTYPE(PFNUARTCOREIRQREQ)    pfnUartIrqReqR0;
-    /** RC interrupt request callback of the owning device. */
+    /** RC timer pointer fo the character timeout indication. */
+    PTMTIMERRC                      pTimerRcvFifoTimeoutRC;
+        /** RC interrupt request callback of the owning device. */
     RCPTRTYPE(PFNUARTCOREIRQREQ)    pfnUartIrqReqRC;
 
@@ -153 +166 @@
     uint8_t                         uRegScr;
 
-    /** The transmit FIFO. */
+    /** Flag whether a character timeout interrupt is pending
+     * (no symbols were inserted or removed from the receive FIFO
+     * during an 4 times the character transmit/receive period and the FIFO
+     * is not empty). */
+    bool                            fIrqCtiPending;
+    /** Alignment. */
+    bool                            afAlignment[3];
+        /** The transmit FIFO. */
     UARTFIFO                        FifoXmit;
     /** The receive FIFO. */
     UARTFIFO                        FifoRecv;
 
+    /** Time it takes to transmit/receive a single symbol in timer ticks. */
+    uint64_t                        cSymbolXferTicks;
     /** Number of bytes available for reading from the layer below. */
     volatile uint32_t               cbAvailRdr;