VirtualBox

Changeset 73281 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jul 20, 2018 7:55:33 PM (7 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
123888
Message:

APIC: Made APICSetBaseMsr work in ring-0 and raw-mode context without requiring returns to ring-3. This uncomplicates NEM/win (not done yet). bugref:9044

Location:
trunk/src/VBox/VMM
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/APICAll.cpp

    r72486 r73281  
    21712171
    21722172/**
     2173 * Resets the APIC base MSR.
     2174 *
     2175 * @param   pVCpu           The cross context virtual CPU structure.
     2176 */
     2177static void apicResetBaseMsr(PVMCPU pVCpu)
     2178{
     2179    /*
     2180     * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
     2181     *
     2182     * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
     2183     * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
     2184     *
     2185     * [1] See AMD spec. 14.1.3 "Processor Initialization State"
     2186     * [2] See Intel spec. 10.12.5.1 "x2APIC States".
     2187     */
     2188    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
     2189
     2190    /* Construct. */
     2191    PAPICCPU pApicCpu     = VMCPU_TO_APICCPU(pVCpu);
     2192    PAPIC    pApic        = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
     2193    uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
     2194    if (pVCpu->idCpu == 0)
     2195        uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
     2196
     2197    /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
     2198    if (pApic->enmMaxMode != PDMAPICMODE_NONE)
     2199    {
     2200        uApicBaseMsr |= MSR_IA32_APICBASE_EN;
     2201
     2202        /*
     2203         * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
     2204         * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
     2205         * See Intel spec. 10.12.5.1 "x2APIC States".
     2206         */
     2207        if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
     2208            LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
     2209    }
     2210
     2211    /* Commit. */
     2212    ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
     2213}
     2214
     2215
     2216/**
     2217 * Initializes per-VCPU APIC to the state following an INIT reset
     2218 * ("Wait-for-SIPI" state).
     2219 *
     2220 * @param   pVCpu       The cross context virtual CPU structure.
     2221 */
     2222void apicInitIpi(PVMCPU pVCpu)
     2223{
     2224    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
     2225    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     2226
     2227    /*
     2228     * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
     2229     * and AMD spec 16.3.2 "APIC Registers".
     2230     *
     2231     * The reason we don't simply zero out the entire APIC page and only set the non-zero members
     2232     * is because there are some registers that are not touched by the INIT IPI (e.g. version)
     2233     * operation and this function is only a subset of the reset operation.
     2234     */
     2235    RT_ZERO(pXApicPage->irr);
     2236    RT_ZERO(pXApicPage->irr);
     2237    RT_ZERO(pXApicPage->isr);
     2238    RT_ZERO(pXApicPage->tmr);
     2239    RT_ZERO(pXApicPage->icr_hi);
     2240    RT_ZERO(pXApicPage->icr_lo);
     2241    RT_ZERO(pXApicPage->ldr);
     2242    RT_ZERO(pXApicPage->tpr);
     2243    RT_ZERO(pXApicPage->ppr);
     2244    RT_ZERO(pXApicPage->timer_icr);
     2245    RT_ZERO(pXApicPage->timer_ccr);
     2246    RT_ZERO(pXApicPage->timer_dcr);
     2247
     2248    pXApicPage->dfr.u.u4Model        = XAPICDESTFORMAT_FLAT;
     2249    pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
     2250
     2251    /** @todo CMCI. */
     2252
     2253    RT_ZERO(pXApicPage->lvt_timer);
     2254    pXApicPage->lvt_timer.u.u1Mask = 1;
     2255
     2256#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
     2257    RT_ZERO(pXApicPage->lvt_thermal);
     2258    pXApicPage->lvt_thermal.u.u1Mask = 1;
     2259#endif
     2260
     2261    RT_ZERO(pXApicPage->lvt_perf);
     2262    pXApicPage->lvt_perf.u.u1Mask = 1;
     2263
     2264    RT_ZERO(pXApicPage->lvt_lint0);
     2265    pXApicPage->lvt_lint0.u.u1Mask = 1;
     2266
     2267    RT_ZERO(pXApicPage->lvt_lint1);
     2268    pXApicPage->lvt_lint1.u.u1Mask = 1;
     2269
     2270    RT_ZERO(pXApicPage->lvt_error);
     2271    pXApicPage->lvt_error.u.u1Mask = 1;
     2272
     2273    RT_ZERO(pXApicPage->svr);
     2274    pXApicPage->svr.u.u8SpuriousVector = 0xff;
     2275
     2276    /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
     2277    PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
     2278    RT_ZERO(pX2ApicPage->self_ipi);
     2279
     2280    /* Clear the pending-interrupt bitmaps. */
     2281    PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
     2282    RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
     2283    RT_BZERO(pApicCpu->CTX_SUFF(pvApicPib), sizeof(APICPIB));
     2284
     2285    /* Clear the interrupt line states for LINT0 and LINT1 pins. */
     2286    pApicCpu->fActiveLint0 = false;
     2287    pApicCpu->fActiveLint1 = false;
     2288}
     2289
     2290
     2291/**
     2292 * Initializes per-VCPU APIC to the state following a power-up or hardware
     2293 * reset.
     2294 *
     2295 * @param   pVCpu               The cross context virtual CPU structure.
     2296 * @param   fResetApicBaseMsr   Whether to reset the APIC base MSR.
     2297 */
     2298void apicResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
     2299{
     2300    VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
     2301
     2302    LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
     2303
     2304#ifdef VBOX_STRICT
     2305    /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
     2306    uint32_t uEax, uEbx, uEcx, uEdx;
     2307    uEax = uEbx = uEcx = uEdx = UINT32_MAX;
     2308    CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
     2309    Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
     2310#endif
     2311
     2312    /*
     2313     * The state following a power-up or reset is a superset of the INIT state.
     2314     * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
     2315     */
     2316    apicInitIpi(pVCpu);
     2317
     2318    /*
     2319     * The APIC version register is read-only, so just initialize it here.
     2320     * It is not clear from the specs, where exactly it is initialized.
     2321     * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
     2322     */
     2323    PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
     2324#if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
     2325    pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
     2326    pXApicPage->version.u.u8Version     = XAPIC_HARDWARE_VERSION_P4;
     2327    AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
     2328#else
     2329# error "Implement Pentium and P6 family APIC architectures"
     2330#endif
     2331
     2332    /** @todo It isn't clear in the spec. where exactly the default base address
     2333     *        is (re)initialized, atm we do it here in Reset. */
     2334    if (fResetApicBaseMsr)
     2335        apicResetBaseMsr(pVCpu);
     2336
     2337    /*
     2338     * Initialize the APIC ID register to xAPIC format.
     2339     */
     2340    ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
     2341    pXApicPage->id.u8ApicId = pVCpu->idCpu;
     2342}
     2343
     2344
     2345/**
    21732346 * Sets the APIC base MSR.
    21742347 *
    2175  * @returns Strict VBox status code.
     2348 * @returns VBox status code - no informational ones, esp. not
     2349 *          VINF_CPUM_R3_MSR_WRITE.  Only the following two:
    21762350 * @retval  VINF_SUCCESS
    2177  * @retval  VINF_CPUM_R3_MSR_WRITE
    21782351 * @retval  VERR_CPUM_RAISE_GP_0
    21792352 *
    … …  
    21812354 * @param   u64BaseMsr  The value to set.
    21822355 */
    2183 VMM_INT_DECL(VBOXSTRICTRC) APICSetBaseMsr(PVMCPU pVCpu, uint64_t u64BaseMsr)
     2356VMM_INT_DECL(int) APICSetBaseMsr(PVMCPU pVCpu, uint64_t u64BaseMsr)
    21842357{
    21852358    Assert(pVCpu);
    21862359
    2187 #ifdef IN_RING3
    21882360    PAPICCPU pApicCpu   = VMCPU_TO_APICCPU(pVCpu);
    21892361    PAPIC    pApic      = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    … …  
    22132385    if (pApic->enmMaxMode == PDMAPICMODE_NONE)
    22142386    {
    2215         LogRel(("APIC%u: Disallowing APIC base MSR write as the VM is configured with APIC disabled!\n",
    2216                 pVCpu->idCpu));
     2387        LogRel(("APIC%u: Disallowing APIC base MSR write as the VM is configured with APIC disabled!\n", pVCpu->idCpu));
    22172388        return apicMsrAccessError(pVCpu, MSR_IA32_APICBASE, APICMSRACCESS_WRITE_DISALLOWED_CONFIG);
    22182389    }
    … …  
    22372408                 * need to update the CPUID leaf ourselves.
    22382409                 */
    2239                 apicR3ResetCpu(pVCpu, false /* fResetApicBaseMsr */);
     2410                apicResetCpu(pVCpu, false /* fResetApicBaseMsr */);
    22402411                uBaseMsr &= ~(MSR_IA32_APICBASE_EN | MSR_IA32_APICBASE_EXTD);
    22412412                CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, false /*fVisible*/);
    … …  
    23082479    ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uBaseMsr);
    23092480    return VINF_SUCCESS;
    2310 
    2311 #else  /* !IN_RING3 */
    2312     RT_NOREF_PV(pVCpu);
    2313     RT_NOREF_PV(u64BaseMsr);
    2314     return VINF_CPUM_R3_MSR_WRITE;
    2315 #endif /* IN_RING3 */
    23162481}
    23172482

  • trunk/src/VBox/VMM/VMMAll/NEMAllNativeTemplate-win.cpp.h

    r73186 r73281  
    10211021            Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
    10221022                  pVCpu->idCpu, uOldBase, aValues[iReg].Reg64, aValues[iReg].Reg64 ^ uOldBase));
    1023             VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, aValues[iReg].Reg64);
    1024             AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", VBOXSTRICTRC_VAL(rc2), aValues[iReg].Reg64));
     1023            int rc2 = APICSetBaseMsr(pVCpu, aValues[iReg].Reg64);
     1024            AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", rc2, aValues[iReg].Reg64));
    10251025        }
    10261026        iReg++;

  • trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp

    r73097 r73281  
    19901990            Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
    19911991                  pVCpu->idCpu, uOldBase, paValues[iReg].Reg64, paValues[iReg].Reg64 ^ uOldBase));
    1992             VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
     1992            int rc2 = APICSetBaseMsr(pVCpu, paValues[iReg].Reg64);
     1993            /** @todo fix me VINF_CPUM_R3_MSR_WRITE / APICSetBaseMsr */
    19931994            if (rc2 == VINF_CPUM_R3_MSR_WRITE)
    19941995            {
    … …  
    19971998            }
    19981999            else
    1999                 AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", VBOXSTRICTRC_VAL(rc2), paValues[iReg].Reg64));
     2000                AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", rc2, paValues[iReg].Reg64));
    20002001        }
    20012002        iReg++;

  • trunk/src/VBox/VMM/VMMR3/APIC.cpp

    r71280 r73281  
    175175
    176176/**
    177  * Initializes per-VCPU APIC to the state following an INIT reset
    178  * ("Wait-for-SIPI" state).
    179  *
    180  * @param   pVCpu       The cross context virtual CPU structure.
    181  */
    182 static void apicR3InitIpi(PVMCPU pVCpu)
    183 {
    184     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    185     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    186 
    187     /*
    188      * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset (Wait-for-SIPI State)"
    189      * and AMD spec 16.3.2 "APIC Registers".
    190      *
    191      * The reason we don't simply zero out the entire APIC page and only set the non-zero members
    192      * is because there are some registers that are not touched by the INIT IPI (e.g. version)
    193      * operation and this function is only a subset of the reset operation.
    194      */
    195     RT_ZERO(pXApicPage->irr);
    196     RT_ZERO(pXApicPage->irr);
    197     RT_ZERO(pXApicPage->isr);
    198     RT_ZERO(pXApicPage->tmr);
    199     RT_ZERO(pXApicPage->icr_hi);
    200     RT_ZERO(pXApicPage->icr_lo);
    201     RT_ZERO(pXApicPage->ldr);
    202     RT_ZERO(pXApicPage->tpr);
    203     RT_ZERO(pXApicPage->ppr);
    204     RT_ZERO(pXApicPage->timer_icr);
    205     RT_ZERO(pXApicPage->timer_ccr);
    206     RT_ZERO(pXApicPage->timer_dcr);
    207 
    208     pXApicPage->dfr.u.u4Model        = XAPICDESTFORMAT_FLAT;
    209     pXApicPage->dfr.u.u28ReservedMb1 = UINT32_C(0xfffffff);
    210 
    211     /** @todo CMCI. */
    212 
    213     RT_ZERO(pXApicPage->lvt_timer);
    214     pXApicPage->lvt_timer.u.u1Mask = 1;
    215 
    216 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
    217     RT_ZERO(pXApicPage->lvt_thermal);
    218     pXApicPage->lvt_thermal.u.u1Mask = 1;
    219 #endif
    220 
    221     RT_ZERO(pXApicPage->lvt_perf);
    222     pXApicPage->lvt_perf.u.u1Mask = 1;
    223 
    224     RT_ZERO(pXApicPage->lvt_lint0);
    225     pXApicPage->lvt_lint0.u.u1Mask = 1;
    226 
    227     RT_ZERO(pXApicPage->lvt_lint1);
    228     pXApicPage->lvt_lint1.u.u1Mask = 1;
    229 
    230     RT_ZERO(pXApicPage->lvt_error);
    231     pXApicPage->lvt_error.u.u1Mask = 1;
    232 
    233     RT_ZERO(pXApicPage->svr);
    234     pXApicPage->svr.u.u8SpuriousVector = 0xff;
    235 
    236     /* The self-IPI register is reset to 0. See Intel spec. 10.12.5.1 "x2APIC States" */
    237     PX2APICPAGE pX2ApicPage = VMCPU_TO_X2APICPAGE(pVCpu);
    238     RT_ZERO(pX2ApicPage->self_ipi);
    239 
    240     /* Clear the pending-interrupt bitmaps. */
    241     PAPICCPU pApicCpu = VMCPU_TO_APICCPU(pVCpu);
    242     RT_BZERO(&pApicCpu->ApicPibLevel, sizeof(APICPIB));
    243     RT_BZERO(pApicCpu->pvApicPibR3,   sizeof(APICPIB));
    244 
    245     /* Clear the interrupt line states for LINT0 and LINT1 pins. */
    246     pApicCpu->fActiveLint0 = false;
    247     pApicCpu->fActiveLint1 = false;
    248 }
    249 
    250 
    251 /**
    252177 * Sets the CPUID feature bits for the APIC mode.
    253178 *
    … …  
    281206
    282207/**
    283  * Resets the APIC base MSR.
    284  *
    285  * @param   pVCpu           The cross context virtual CPU structure.
    286  */
    287 static void apicR3ResetBaseMsr(PVMCPU pVCpu)
    288 {
    289     /*
    290      * Initialize the APIC base MSR. The APIC enable-bit is set upon power-up or reset[1].
    291      *
    292      * A Reset (in xAPIC and x2APIC mode) brings up the local APIC in xAPIC mode.
    293      * An INIT IPI does -not- cause a transition between xAPIC and x2APIC mode[2].
    294      *
    295      * [1] See AMD spec. 14.1.3 "Processor Initialization State"
    296      * [2] See Intel spec. 10.12.5.1 "x2APIC States".
    297      */
    298     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    299 
    300     /* Construct. */
    301     PAPICCPU pApicCpu     = VMCPU_TO_APICCPU(pVCpu);
    302     PAPIC    pApic        = VM_TO_APIC(pVCpu->CTX_SUFF(pVM));
    303     uint64_t uApicBaseMsr = MSR_IA32_APICBASE_ADDR;
    304     if (pVCpu->idCpu == 0)
    305         uApicBaseMsr |= MSR_IA32_APICBASE_BSP;
    306 
    307     /* If the VM was configured with no APIC, don't enable xAPIC mode, obviously. */
    308     if (pApic->enmMaxMode != PDMAPICMODE_NONE)
    309     {
    310         uApicBaseMsr |= MSR_IA32_APICBASE_EN;
    311 
    312         /*
    313          * While coming out of a reset the APIC is enabled and in xAPIC mode. If software had previously
    314          * disabled the APIC (which results in the CPUID bit being cleared as well) we re-enable it here.
    315          * See Intel spec. 10.12.5.1 "x2APIC States".
    316          */
    317         if (CPUMSetGuestCpuIdPerCpuApicFeature(pVCpu, true /*fVisible*/) == false)
    318             LogRel(("APIC%u: Resetting mode to xAPIC\n", pVCpu->idCpu));
    319     }
    320 
    321     /* Commit. */
    322     ASMAtomicWriteU64(&pApicCpu->uApicBaseMsr, uApicBaseMsr);
    323 }
    324 
    325 
    326 /**
    327  * Initializes per-VCPU APIC to the state following a power-up or hardware
    328  * reset.
    329  *
    330  * @param   pVCpu               The cross context virtual CPU structure.
    331  * @param   fResetApicBaseMsr   Whether to reset the APIC base MSR.
    332  */
    333 VMMR3_INT_DECL(void) apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr)
    334 {
    335     VMCPU_ASSERT_EMT_OR_NOT_RUNNING(pVCpu);
    336 
    337     LogFlow(("APIC%u: apicR3ResetCpu: fResetApicBaseMsr=%RTbool\n", pVCpu->idCpu, fResetApicBaseMsr));
    338 
    339 #ifdef VBOX_STRICT
    340     /* Verify that the initial APIC ID reported via CPUID matches our VMCPU ID assumption. */
    341     uint32_t uEax, uEbx, uEcx, uEdx;
    342     uEax = uEbx = uEcx = uEdx = UINT32_MAX;
    343     CPUMGetGuestCpuId(pVCpu, 1, 0, &uEax, &uEbx, &uEcx, &uEdx);
    344     Assert(((uEbx >> 24) & 0xff) == pVCpu->idCpu);
    345 #endif
    346 
    347     /*
    348      * The state following a power-up or reset is a superset of the INIT state.
    349      * See Intel spec. 10.4.7.3 "Local APIC State After an INIT Reset ('Wait-for-SIPI' State)"
    350      */
    351     apicR3InitIpi(pVCpu);
    352 
    353     /*
    354      * The APIC version register is read-only, so just initialize it here.
    355      * It is not clear from the specs, where exactly it is initialized.
    356      * The version determines the number of LVT entries and size of the APIC ID (8 bits for P4).
    357      */
    358     PXAPICPAGE pXApicPage = VMCPU_TO_XAPICPAGE(pVCpu);
    359 #if XAPIC_HARDWARE_VERSION == XAPIC_HARDWARE_VERSION_P4
    360     pXApicPage->version.u.u8MaxLvtEntry = XAPIC_MAX_LVT_ENTRIES_P4 - 1;
    361     pXApicPage->version.u.u8Version     = XAPIC_HARDWARE_VERSION_P4;
    362     AssertCompile(sizeof(pXApicPage->id.u8ApicId) >= XAPIC_APIC_ID_BIT_COUNT_P4 / 8);
    363 #else
    364 # error "Implement Pentium and P6 family APIC architectures"
    365 #endif
    366 
    367     /** @todo It isn't clear in the spec. where exactly the default base address
    368      *        is (re)initialized, atm we do it here in Reset. */
    369     if (fResetApicBaseMsr)
    370         apicR3ResetBaseMsr(pVCpu);
    371 
    372     /*
    373      * Initialize the APIC ID register to xAPIC format.
    374      */
    375     ASMMemZero32(&pXApicPage->id, sizeof(pXApicPage->id));
    376     pXApicPage->id.u8ApicId = pVCpu->idCpu;
    377 }
    378 
    379 
    380 /**
    381208 * Receives an INIT IPI.
    382209 *
    … …  
    387214    VMCPU_ASSERT_EMT(pVCpu);
    388215    LogFlow(("APIC%u: APICR3InitIpi\n", pVCpu->idCpu));
    389     apicR3InitIpi(pVCpu);
     216    apicInitIpi(pVCpu);
    390217}
    391218
    … …  
    13431170            TMTimerStop(pApicCpu->pTimerR3);
    13441171
    1345         apicR3ResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
     1172        apicResetCpu(pVCpuDest, true /* fResetApicBaseMsr */);
    13461173
    13471174        /* Clear the interrupt pending force flag. */
    … …  
    15451372                /* Initialize the virtual-APIC state. */
    15461373                RT_BZERO(pApicCpu->pvApicPageR3, pApicCpu->cbApicPage);
    1547                 apicR3ResetCpu(pVCpu, true /* fResetApicBaseMsr */);
     1374                apicResetCpu(pVCpu, true /* fResetApicBaseMsr */);
    15481375
    15491376#ifdef DEBUG_ramshankar

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-win.cpp

    r73182 r73281  
    16751675                {
    16761676                    LogFlow(("nemR3NativeRunGC: calling APICSetBaseMsr(,%RX64)...\n", pVCpu->nem.s.uPendingApicBase));
    1677                     VBOXSTRICTRC rc2 = APICSetBaseMsr(pVCpu, pVCpu->nem.s.uPendingApicBase);
    1678                     AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", VBOXSTRICTRC_VAL(rc2), pVCpu->nem.s.uPendingApicBase));
     1677                    int rc2 = APICSetBaseMsr(pVCpu, pVCpu->nem.s.uPendingApicBase);
     1678                    AssertLogRelMsg(rc2 == VINF_SUCCESS, ("rc2=%Rrc [%#RX64]\n", rc2, pVCpu->nem.s.uPendingApicBase));
    16791679                    pVCpu->nem.s.uPendingApicBase = UINT64_MAX;
    16801680                }

  • trunk/src/VBox/VMM/include/APICInternal.h

    r69111 r73281  
    14491449VMM_INT_DECL(void)            apicSetInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType);
    14501450VMM_INT_DECL(void)            apicClearInterruptFF(PVMCPU pVCpu, PDMAPICIRQ enmType);
    1451 
    1452 #ifdef IN_RING3
    1453 VMMR3_INT_DECL(void)          apicR3ResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr);
     1451void                          apicInitIpi(PVMCPU pVCpu);
     1452void                          apicResetCpu(PVMCPU pVCpu, bool fResetApicBaseMsr);
     1453
     1454RT_C_DECLS_END
     1455
     1456/** @} */
     1457
    14541458#endif
    14551459
    1456 RT_C_DECLS_END
    1457 
    1458 /** @} */
    1459 
    1460 #endif
    1461 
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