Changeset 73310 in vbox for trunk/include
- Timestamp:
- Jul 23, 2018 6:51:46 AM (6 years ago)
- File:
-
- 1 edited
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trunk/include/VBox/vmm/hm_vmx.h (modified) (26 diffs)
Legend:
- Unmodified
- Added
- Removed
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trunk/include/VBox/vmm/hm_vmx.h
r73293 r73310 1099 1099 */ 1100 1100 /** VMCS revision identifier used by the processor. */ 1101 #define MSR_IA32_VMX_BASIC_VMCS_ID(a) ((a) & 0x7fffffff)1101 #define MSR_IA32_VMX_BASIC_VMCS_ID(a) ((a) & 0x7fffffff) 1102 1102 /** Shift to get the VMCS size. */ 1103 #define MSR_IA32_VMX_BASIC_VMCS_SIZE_SHIFT 321103 #define MSR_IA32_VMX_BASIC_VMCS_SIZE_SHIFT 32 1104 1104 /** VMCS size in bytes. */ 1105 #define MSR_IA32_VMX_BASIC_VMCS_SIZE(a) (((a) >> 32) & 0x1fff)1105 #define MSR_IA32_VMX_BASIC_VMCS_SIZE(a) (((a) >> 32) & 0x1fff) 1106 1106 /** Shift to get the width of physical addresses and associated memory regions. */ 1107 #define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT 481107 #define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT 48 1108 1108 /** Width of physical addresses used for the VMCS and associated memory regions. */ 1109 #define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1)1109 #define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(a) (((a) >> 48) & 1) 1110 1110 /** Shift to get the dual-monitor treatment of SMI and SMM. */ 1111 #define MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT 491111 #define MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT 49 1112 1112 /** Dual-monitor treatment of SMI and SMM supported. */ 1113 #define MSR_IA32_VMX_BASIC_DUAL_MON(a) (((a) >> 49) & 1)1113 #define MSR_IA32_VMX_BASIC_DUAL_MON(a) (((a) >> 49) & 1) 1114 1114 /** Shift to get the memory type that must be used for the VMCS and associated 1115 1115 * memory regions. */ 1116 #define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT 501116 #define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT 50 1117 1117 /** Memory type that must be used for the VMCS and associated memory regions. */ 1118 #define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xf)1118 #define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(a) (((a) >> 50) & 0xf) 1119 1119 /** Shift to get the additional VM-exit information for INS/OUTS. */ 1120 #define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT 541120 #define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT 54 1121 1121 /** Additional VM-exit information for INS/OUTS. */ 1122 #define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(a) (((a) >> 54) & 1)1122 #define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(a) (((a) >> 54) & 1) 1123 1123 /** Shift to get the VMCS true controls. */ 1124 #define MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT 551124 #define MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT 55 1125 1125 /** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be 1126 1126 * cleared to 0 and that 'true' control MSRs are supported. */ 1127 #define MSR_IA32_VMX_BASIC_TRUE_CONTROLS(a) (((a) >> 55) & 1)1127 #define MSR_IA32_VMX_BASIC_TRUE_CONTROLS(a) (((a) >> 55) & 1) 1128 1128 /** @} */ 1129 1129 … … 1165 1165 * @{ 1166 1166 */ 1167 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY 1168 #define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 1169 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC 1170 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB 1171 #define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M 1172 #define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G 1173 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT 1174 #define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY 1175 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT 1176 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS 1177 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID 1178 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR 1179 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT 1180 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS 1167 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY RT_BIT_64(0) 1168 #define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4 RT_BIT_64(6) 1169 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC RT_BIT_64(8) 1170 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB RT_BIT_64(14) 1171 #define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M RT_BIT_64(16) 1172 #define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G RT_BIT_64(17) 1173 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT RT_BIT_64(20) 1174 #define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY RT_BIT_64(21) 1175 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT RT_BIT_64(25) 1176 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS RT_BIT_64(26) 1177 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID RT_BIT_64(32) 1178 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR RT_BIT_64(40) 1179 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT RT_BIT_64(41) 1180 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS RT_BIT_64(42) 1181 1181 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS RT_BIT_64(43) 1182 1182 /** @} */ … … 1203 1203 */ 1204 1204 #define VMX_VMCS16_VPID 0x000 1205 #define VMX_VMCS16_POSTED_INT R_NOTIFY_VECTOR0x0021205 #define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR 0x002 1206 1206 #define VMX_VMCS16_EPTP_INDEX 0x004 1207 1207 #define VMX_VMCS16_GUEST_ES_SEL 0x800 … … 1214 1214 #define VMX_VMCS16_GUEST_TR_SEL 0x80e 1215 1215 #define VMX_VMCS16_GUEST_INTR_STATUS 0x810 1216 /** @} */ 1216 #define VMX_VMCS16_GUEST_PML_INDEX 0x812 1217 /** @} */ 1218 1217 1219 1218 1220 /** @name VMCS field encoding: 16-bits host fields. … … 1226 1228 #define VMX_VMCS16_HOST_GS_SEL 0xc0a 1227 1229 #define VMX_VMCS16_HOST_TR_SEL 0xc0c 1228 /** @} */ 1229 1230 /** @name VMCS field encoding: 64-bit host fields. 1231 * @{ 1232 */ 1233 #define VMX_VMCS64_HOST_PAT_FULL 0x2c00 1234 #define VMX_VMCS64_HOST_PAT_HIGH 0x2c01 1235 #define VMX_VMCS64_HOST_EFER_FULL 0x2c02 1236 #define VMX_VMCS64_HOST_EFER_HIGH 0x2c03 1237 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04 /**< MSR IA32_PERF_GLOBAL_CTRL */ 1238 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05 /**< MSR IA32_PERF_GLOBAL_CTRL */ 1239 /** @} */ 1230 /** @} */ 1240 1231 1241 1232 … … 1287 1278 #define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL 0x202c 1288 1279 #define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH 0x202d 1280 #define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL 0x202e 1281 #define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH 0x202f 1289 1282 #define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL 0x2032 1290 1283 #define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH 0x2033 1291 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_FULL 0x2400 1292 #define VMX_VMCS64_EXIT_GUEST_PHYS_ADDR_HIGH 0x2401 1284 /** @} */ 1285 1286 1287 /** @name VMCS field encoding: 64-bit read-only data fields. 1288 * @{ 1289 */ 1290 #define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL 0x2400 1291 #define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH 0x2401 1293 1292 /** @} */ 1294 1293 … … 1315 1314 #define VMX_VMCS64_GUEST_PDPTE3_FULL 0x2810 1316 1315 #define VMX_VMCS64_GUEST_PDPTE3_HIGH 0x2811 1316 #define VMX_VMCS64_GUEST_BNDCFGS_FULL 0x2812 1317 #define VMX_VMCS64_GUEST_BNDCFGS_HIGH 0x2813 1318 /** @} */ 1319 1320 1321 /** @name VMCS field encoding: 64-bit host fields. 1322 * @{ 1323 */ 1324 #define VMX_VMCS64_HOST_PAT_FULL 0x2c00 1325 #define VMX_VMCS64_HOST_PAT_HIGH 0x2c01 1326 #define VMX_VMCS64_HOST_EFER_FULL 0x2c02 1327 #define VMX_VMCS64_HOST_EFER_HIGH 0x2c03 1328 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL 0x2c04 /**< MSR IA32_PERF_GLOBAL_CTRL */ 1329 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH 0x2c05 /**< MSR IA32_PERF_GLOBAL_CTRL */ 1317 1330 /** @} */ 1318 1331 … … 1339 1352 #define VMX_VMCS32_CTRL_PLE_GAP 0x4020 1340 1353 #define VMX_VMCS32_CTRL_PLE_WINDOW 0x4022 1354 /** @} */ 1355 1356 1357 /** @name VMCS field encoding: 32-bits read-only fields. 1358 * @{ 1359 */ 1360 #define VMX_VMCS32_RO_VM_INSTR_ERROR 0x4400 1361 #define VMX_VMCS32_RO_EXIT_REASON 0x4402 1362 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x4404 1363 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x4406 1364 #define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x4408 1365 #define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a 1366 #define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c 1367 #define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e 1368 /** @} */ 1369 1370 1371 /** @name VMCS field encoding: 32-bit guest-state fields. 1372 * @{ 1373 */ 1374 #define VMX_VMCS32_GUEST_ES_LIMIT 0x4800 1375 #define VMX_VMCS32_GUEST_CS_LIMIT 0x4802 1376 #define VMX_VMCS32_GUEST_SS_LIMIT 0x4804 1377 #define VMX_VMCS32_GUEST_DS_LIMIT 0x4806 1378 #define VMX_VMCS32_GUEST_FS_LIMIT 0x4808 1379 #define VMX_VMCS32_GUEST_GS_LIMIT 0x480a 1380 #define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c 1381 #define VMX_VMCS32_GUEST_TR_LIMIT 0x480e 1382 #define VMX_VMCS32_GUEST_GDTR_LIMIT 0x4810 1383 #define VMX_VMCS32_GUEST_IDTR_LIMIT 0x4812 1384 #define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x4814 1385 #define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x4816 1386 #define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x4818 1387 #define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a 1388 #define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c 1389 #define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e 1390 #define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x4820 1391 #define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x4822 1392 #define VMX_VMCS32_GUEST_INT_STATE 0x4824 1393 #define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x4826 1394 #define VMX_VMCS32_GUEST_SMBASE 0x4828 1395 #define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a /**< MSR IA32_SYSENTER_CS */ 1396 #define VMX_VMCS32_PREEMPT_TIMER_VALUE 0x482e 1397 /** @} */ 1398 1399 1400 /** @name VMCS field encoding: 32-bit host-state fields. 1401 * @{ 1402 */ 1403 #define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00 1404 /** @} */ 1405 1406 1407 /** @name Natural width control fields. 1408 * @{ 1409 */ 1410 #define VMX_VMCS_CTRL_CR0_MASK 0x6000 1411 #define VMX_VMCS_CTRL_CR4_MASK 0x6002 1412 #define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004 1413 #define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006 1414 #define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008 1415 #define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a 1416 #define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c 1417 #define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600e 1418 /** @} */ 1419 1420 /** @name Natural width read-only data fields. 1421 * @{ 1422 */ 1423 #define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400 1424 #define VMX_VMCS_RO_IO_RCX 0x6402 1425 #define VMX_VMCS_RO_IO_RSX 0x6404 1426 #define VMX_VMCS_RO_IO_RDI 0x6406 1427 #define VMX_VMCS_RO_IO_RIP 0x6408 1428 #define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a 1429 /** @} */ 1430 1431 1432 /** @name VMCS field encoding: Natural width guest-state fields. 1433 * @{ 1434 */ 1435 #define VMX_VMCS_GUEST_CR0 0x6800 1436 #define VMX_VMCS_GUEST_CR3 0x6802 1437 #define VMX_VMCS_GUEST_CR4 0x6804 1438 #define VMX_VMCS_GUEST_ES_BASE 0x6806 1439 #define VMX_VMCS_GUEST_CS_BASE 0x6808 1440 #define VMX_VMCS_GUEST_SS_BASE 0x680a 1441 #define VMX_VMCS_GUEST_DS_BASE 0x680c 1442 #define VMX_VMCS_GUEST_FS_BASE 0x680e 1443 #define VMX_VMCS_GUEST_GS_BASE 0x6810 1444 #define VMX_VMCS_GUEST_LDTR_BASE 0x6812 1445 #define VMX_VMCS_GUEST_TR_BASE 0x6814 1446 #define VMX_VMCS_GUEST_GDTR_BASE 0x6816 1447 #define VMX_VMCS_GUEST_IDTR_BASE 0x6818 1448 #define VMX_VMCS_GUEST_DR7 0x681a 1449 #define VMX_VMCS_GUEST_RSP 0x681c 1450 #define VMX_VMCS_GUEST_RIP 0x681e 1451 #define VMX_VMCS_GUEST_RFLAGS 0x6820 1452 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS 0x6822 1453 #define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */ 1454 #define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */ 1455 /** @} */ 1456 1457 1458 /** @name VMCS field encoding: Natural width host-state fields. 1459 * @{ 1460 */ 1461 #define VMX_VMCS_HOST_CR0 0x6c00 1462 #define VMX_VMCS_HOST_CR3 0x6c02 1463 #define VMX_VMCS_HOST_CR4 0x6c04 1464 #define VMX_VMCS_HOST_FS_BASE 0x6c06 1465 #define VMX_VMCS_HOST_GS_BASE 0x6c08 1466 #define VMX_VMCS_HOST_TR_BASE 0x6c0a 1467 #define VMX_VMCS_HOST_GDTR_BASE 0x6c0c 1468 #define VMX_VMCS_HOST_IDTR_BASE 0x6c0e 1469 #define VMX_VMCS_HOST_SYSENTER_ESP 0x6c10 1470 #define VMX_VMCS_HOST_SYSENTER_EIP 0x6c12 1471 #define VMX_VMCS_HOST_RSP 0x6c14 1472 #define VMX_VMCS_HOST_RIP 0x6c16 1341 1473 /** @} */ 1342 1474 … … 1515 1647 1516 1648 1517 /** @name VMCS field encoding: 32-bits read-only fields.1518 * @{1519 */1520 #define VMX_VMCS32_RO_VM_INSTR_ERROR 0x44001521 #define VMX_VMCS32_RO_EXIT_REASON 0x44021522 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO 0x44041523 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE 0x44061524 #define VMX_VMCS32_RO_IDT_VECTORING_INFO 0x44081525 #define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE 0x440a1526 #define VMX_VMCS32_RO_EXIT_INSTR_LENGTH 0x440c1527 #define VMX_VMCS32_RO_EXIT_INSTR_INFO 0x440e1528 /** @} */1529 1530 1531 1649 /** @name VMX_VMCS32_RO_EXIT_REASON 1532 1650 * @{ … … 1539 1657 * @{ 1540 1658 */ 1541 #define VMX_ENTRY_INT ERRUPTION_INFO_IS_VALID(a)(((a) >> 31) & 1)1542 #define VMX_ENTRY_INT ERRUPTION_INFO_TYPE_SHIFT81543 #define VMX_ENTRY_INT ERRUPTION_INFO_TYPE(a) ((a >> VMX_ENTRY_INTERRUPTION_INFO_TYPE_SHIFT) & 7)1659 #define VMX_ENTRY_INT_INFO_IS_VALID(a) (((a) >> 31) & 1) 1660 #define VMX_ENTRY_INT_INFO_TYPE_SHIFT 8 1661 #define VMX_ENTRY_INT_INFO_TYPE(a) (((a) >> 8) & 7) 1544 1662 /** @} */ 1545 1663 … … 1548 1666 * @{ 1549 1667 */ 1550 #define VMX_EXIT_INTERRUPTION_INFO_VECTOR(a) ((a) & 0xff) 1551 #define VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT 8 1552 #define VMX_EXIT_INTERRUPTION_INFO_TYPE(a) (((a) >> VMX_EXIT_INTERRUPTION_INFO_TYPE_SHIFT) & 7) 1553 #define VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID RT_BIT(11) 1554 #define VMX_EXIT_INTERRUPTION_INFO_IS_ERROR_CODE_VALID(a) RT_BOOL((a) & VMX_EXIT_INTERRUPTION_INFO_ERROR_CODE_VALID) 1555 #define VMX_EXIT_INTERRUPTION_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1) 1556 #define VMX_EXIT_INTERRUPTION_INFO_VALID RT_BIT(31) 1557 #define VMX_EXIT_INTERRUPTION_INFO_IS_VALID(a) (((a) >> 31) & 1) 1668 #define VMX_EXIT_INT_INFO_VECTOR(a) ((a) & 0xff) 1669 #define VMX_EXIT_INT_INFO_TYPE_SHIFT 8 1670 #define VMX_EXIT_INT_INFO_TYPE(a) (((a) >> 8) & 7) 1671 #define VMX_EXIT_INT_INFO_ERROR_CODE_VALID RT_BIT(11) 1672 #define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1) 1673 #define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET 12 1674 #define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a) (((a) >> 12) & 1) 1675 #define VMX_EXIT_INT_INFO_VALID RT_BIT(31) 1676 #define VMX_EXIT_INT_INFO_IS_VALID(a) (((a) >> 31) & 1) 1558 1677 /** Construct an irq event injection value from the exit interruption info value 1559 1678 * (same except that bit 12 is reserved). */ 1560 #define VMX_VMCS_ CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a)((a) & ~RT_BIT(12))1679 #define VMX_VMCS_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a) ((a) & ~RT_BIT(12)) 1561 1680 /** @} */ 1562 1681 … … 1565 1684 * @{ 1566 1685 */ 1567 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_EXT_INT01568 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_NMI21569 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_HW_XCPT31570 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_SW_INT41571 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_PRIV_SW_XCPT51572 #define VMX_EXIT_INT ERRUPTION_INFO_TYPE_SW_XCPT61686 #define VMX_EXIT_INT_INFO_TYPE_EXT_INT 0 1687 #define VMX_EXIT_INT_INFO_TYPE_NMI 2 1688 #define VMX_EXIT_INT_INFO_TYPE_HW_XCPT 3 1689 #define VMX_EXIT_INT_INFO_TYPE_SW_INT 4 1690 #define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT 5 1691 #define VMX_EXIT_INT_INFO_TYPE_SW_XCPT 6 1573 1692 /** @} */ 1574 1693 … … 1579 1698 #define VMX_IDT_VECTORING_INFO_VECTOR(a) ((a) & 0xff) 1580 1699 #define VMX_IDT_VECTORING_INFO_TYPE_SHIFT 8 1581 #define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> VMX_IDT_VECTORING_INFO_TYPE_SHIFT) & 7)1700 #define VMX_IDT_VECTORING_INFO_TYPE(a) (((a) >> 8) & 7) 1582 1701 #define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID RT_BIT(11) 1583 1702 #define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a) (((a) >> 11) & 1) … … 1596 1715 #define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT 5 1597 1716 #define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT 6 1598 /** @} */1599 1600 1601 /** @name VMCS field encoding: 32-bit guest-state fields.1602 * @{1603 */1604 #define VMX_VMCS32_GUEST_ES_LIMIT 0x48001605 #define VMX_VMCS32_GUEST_CS_LIMIT 0x48021606 #define VMX_VMCS32_GUEST_SS_LIMIT 0x48041607 #define VMX_VMCS32_GUEST_DS_LIMIT 0x48061608 #define VMX_VMCS32_GUEST_FS_LIMIT 0x48081609 #define VMX_VMCS32_GUEST_GS_LIMIT 0x480a1610 #define VMX_VMCS32_GUEST_LDTR_LIMIT 0x480c1611 #define VMX_VMCS32_GUEST_TR_LIMIT 0x480e1612 #define VMX_VMCS32_GUEST_GDTR_LIMIT 0x48101613 #define VMX_VMCS32_GUEST_IDTR_LIMIT 0x48121614 #define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS 0x48141615 #define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS 0x48161616 #define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS 0x48181617 #define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS 0x481a1618 #define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS 0x481c1619 #define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS 0x481e1620 #define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS 0x48201621 #define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS 0x48221622 #define VMX_VMCS32_GUEST_INTERRUPTIBILITY_STATE 0x48241623 #define VMX_VMCS32_GUEST_ACTIVITY_STATE 0x48261624 #define VMX_VMCS32_GUEST_SYSENTER_CS 0x482a /**< MSR IA32_SYSENTER_CS */1625 #define VMX_VMCS32_GUEST_PREEMPT_TIMER_VALUE 0x482e1626 1717 /** @} */ 1627 1718 … … 1641 1732 1642 1733 1643 /** @name VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE 1644 * @{ 1645 */ 1646 #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_STI RT_BIT(0) 1647 #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_MOVSS RT_BIT(1) 1648 #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_SMI RT_BIT(2) 1649 #define VMX_VMCS_GUEST_INTERRUPTIBILITY_STATE_BLOCK_NMI RT_BIT(3) 1650 /** @} */ 1651 1652 1653 /** @name VMCS field encoding: 32-bit host-state fields. 1654 * @{ 1655 */ 1656 #define VMX_VMCS32_HOST_SYSENTER_CS 0x4C00 1657 /** @} */ 1658 1659 1660 /** @name Natural width control fields 1661 * @{ 1662 */ 1663 #define VMX_VMCS_CTRL_CR0_MASK 0x6000 1664 #define VMX_VMCS_CTRL_CR4_MASK 0x6002 1665 #define VMX_VMCS_CTRL_CR0_READ_SHADOW 0x6004 1666 #define VMX_VMCS_CTRL_CR4_READ_SHADOW 0x6006 1667 #define VMX_VMCS_CTRL_CR3_TARGET_VAL0 0x6008 1668 #define VMX_VMCS_CTRL_CR3_TARGET_VAL1 0x600a 1669 #define VMX_VMCS_CTRL_CR3_TARGET_VAL2 0x600c 1670 #define VMX_VMCS_CTRL_CR3_TARGET_VAL31 0x600e 1671 /** @} */ 1672 1673 1674 /** @name Natural width read-only data fields 1675 * @{ 1676 */ 1677 #define VMX_VMCS_RO_EXIT_QUALIFICATION 0x6400 1678 #define VMX_VMCS_RO_IO_RCX 0x6402 1679 #define VMX_VMCS_RO_IO_RSX 0x6404 1680 #define VMX_VMCS_RO_IO_RDI 0x6406 1681 #define VMX_VMCS_RO_IO_RIP 0x6408 1682 #define VMX_VMCS_RO_EXIT_GUEST_LINEAR_ADDR 0x640a 1734 /** @name VMX_VMCS32_GUEST_INT_STATE 1735 * @{ 1736 */ 1737 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI RT_BIT(0) 1738 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS RT_BIT(1) 1739 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI RT_BIT(2) 1740 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI RT_BIT(3) 1683 1741 /** @} */ 1684 1742 … … 1704 1762 * @{ 1705 1763 */ 1706 #define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 01707 #define VMX_EXIT_QUAL_DRX_DIRECTION_READ 11764 #define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE 0 1765 #define VMX_EXIT_QUAL_DRX_DIRECTION_READ 1 1708 1766 /** @} */ 1709 1767 … … 1713 1771 */ 1714 1772 /** 0-3: Control register number (0 for CLTS & LMSW) */ 1715 #define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf)1773 #define VMX_EXIT_QUAL_CRX_REGISTER(a) ((a) & 0xf) 1716 1774 /** 4-5: Access type. */ 1717 #define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3)1775 #define VMX_EXIT_QUAL_CRX_ACCESS(a) (((a) >> 4) & 3) 1718 1776 /** 6: LMSW operand type */ 1719 #define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1)1777 #define VMX_EXIT_QUAL_CRX_LMSW_OP(a) (((a) >> 6) & 1) 1720 1778 /** 7: Reserved; cleared to 0. */ 1721 #define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1)1779 #define VMX_EXIT_QUAL_CRX_RES1(a) (((a) >> 7) & 1) 1722 1780 /** 8-11: General purpose register number (0 for CLTS & LMSW). */ 1723 #define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf)1781 #define VMX_EXIT_QUAL_CRX_GENREG(a) (((a) >> 8) & 0xf) 1724 1782 /** 12-15: Reserved; cleared to 0. */ 1725 #define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf)1783 #define VMX_EXIT_QUAL_CRX_RES2(a) (((a) >> 12) & 0xf) 1726 1784 /** 16-31: LMSW source data (else 0). */ 1727 #define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff)1785 #define VMX_EXIT_QUAL_CRX_LMSW_DATA(a) (((a) >> 16) & 0xffff) 1728 1786 /* Rest: reserved. */ 1729 1787 /** @} */ … … 1733 1791 * @{ 1734 1792 */ 1735 #define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 01736 #define VMX_EXIT_QUAL_CRX_ACCESS_READ 11737 #define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 21738 #define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 31793 #define VMX_EXIT_QUAL_CRX_ACCESS_WRITE 0 1794 #define VMX_EXIT_QUAL_CRX_ACCESS_READ 1 1795 #define VMX_EXIT_QUAL_CRX_ACCESS_CLTS 2 1796 #define VMX_EXIT_QUAL_CRX_ACCESS_LMSW 3 1739 1797 /** @} */ 1740 1798 … … 1743 1801 * @{ 1744 1802 */ 1745 #define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff)1746 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3)1803 #define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a) ((a) & 0xffff) 1804 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a) (((a) >> 30) & 0x3) 1747 1805 /** Task switch caused by a call instruction. */ 1748 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 01806 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL 0 1749 1807 /** Task switch caused by an iret instruction. */ 1750 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 11808 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET 1 1751 1809 /** Task switch caused by a jmp instruction. */ 1752 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 21810 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP 2 1753 1811 /** Task switch caused by an interrupt gate. */ 1754 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 31812 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT 3 1755 1813 /** @} */ 1756 1814 … … 1760 1818 */ 1761 1819 /** Set if the violation was caused by a data read. */ 1762 #define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0)1820 #define VMX_EXIT_QUAL_EPT_DATA_READ RT_BIT(0) 1763 1821 /** Set if the violation was caused by a data write. */ 1764 #define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1)1822 #define VMX_EXIT_QUAL_EPT_DATA_WRITE RT_BIT(1) 1765 1823 /** Set if the violation was caused by an instruction fetch. */ 1766 #define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2)1824 #define VMX_EXIT_QUAL_EPT_INSTR_FETCH RT_BIT(2) 1767 1825 /** AND of the present bit of all EPT structures. */ 1768 #define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3)1826 #define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT RT_BIT(3) 1769 1827 /** AND of the write bit of all EPT structures. */ 1770 #define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4)1828 #define VMX_EXIT_QUAL_EPT_ENTRY_WRITE RT_BIT(4) 1771 1829 /** AND of the execute bit of all EPT structures. */ 1772 #define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5)1830 #define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE RT_BIT(5) 1773 1831 /** Set if the guest linear address field contains the faulting address. */ 1774 #define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7)1832 #define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID RT_BIT(7) 1775 1833 /** If bit 7 is one: (reserved otherwise) 1776 1834 * 1 - violation due to physical address access. 1777 1835 * 0 - violation caused by page walk or access/dirty bit updates 1778 1836 */ 1779 #define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8)1837 #define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS RT_BIT(8) 1780 1838 /** @} */ 1781 1839 … … 1785 1843 */ 1786 1844 /** 0-2: IO operation width. */ 1787 #define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7)1845 #define VMX_EXIT_QUAL_IO_WIDTH(a) ((a) & 7) 1788 1846 /** 3: IO operation direction. */ 1789 #define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1)1847 #define VMX_EXIT_QUAL_IO_DIRECTION(a) (((a) >> 3) & 1) 1790 1848 /** 4: String IO operation (INS / OUTS). */ 1791 #define VMX_EXIT_QUAL_IO_IS_STRING(a) RT_BOOL((a) & RT_BIT_64(4))1849 #define VMX_EXIT_QUAL_IO_IS_STRING(a) (((a) >> 4) & 1) 1792 1850 /** 5: Repeated IO operation. */ 1793 #define VMX_EXIT_QUAL_IO_IS_REP(a) RT_BOOL((a) & RT_BIT_64(5))1851 #define VMX_EXIT_QUAL_IO_IS_REP(a) (((a) >> 5) & 1) 1794 1852 /** 6: Operand encoding. */ 1795 #define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1)1853 #define VMX_EXIT_QUAL_IO_ENCODING(a) (((a) >> 6) & 1) 1796 1854 /** 16-31: IO Port (0-0xffff). */ 1797 #define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff)1855 #define VMX_EXIT_QUAL_IO_PORT(a) (((a) >> 16) & 0xffff) 1798 1856 /* Rest reserved. */ 1799 1857 /** @} */ … … 1803 1861 * @{ 1804 1862 */ 1805 #define VMX_EXIT_QUAL_IO_DIRECTION_OUT 01806 #define VMX_EXIT_QUAL_IO_DIRECTION_IN 11863 #define VMX_EXIT_QUAL_IO_DIRECTION_OUT 0 1864 #define VMX_EXIT_QUAL_IO_DIRECTION_IN 1 1807 1865 /** @} */ 1808 1866 … … 1811 1869 * @{ 1812 1870 */ 1813 #define VMX_EXIT_QUAL_IO_ENCODING_DX 01814 #define VMX_EXIT_QUAL_IO_ENCODING_IMM 11871 #define VMX_EXIT_QUAL_IO_ENCODING_DX 0 1872 #define VMX_EXIT_QUAL_IO_ENCODING_IMM 1 1815 1873 /** @} */ 1816 1874 … … 1821 1879 /** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of 1822 1880 * access within the APIC page. */ 1823 #define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff)1881 #define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a) ((a) & 0xfff) 1824 1882 /** 12-15: Access type. */ 1825 #define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12)1883 #define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a) (((a) & 0xf000) >> 12) 1826 1884 /* Rest reserved. */ 1827 1885 /** @} */ … … 1956 2014 1957 2015 1958 /** @name VMCS field encoding: Natural width guest-state fields.1959 * @{1960 */1961 #define VMX_VMCS_GUEST_CR0 0x68001962 #define VMX_VMCS_GUEST_CR3 0x68021963 #define VMX_VMCS_GUEST_CR4 0x68041964 #define VMX_VMCS_GUEST_ES_BASE 0x68061965 #define VMX_VMCS_GUEST_CS_BASE 0x68081966 #define VMX_VMCS_GUEST_SS_BASE 0x680a1967 #define VMX_VMCS_GUEST_DS_BASE 0x680c1968 #define VMX_VMCS_GUEST_FS_BASE 0x680e1969 #define VMX_VMCS_GUEST_GS_BASE 0x68101970 #define VMX_VMCS_GUEST_LDTR_BASE 0x68121971 #define VMX_VMCS_GUEST_TR_BASE 0x68141972 #define VMX_VMCS_GUEST_GDTR_BASE 0x68161973 #define VMX_VMCS_GUEST_IDTR_BASE 0x68181974 #define VMX_VMCS_GUEST_DR7 0x681a1975 #define VMX_VMCS_GUEST_RSP 0x681c1976 #define VMX_VMCS_GUEST_RIP 0x681e1977 #define VMX_VMCS_GUEST_RFLAGS 0x68201978 #define VMX_VMCS_GUEST_PENDING_DEBUG_EXCEPTIONS 0x68221979 #define VMX_VMCS_GUEST_SYSENTER_ESP 0x6824 /**< MSR IA32_SYSENTER_ESP */1980 #define VMX_VMCS_GUEST_SYSENTER_EIP 0x6826 /**< MSR IA32_SYSENTER_EIP */1981 /** @} */1982 1983 1984 2016 /** @name VMX_VMCS_GUEST_DEBUG_EXCEPTIONS 1985 2017 * Bits 4-11, 13 and 15-63 are reserved. … … 1998 2030 /** A debug exception would have been triggered by single-step execution mode. */ 1999 2031 #define VMX_VMCS_GUEST_DEBUG_EXCEPTIONS_BS RT_BIT(14) 2000 /** @} */2001 2002 2003 /** @name VMCS field encoding: Natural width host-state fields.2004 * @{2005 */2006 #define VMX_VMCS_HOST_CR0 0x6c002007 #define VMX_VMCS_HOST_CR3 0x6c022008 #define VMX_VMCS_HOST_CR4 0x6c042009 #define VMX_VMCS_HOST_FS_BASE 0x6c062010 #define VMX_VMCS_HOST_GS_BASE 0x6c082011 #define VMX_VMCS_HOST_TR_BASE 0x6c0a2012 #define VMX_VMCS_HOST_GDTR_BASE 0x6c0c2013 #define VMX_VMCS_HOST_IDTR_BASE 0x6c0e2014 #define VMX_VMCS_HOST_SYSENTER_ESP 0x6c102015 #define VMX_VMCS_HOST_SYSENTER_EIP 0x6c122016 #define VMX_VMCS_HOST_RSP 0x6c142017 #define VMX_VMCS_HOST_RIP 0x6c162018 2032 /** @} */ 2019 2033
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