VirtualBox

Changeset 73324 in vbox for trunk/src


Ignore:
Timestamp:
Jul 23, 2018 2:06:55 PM (7 years ago)
Author:
vboxsync
Message:

PGM: Introduced a special shadow paging mode for NEM that translates to minimal unnecessary work. bugref:9044

Location:
trunk/src/VBox/VMM
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r73280 r73324  
    519519# undef PGM_SHW_NAME
    520520
     521
     522/*
     523 * Shadow - NEM / None.
     524 */
     525# define PGM_SHW_TYPE               PGM_TYPE_NONE
     526# define PGM_SHW_NAME(name)         PGM_SHW_NAME_NONE(name)
     527# include "PGMAllShw.h"
     528
     529/* Guest - real mode */
     530# define PGM_GST_TYPE               PGM_TYPE_REAL
     531# define PGM_GST_NAME(name)         PGM_GST_NAME_REAL(name)
     532# define PGM_BTH_NAME(name)         PGM_BTH_NAME_NONE_REAL(name)
     533# include "PGMGstDefs.h"
     534# include "PGMAllBth.h"
     535# undef PGM_BTH_NAME
     536# undef PGM_GST_TYPE
     537# undef PGM_GST_NAME
     538
     539/* Guest - protected mode */
     540# define PGM_GST_TYPE               PGM_TYPE_PROT
     541# define PGM_GST_NAME(name)         PGM_GST_NAME_PROT(name)
     542# define PGM_BTH_NAME(name)         PGM_BTH_NAME_NONE_PROT(name)
     543# include "PGMGstDefs.h"
     544# include "PGMAllBth.h"
     545# undef PGM_BTH_NAME
     546# undef PGM_GST_TYPE
     547# undef PGM_GST_NAME
     548
     549/* Guest - 32-bit mode */
     550# define PGM_GST_TYPE               PGM_TYPE_32BIT
     551# define PGM_GST_NAME(name)         PGM_GST_NAME_32BIT(name)
     552# define PGM_BTH_NAME(name)         PGM_BTH_NAME_NONE_32BIT(name)
     553# include "PGMGstDefs.h"
     554# include "PGMAllBth.h"
     555# undef PGM_BTH_NAME
     556# undef PGM_GST_TYPE
     557# undef PGM_GST_NAME
     558
     559/* Guest - PAE mode */
     560# define PGM_GST_TYPE               PGM_TYPE_PAE
     561# define PGM_GST_NAME(name)         PGM_GST_NAME_PAE(name)
     562# define PGM_BTH_NAME(name)         PGM_BTH_NAME_NONE_PAE(name)
     563# include "PGMGstDefs.h"
     564# include "PGMAllBth.h"
     565# undef PGM_BTH_NAME
     566# undef PGM_GST_TYPE
     567# undef PGM_GST_NAME
     568
     569# ifdef VBOX_WITH_64_BITS_GUESTS
     570/* Guest - AMD64 mode */
     571#  define PGM_GST_TYPE              PGM_TYPE_AMD64
     572#  define PGM_GST_NAME(name)        PGM_GST_NAME_AMD64(name)
     573#  define PGM_BTH_NAME(name)        PGM_BTH_NAME_NONE_AMD64(name)
     574#  include "PGMGstDefs.h"
     575#  include "PGMAllBth.h"
     576#  undef PGM_BTH_NAME
     577#  undef PGM_GST_TYPE
     578#  undef PGM_GST_NAME
     579# endif /* VBOX_WITH_64_BITS_GUESTS */
     580
     581# undef PGM_SHW_TYPE
     582# undef PGM_SHW_NAME
     583
    521584#endif /* !IN_RC */
    522585
    … …  
    667730# endif
    668731    },
     732    {
     733        PGM_TYPE_NONE,
     734        PGM_SHW_NAME_NONE(GetPage),
     735        PGM_SHW_NAME_NONE(ModifyPage),
     736        PGM_SHW_NAME_NONE(Enter),
     737        PGM_SHW_NAME_NONE(Exit),
     738# ifdef IN_RING3
     739        PGM_SHW_NAME_NONE(Relocate),
     740# endif
     741    },
    669742#endif /* IN_RC */
    670743};
    … …  
    711784    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
    712785    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_EPT          - illegal */
     786    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_32BIT, PGM_TYPE_NONE         - illegal */
    713787
    714788    /* PAE shadow paging mode: */
    … …  
    723797    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
    724798    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_EPT          - illegal */
     799    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_PAE, PGM_TYPE_NONE         - illegal */
    725800
    726801#ifndef IN_RC
    … …  
    740815    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
    741816    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_EPT          - illegal */
     817    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_AMD64, PGM_TYPE_NONE         - illegal */
    742818
    743819    /* 32-bit nested paging mode: */
    … …  
    756832    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NESTED_AMD64 - illegal */
    757833    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_EPT          - illegal */
     834    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_32BIT, PGM_TYPE_NONE         - illegal */
    758835
    759836    /* PAE nested paging mode: */
    … …  
    772849    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NESTED_AMD64 - illegal */
    773850    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_EPT          - illegal */
     851    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_PAE, PGM_TYPE_NONE         - illegal */
    774852
    775853    /* AMD64 nested paging mode: */
    … …  
    788866    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NESTED_AMD64 - illegal */
    789867    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_EPT          - illegal */
     868    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NESTED_AMD64, PGM_TYPE_NONE         - illegal */
    790869
    791870    /* EPT nested paging mode: */
    … …  
    804883    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NESTED_AMD64 - illegal */
    805884    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_EPT          - illegal */
     885    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_EPT, PGM_TYPE_NONE         - illegal */
     886
     887    /* NONE / NEM: */
     888    PGMMODEDATABTH_NULL_ENTRY(), /* 0 */
     889    PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_REAL,  PGM_BTH_NAME_EPT_REAL),
     890    PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PROT,  PGM_BTH_NAME_EPT_PROT),
     891    PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_32BIT, PGM_BTH_NAME_EPT_32BIT),
     892    PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_PAE,   PGM_BTH_NAME_EPT_PAE),
     893# ifdef VBOX_WITH_64_BITS_GUESTS
     894    PGMMODEDATABTH_ENTRY(PGM_TYPE_NONE, PGM_TYPE_AMD64, PGM_BTH_NAME_EPT_AMD64),
     895# else
     896    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_AMD64        - illegal */
     897# endif
     898    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_32BIT - illegal */
     899    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_PAE   - illegal */
     900    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NESTED_AMD64 - illegal */
     901    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_EPT          - illegal */
     902    PGMMODEDATABTH_NULL_ENTRY(), /* PGM_TYPE_NONE, PGM_TYPE_NONE         - illegal */
    806903
    807904#endif /* IN_RC */
    … …  
    29213018        case PGMMODE_NESTED_AMD64:  return PGM_TYPE_NESTED_AMD64;
    29223019        case PGMMODE_EPT:           return PGM_TYPE_EPT;
     3020        case PGMMODE_NONE:          return PGM_TYPE_NONE;
    29233021        default:
    29243022            AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
    … …  
    30943192    {
    30953193        pVM->pgm.s.fNestedPaging = true;
    3096         enmShadowMode = PGMMODE_EPT; /* whatever harmless... */
     3194        enmShadowMode = PGMMODE_NONE;
    30973195    }
    30983196    else
    … …  
    34403538        case PGMMODE_NESTED_AMD64:  return "Nested-AMD64";
    34413539        case PGMMODE_EPT:           return "EPT";
     3540        case PGMMODE_NONE:          return "None";
    34423541        default:                    return "unknown mode value";
    34433542    }

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r73277 r73324  
    6868 * remove redundant checks inside functions.
    6969 */
    70 #if      PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     70#if    PGM_GST_TYPE == PGM_TYPE_PAE && PGM_SHW_TYPE != PGM_TYPE_PAE \
     71    && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
    7172# error "Invalid combination; PAE guest implies PAE shadow"
    7273#endif
    7374
    74 #if     (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
    75     && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE))
     75#if    (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
     76    && !(   PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64 \
     77         || PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NONE)
    7678# error "Invalid combination; real or protected mode without paging implies 32 bits or PAE shadow paging."
    7779#endif
    7880
    7981#if     (PGM_GST_TYPE == PGM_TYPE_32BIT || PGM_GST_TYPE == PGM_TYPE_PAE) \
    80     && !(PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE))
     82    && !(   PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_PAE \
     83         || PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NONE)
    8184# error "Invalid combination; 32 bits guest paging or PAE implies 32 bits or PAE shadow paging."
    8285#endif
    8386
    84 #if    (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)) \
     87#if    (PGM_GST_TYPE == PGM_TYPE_AMD64 && PGM_SHW_TYPE != PGM_TYPE_AMD64 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE) \
    8588    || (PGM_SHW_TYPE == PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_AMD64 && PGM_GST_TYPE != PGM_TYPE_PROT)
    8689# error "Invalid combination; AMD64 guest implies AMD64 shadow and vice versa"
    … …  
    225228
    226229
    227 #if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE)
     230#if !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
    228231/**
    229232 * Deal with a guest page fault.
    … …  
    525528    return rcStrict;
    526529} /* if any kind of handler */
    527 # endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) */
     530# endif /* !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE*/
    528531
    529532
    … …  
    548551       || PGM_GST_TYPE == PGM_TYPE_PAE   || PGM_GST_TYPE == PGM_TYPE_AMD64) \
    549552    && !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
    550     && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT)
     553    && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
     554    && PGM_SHW_TYPE != PGM_TYPE_NONE
    551555    int rc;
    552556
    … …  
    12701274    return rc;
    12711275
    1272 # else  /* Nested paging, EPT except PGM_GST_TYPE = PROT   */
     1276# else  /* Nested paging, EPT except PGM_GST_TYPE = PROT, NONE.   */
    12731277    NOREF(uErr); NOREF(pRegFrame); NOREF(pvFault);
    12741278    AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_SHW_TYPE, PGM_GST_TYPE));
    … …  
    13021306{
    13031307#if    PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)   \
    1304     && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     1308    && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
     1309    && PGM_SHW_TYPE != PGM_TYPE_NONE
    13051310    int rc;
    13061311    PVM pVM = pVCpu->CTX_SUFF(pVM);
    … …  
    15851590    return rc;
    15861591
    1587 #else /* guest real and protected mode */
     1592#else /* guest real and protected mode, nested + ept, none. */
    15881593    /* There's no such thing as InvalidatePage when paging is disabled, so just ignore. */
    15891594    NOREF(pVCpu); NOREF(GCPtrPage);
    … …  
    15921597}
    15931598
     1599#if PGM_SHW_TYPE != PGM_TYPE_NONE
    15941600
    15951601/**
    … …  
    17271733    {
    17281734        LogFlow(("SyncHandlerPte: monitored page (%R[pgmpage]) -> mark read-only\n", pPage));
    1729 #if PGM_SHW_TYPE == PGM_TYPE_EPT
     1735# if PGM_SHW_TYPE == PGM_TYPE_EPT
    17301736        pPteDst->u             = PGM_PAGE_GET_HCPHYS(pPage);
    17311737        pPteDst->n.u1Present   = 1;
    … …  
    17341740        pPteDst->n.u3EMT       = VMX_EPT_MEMTYPE_WB;
    17351741        /* PteDst.n.u1Write = 0 && PteDst.n.u1Size = 0 */
    1736 #else
     1742# else
    17371743        if (fPteSrc & X86_PTE_A)
    17381744        {
    … …  
    17421748        else
    17431749            SHW_PTE_SET(*pPteDst, 0);
    1744 #endif
    1745     }
    1746 #ifdef PGM_WITH_MMIO_OPTIMIZATIONS
    1747 # if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
     1750# endif
     1751    }
     1752# ifdef PGM_WITH_MMIO_OPTIMIZATIONS
     1753#  if PGM_SHW_TYPE == PGM_TYPE_EPT || PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_AMD64
    17481754    else if (   PGM_PAGE_HAS_ACTIVE_ALL_HANDLERS(pPage)
    17491755             && (   BTH_IS_NP_ACTIVE(pVM)
    17501756                 || (fPteSrc & (X86_PTE_RW | X86_PTE_US)) == X86_PTE_RW) /** @todo Remove X86_PTE_US here and pGstWalk->Core.fEffectiveUS before the sync page test. */
    1751 #  if PGM_SHW_TYPE == PGM_TYPE_AMD64
     1757#   if PGM_SHW_TYPE == PGM_TYPE_AMD64
    17521758             && pVM->pgm.s.fLessThan52PhysicalAddressBits
    1753 #  endif
     1759#   endif
    17541760            )
    17551761    {
    17561762        LogFlow(("SyncHandlerPte: MMIO page -> invalid \n"));
    1757 #  if PGM_SHW_TYPE == PGM_TYPE_EPT
     1763#   if PGM_SHW_TYPE == PGM_TYPE_EPT
    17581764        /* 25.2.3.1: Reserved physical address bit -> EPT Misconfiguration (exit 49) */
    17591765        pPteDst->u = pVM->pgm.s.HCPhysInvMmioPg;
    … …  
    17641770        /* 25.2.3.1: leaf && 2:0 != 0 && u3Emt in {2, 3, 7} -> EPT Misconfiguration */
    17651771        pPteDst->n.u3EMT     = 7;
    1766 #  else
     1772#   else
    17671773        /* Set high page frame bits that MBZ (bankers on PAE, CPU dependent on AMD64).  */
    17681774        SHW_PTE_SET(*pPteDst, pVM->pgm.s.HCPhysInvMmioPg | X86_PTE_PAE_MBZ_MASK_NO_NX | X86_PTE_P);
    1769 #  endif
    1770     }
    1771 # endif
    1772 #endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
     1775#   endif
     1776    }
     1777#  endif
     1778# endif /* PGM_WITH_MMIO_OPTIMIZATIONS */
    17731779    else
    17741780    {
    … …  
    17971803 * @remark  Not used for 2/4MB pages!
    17981804 */
    1799 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) || defined(DOXYGEN_RUNNING)
     1805# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) || defined(DOXYGEN_RUNNING)
    18001806static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, GSTPDE PdeSrc, GSTPTE PteSrc,
    18011807                                         PPGMPOOLPAGE pShwPage, unsigned iPTDst)
    1802 #else
     1808# else
    18031809static void PGM_BTH_NAME(SyncPageWorker)(PVMCPU pVCpu, PSHWPTE pPteDst, RTGCPHYS GCPhysPage,
    18041810                                         PPGMPOOLPAGE pShwPage, unsigned iPTDst)
    1805 #endif
     1811# endif
    18061812{
    18071813    PVM      pVM = pVCpu->CTX_SUFF(pVM);
    18081814    RTGCPHYS GCPhysOldPage = NIL_RTGCPHYS;
    18091815
    1810 #if    defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
     1816# if    defined(PGMPOOL_WITH_OPTIMIZED_DIRTY_PT) \
    18111817     && PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) \
    18121818     && (PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_PAE /* pae/32bit combo */)
    … …  
    18221828        pGstPT->a[iPTDst].u = PteSrc.u;
    18231829    }
    1824 #else
     1830# else
    18251831    Assert(!pShwPage->fDirty);
    1826 #endif
    1827 
    1828 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1832# endif
     1833
     1834# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    18291835    if (   PteSrc.n.u1Present
    18301836        && GST_IS_PTE_VALID(pVCpu, PteSrc))
    1831 #endif
    1832     {
    1833 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1837# endif
     1838    {
     1839#  if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    18341840        RTGCPHYS GCPhysPage = GST_GET_PTE_GCPHYS(PteSrc);
    1835 # endif
     1841#  endif
    18361842        PGM_A20_ASSERT_MASKED(pVCpu, GCPhysPage);
    18371843
    … …  
    18521858            }
    18531859
    1854 #ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
     1860# ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
    18551861            /* Make the page writable if necessary. */
    18561862            if (    PGM_PAGE_GET_TYPE(pPage)  == PGMPAGETYPE_RAM
    18571863                &&  (   PGM_PAGE_IS_ZERO(pPage)
    1858 # if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1864#  if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    18591865                     || (   PteSrc.n.u1Write
    1860 # else
     1866#  else
    18611867                     || (   1
    1862 # endif
     1868#  endif
    18631869                         && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
    1864 # ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
     1870#  ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
    18651871                         && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
    1866 # endif
    1867 # ifdef VBOX_WITH_PAGE_SHARING
     1872#  endif
     1873#  ifdef VBOX_WITH_PAGE_SHARING
    18681874                         && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
    1869 # endif
     1875#  endif
    18701876                        )
    18711877                     )
    … …  
    18751881                AssertRC(rc);
    18761882            }
    1877 #endif
     1883# endif
    18781884
    18791885            /*
    … …  
    18901896            else
    18911897            {
    1892 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1898# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    18931899                /*
    18941900                 * If the page or page directory entry is not marked accessed,
    … …  
    19151921                }
    19161922                else
    1917 #endif
     1923# endif
    19181924                {
    19191925                    STAM_COUNTER_INC(&pVCpu->pgm.s.CTX_SUFF(pStats)->CTX_MID_Z(Stat,DirtyPageSkipped));
    1920 #if PGM_SHW_TYPE == PGM_TYPE_EPT
     1926# if PGM_SHW_TYPE == PGM_TYPE_EPT
    19211927                    PteDst.u             = PGM_PAGE_GET_HCPHYS(pPage);
    19221928                    PteDst.n.u1Present   = 1;
    … …  
    19261932                    PteDst.n.u3EMT       = VMX_EPT_MEMTYPE_WB;
    19271933                    /* PteDst.n.u1Size = 0 */
    1928 #else
     1934# else
    19291935                    SHW_PTE_SET(PteDst, fGstShwPteFlags | PGM_PAGE_GET_HCPHYS(pPage));
    1930 #endif
     1936# endif
    19311937                }
    19321938
    … …  
    19671973             * Update statistics and commit the entry.
    19681974             */
    1969 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1975# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    19701976            if (!PteSrc.n.u1Global)
    19711977                pShwPage->fSeenNonGlobal = true;
    1972 #endif
     1978# endif
    19731979            SHW_PTE_ATOMIC_SET2(*pPteDst, PteDst);
    19741980            return;
    … …  
    19781984        Log2(("SyncPageWorker: invalid address in Pte\n"));
    19791985    }
    1980 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     1986# if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
    19811987    else if (!PteSrc.n.u1Present)
    19821988        Log2(("SyncPageWorker: page not present in Pte\n"));
    19831989    else
    19841990        Log2(("SyncPageWorker: invalid Pte\n"));
    1985 #endif
     1991# endif
    19861992
    19871993    /*
    … …  
    20242030    PGM_LOCK_ASSERT_OWNER(pVM);
    20252031
    2026 #if    (   PGM_GST_TYPE == PGM_TYPE_32BIT \
     2032# if   (   PGM_GST_TYPE == PGM_TYPE_32BIT \
    20272033        || PGM_GST_TYPE == PGM_TYPE_PAE \
    20282034        || PGM_GST_TYPE == PGM_TYPE_AMD64) \
    … …  
    20342040    Assert(PdeSrc.n.u1Present);
    20352041    Assert(cPages);
    2036 # if 0 /* rarely useful; leave for debugging. */
     2042#  if 0 /* rarely useful; leave for debugging. */
    20372043    STAM_COUNTER_INC(&pVCpu->pgm.s.StatSyncPagePD[(GCPtrPage >> GST_PD_SHIFT) & GST_PD_MASK]);
    2038 # endif
     2044#  endif
    20392045
    20402046    /*
    20412047     * Get the shadow PDE, find the shadow page table in the pool.
    20422048     */
    2043 # if PGM_SHW_TYPE == PGM_TYPE_32BIT
     2049#  if PGM_SHW_TYPE == PGM_TYPE_32BIT
    20442050    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
    20452051    PX86PDE         pPdeDst  = pgmShwGet32BitPDEPtr(pVCpu, GCPtrPage);
    … …  
    20492055    Assert(pShwPde);
    20502056
    2051 # elif PGM_SHW_TYPE == PGM_TYPE_PAE
     2057#  elif PGM_SHW_TYPE == PGM_TYPE_PAE
    20522058    const unsigned  iPDDst  = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
    20532059    PPGMPOOLPAGE    pShwPde = NULL;
    … …  
    20622068    PX86PDEPAE pPdeDst = &pPDDst->a[iPDDst];
    20632069
    2064 # elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     2070#  elif PGM_SHW_TYPE == PGM_TYPE_AMD64
    20652071    const unsigned  iPDDst   = (GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK;
    20662072    const unsigned  iPdpt    = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    … …  
    20722078    Assert(pPDDst && pPdptDst);
    20732079    PX86PDEPAE      pPdeDst = &pPDDst->a[iPDDst];
    2074 # endif
     2080#  endif
    20752081    SHWPDE          PdeDst   = *pPdeDst;
    20762082
    … …  
    20962102    Assert(pShwPage);
    20972103
    2098 # if PGM_GST_TYPE == PGM_TYPE_AMD64
     2104#  if PGM_GST_TYPE == PGM_TYPE_AMD64
    20992105    /* Fetch the pgm pool shadow descriptor. */
    21002106    PPGMPOOLPAGE    pShwPde  = pgmPoolGetPage(pPool, pPdptDst->a[iPdpt].u & X86_PDPE_PG_MASK);
    21012107    Assert(pShwPde);
    2102 # endif
     2108#  endif
    21032109
    21042110    /*
    … …  
    21112117    {
    21122118        GCPhys = GST_GET_PDE_GCPHYS(PdeSrc);
    2113 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
     2119#  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
    21142120        /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
    21152121        GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | ((iPDDst & 1) * (PAGE_SIZE / 2)));
    2116 # endif
     2122#  endif
    21172123    }
    21182124    else
    21192125    {
    21202126        GCPhys = GST_GET_BIG_PDE_GCPHYS(pVM, PdeSrc);
    2121 # if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
     2127#  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
    21222128        /* Select the right PDE as we're emulating a 4MB page directory with two 2 MB shadow PDEs.*/
    21232129        GCPhys = PGM_A20_APPLY(pVCpu, GCPhys | (GCPtrPage & (1 << X86_PD_PAE_SHIFT)));
    2124 # endif
     2130#  endif
    21252131    }
    21262132    /** @todo This doesn't check the G bit of 2/4MB pages. FIXME */
    … …  
    21302136        &&  PdeSrc.n.u1User == PdeDst.n.u1User
    21312137        &&  (PdeSrc.n.u1Write == PdeDst.n.u1Write || !PdeDst.n.u1Write)
    2132 # if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
     2138#  if PGM_WITH_NX(PGM_GST_TYPE, PGM_SHW_TYPE)
    21332139        &&  (PdeSrc.n.u1NoExecute == PdeDst.n.u1NoExecute || !GST_IS_NX_ACTIVE(pVCpu))
    2134 # endif
     2140#  endif
    21352141       )
    21362142    {
    … …  
    21522158                if (RT_SUCCESS(rc))
    21532159                {
    2154 # ifdef PGM_SYNC_N_PAGES
     2160#  ifdef PGM_SYNC_N_PAGES
    21552161                    Assert(cPages == 1 || !(uErr & X86_TRAP_PF_P));
    21562162                    if (    cPages > 1
    … …  
    21662172                         */
    21672173                        unsigned        iPTDst      = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
    2168 #  if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
     2174#   if PGM_SHW_TYPE == PGM_TYPE_PAE && PGM_GST_TYPE == PGM_TYPE_32BIT
    21692175                        /* Select the right PDE as we're emulating a 4kb page table with 2 shadow page tables. */
    21702176                        const unsigned  offPTSrc    = ((GCPtrPage >> SHW_PD_SHIFT) & 1) * 512;
    2171 #  else
     2177#   else
    21722178                        const unsigned  offPTSrc    = 0;
    2173 #  endif
     2179#   endif
    21742180                        const unsigned  iPTDstEnd   = RT_MIN(iPTDst + PGM_SYNC_NR_PAGES / 2, RT_ELEMENTS(pPTDst->a));
    21752181                        if (iPTDst < PGM_SYNC_NR_PAGES / 2)
    … …  
    21872193                                RTGCPTR GCPtrCurPage = (GCPtrPage & ~(RTGCPTR)(GST_PT_MASK << GST_PT_SHIFT)) | ((offPTSrc + iPTDst) << PAGE_SHIFT);
    21882194                                NOREF(GCPtrCurPage);
    2189 #  ifdef VBOX_WITH_RAW_MODE_NOT_R0
     2195#   ifdef VBOX_WITH_RAW_MODE_NOT_R0
    21902196                                /*
    21912197                                 * Assuming kernel code will be marked as supervisor - and not as user level
    … …  
    22002206                                         && PGM_PAGE_HAS_ACTIVE_HANDLERS(pPage))
    22012207                                   )
    2202 #  endif /* else: CSAM not active */
     2208#   endif /* else: CSAM not active */
    22032209                                   PGM_BTH_NAME(SyncPageWorker)(pVCpu, &pPTDst->a[iPTDst], PdeSrc, *pPteSrc, pShwPage, iPTDst);
    22042210                                Log2(("SyncPage: 4K+ %RGv PteSrc:{P=%d RW=%d U=%d raw=%08llx} PteDst=%08llx%s\n",
    … …  
    22132219                    }
    22142220                    else
    2215 # endif /* PGM_SYNC_N_PAGES */
     2221#  endif /* PGM_SYNC_N_PAGES */
    22162222                    {
    22172223                        const unsigned iPTSrc = (GCPtrPage >> GST_PT_SHIFT) & GST_PT_MASK;
    … …  
    22492255                    AssertFatalMsg(!PGM_PAGE_IS_BALLOONED(pPage), ("Unexpected ballooned page at %RGp\n", GCPhys));
    22502256
    2251 # ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
     2257#  ifndef VBOX_WITH_NEW_LAZY_PAGE_ALLOC
    22522258                    /* Try to make the page writable if necessary. */
    22532259                    if (    PGM_PAGE_GET_TYPE(pPage)  == PGMPAGETYPE_RAM
    … …  
    22552261                             || (   PdeSrc.n.u1Write
    22562262                                 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_ALLOCATED
    2257 #  ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
     2263#   ifdef VBOX_WITH_REAL_WRITE_MONITORED_PAGES
    22582264                                 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_WRITE_MONITORED
    2259 #  endif
    2260 #  ifdef VBOX_WITH_PAGE_SHARING
     2265#   endif
     2266#   ifdef VBOX_WITH_PAGE_SHARING
    22612267                                 && PGM_PAGE_GET_STATE(pPage) != PGM_PAGE_STATE_SHARED
    2262 #  endif
     2268#   endif
    22632269                                 )
    22642270                             )
    … …  
    22682274                        AssertRC(rc);
    22692275                    }
    2270 # endif
     2276#  endif
    22712277
    22722278                    /*
    … …  
    23622368
    23632369
    2364 #elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
     2370# elif (PGM_GST_TYPE == PGM_TYPE_REAL || PGM_GST_TYPE == PGM_TYPE_PROT) \
    23652371    && !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
    23662372    && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
    … …  
    23682374    NOREF(PdeSrc);
    23692375
    2370 # ifdef PGM_SYNC_N_PAGES
     2376#  ifdef PGM_SYNC_N_PAGES
    23712377    /*
    23722378     * Get the shadow PDE, find the shadow page table in the pool.
    23732379     */
    2374 #  if PGM_SHW_TYPE == PGM_TYPE_32BIT
     2380#   if PGM_SHW_TYPE == PGM_TYPE_32BIT
    23752381    X86PDE          PdeDst = pgmShwGet32BitPDE(pVCpu, GCPtrPage);
    23762382
    2377 #  elif PGM_SHW_TYPE == PGM_TYPE_PAE
     2383#   elif PGM_SHW_TYPE == PGM_TYPE_PAE
    23782384    X86PDEPAE       PdeDst = pgmShwGetPaePDE(pVCpu, GCPtrPage);
    23792385
    2380 #  elif PGM_SHW_TYPE == PGM_TYPE_AMD64
     2386#   elif PGM_SHW_TYPE == PGM_TYPE_AMD64
    23812387    const unsigned  iPDDst   = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
    23822388    const unsigned  iPdpt    = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64; NOREF(iPdpt);
    … …  
    23892395    Assert(pPDDst && pPdptDst);
    23902396    PdeDst = pPDDst->a[iPDDst];
    2391 #  elif PGM_SHW_TYPE == PGM_TYPE_EPT
     2397#   elif PGM_SHW_TYPE == PGM_TYPE_EPT
    23922398    const unsigned  iPDDst = ((GCPtrPage >> SHW_PD_SHIFT) & SHW_PD_MASK);
    23932399    PEPTPD          pPDDst;
    … …  
    24022408    Assert(pPDDst);
    24032409    PdeDst = pPDDst->a[iPDDst];
    2404 #  endif
     2410#   endif
    24052411    /* In the guest SMP case we could have blocked while another VCPU reused this page table. */
    24062412    if (!PdeDst.n.u1Present)
    … …  
    24642470    }
    24652471    else
    2466 # endif /* PGM_SYNC_N_PAGES */
     2472#  endif /* PGM_SYNC_N_PAGES */
    24672473    {
    24682474        const unsigned  iPTDst       = (GCPtrPage >> SHW_PT_SHIFT) & SHW_PT_MASK;
    … …  
    24792485    return VINF_SUCCESS;
    24802486
    2481 #else
     2487# else
    24822488    NOREF(PdeSrc);
    24832489    AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
    24842490    return VERR_PGM_NOT_USED_IN_MODE;
    2485 #endif
     2491# endif
    24862492}
    24872493
    2488 
    2489 #if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE)
     2494#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
     2495#if PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
    24902496
    24912497/**
    … …  
    27352741}
    27362742
    2737 #endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) */
    2738 
     2743#endif /* PGM_WITH_PAGING(PGM_GST_TYPE, PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
    27392744
    27402745/**
    … …  
    27742779     || PGM_GST_TYPE == PGM_TYPE_PAE \
    27752780     || PGM_GST_TYPE == PGM_TYPE_AMD64) \
    2776  && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     2781 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
     2782 && PGM_SHW_TYPE != PGM_TYPE_NONE
    27772783    int             rc       = VINF_SUCCESS;
    27782784
    … …  
    32323238    && !PGM_TYPE_IS_NESTED(PGM_SHW_TYPE) \
    32333239    && (PGM_SHW_TYPE != PGM_TYPE_EPT || PGM_GST_TYPE == PGM_TYPE_PROT) \
     3240    && PGM_SHW_TYPE != PGM_TYPE_NONE \
    32343241    && !defined(IN_RC)
    32353242    NOREF(iPDSrc); NOREF(pPDSrc);
    … …  
    34703477     || PGM_GST_TYPE == PGM_TYPE_PAE \
    34713478     || PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
    3472  && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     3479 && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
     3480 && PGM_SHW_TYPE != PGM_TYPE_NONE
    34733481    /*
    34743482     * Check that all Guest levels thru the PDE are present, getting the
    … …  
    35833591    return rc;
    35843592
    3585 #elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     3593#elif PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NONE
    35863594    NOREF(pVCpu); NOREF(GCPtrPage);
    35873595    return VINF_SUCCESS; /* ignore */
    … …  
    36183626       || PGM_GST_TYPE == PGM_TYPE_PAE \
    36193627       || PGM_GST_TYPE == PGM_TYPE_AMD64 ) \
    3620     && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     3628    && !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) \
     3629    && PGM_SHW_TYPE != PGM_TYPE_NONE
    36213630
    36223631# ifdef VBOX_WITH_RAW_MODE_NOT_R0
    … …  
    37783787#else  /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
    37793788
    3780     AssertReleaseMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
     3789    AssertLogRelMsgFailed(("Shw=%d Gst=%d is not implemented!\n", PGM_GST_TYPE, PGM_SHW_TYPE));
    37813790    return VERR_PGM_NOT_USED_IN_MODE;
    37823791#endif /* PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
    … …  
    38053814    LogFlow(("SyncCR3 FF=%d fGlobal=%d\n", !!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3), fGlobal));
    38063815
    3807 #if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     3816#if !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE
    38083817
    38093818    pgmLock(pVM);
    … …  
    38303839#endif /* !NESTED && !EPT */
    38313840
    3832 #if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
    3833     /*
    3834      * Nested / EPT - almost no work.
     3841#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NONE
     3842    /*
     3843     * Nested / EPT / None - No work.
    38353844     */
    38363845    Assert(!pgmMapAreMappingsEnabled(pVM));
    … …  
    38973906{
    38983907    NOREF(pVCpu); NOREF(cr3); NOREF(cr4); NOREF(GCPtr); NOREF(cb);
    3899 #if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     3908#if PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NONE
    39003909    return 0;
    39013910#else
    … …  
    46394648# endif /* GST is in {32BIT, PAE, AMD64} */
    46404649    return cErrors;
    4641 #endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) */
     4650#endif /* !PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE) && PGM_SHW_TYPE != PGM_TYPE_NONE */
    46424651}
    46434652#endif /* VBOX_STRICT */
    … …  
    47784787#endif
    47794788
    4780     /* Update shadow paging info for guest modes with paging (32, pae, 64). */
     4789    /*
     4790     * Update shadow paging info for guest modes with paging (32-bit, PAE, AMD64).
     4791     */
    47814792# if  (   (   PGM_SHW_TYPE == PGM_TYPE_32BIT \
    47824793           || PGM_SHW_TYPE == PGM_TYPE_PAE    \

  • trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

    r73273 r73324  
    152152# define SHW_PT_MASK                    X86_PT_PAE_MASK
    153153
    154 # if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
     154# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64 || /* whatever: */ PGM_SHW_TYPE == PGM_TYPE_NONE
    155155#  define SHW_PDPT_SHIFT                X86_PDPT_SHIFT
    156156#  define SHW_PDPT_MASK                 X86_PDPT_MASK_AMD64
    … …  
    167167#  error "Misconfigured PGM_SHW_TYPE or something..."
    168168# endif
     169#endif
     170
     171#if PGM_SHW_TYPE == PGM_TYPE_NONE && PGM_TYPE_IS_NESTED_OR_EPT(PGM_SHW_TYPE)
     172# error "PGM_TYPE_IS_NESTED_OR_EPT is true for PGM_TYPE_NONE!"
    169173#endif
    170174
    … …  
    283287PGM_SHW_DECL(int, GetPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, uint64_t *pfFlags, PRTHCPHYS pHCPhys)
    284288{
     289#if PGM_SHW_TYPE == PGM_TYPE_NONE
     290    RT_NOREF(pVCpu, GCPtr);
     291    AssertFailed();
     292    *pfFlags = 0;
     293    *pHCPhys = NIL_RTHCPHYS;
     294    return VERR_PGM_SHW_NONE_IPE;
     295
     296#else  /* PGM_SHW_TYPE != PGM_TYPE_NONE */
    285297    PVM pVM = pVCpu->CTX_SUFF(pVM);
    286298
    … …  
    290302     * Get the PDE.
    291303     */
    292 #if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
     304# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
    293305    X86PDEPAE Pde;
    294306
    … …  
    322334    Pde.n.u1NoExecute |= Pml4e.n.u1NoExecute | Pdpe.lm.u1NoExecute;
    323335
    324 #elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
     336# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
    325337    X86PDEPAE       Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
    326338
    327 #elif PGM_SHW_TYPE == PGM_TYPE_EPT
     339# elif PGM_SHW_TYPE == PGM_TYPE_EPT
    328340    const unsigned  iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
    329341    PEPTPD          pPDDst;
    … …  
    339351    Pde = pPDDst->a[iPd];
    340352
    341 #elif PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
     353# elif PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
    342354    X86PDE          Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
    343 #else
    344 # error "Misconfigured PGM_SHW_TYPE or something..."
    345 #endif
     355# else
     356#  error "Misconfigured PGM_SHW_TYPE or something..."
     357# endif
    346358    if (!Pde.n.u1Present)
    347359        return VERR_PAGE_TABLE_NOT_PRESENT;
    … …  
    358370        {
    359371            *pfFlags = (Pde.u & ~SHW_PDE_PG_MASK);
    360 #if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
     372# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
    361373            if (   (Pde.u & X86_PTE_PAE_NX)
    362 # if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
     374#  if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
    363375                && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
    364 # endif
     376#  endif
    365377               )
    366378                *pfFlags |= X86_PTE_PAE_NX;
    367 #endif
     379# endif
    368380        }
    369381
    … …  
    386398    else /* mapping: */
    387399    {
    388 #if  PGM_SHW_TYPE == PGM_TYPE_AMD64 \
     400# if  PGM_SHW_TYPE == PGM_TYPE_AMD64 \
    389401  || PGM_SHW_TYPE == PGM_TYPE_EPT \
    390402  || defined(PGM_WITHOUT_MAPPINGS)
    391403        AssertFailed(); /* can't happen */
    392404        pPT = NULL;     /* shut up MSC */
    393 #else
     405# else
    394406        Assert(pgmMapAreMappingsEnabled(pVM));
    395407
    396408        PPGMMAPPING pMap = pgmGetMapping(pVM, (RTGCPTR)GCPtr);
    397409        AssertMsgReturn(pMap, ("GCPtr=%RGv\n", GCPtr), VERR_PGM_MAPPING_IPE);
    398 # if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
     410#  if PGM_SHW_TYPE == PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT
    399411        pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(pPT);
    400 # else /* PAE */
     412#  else /* PAE */
    401413        pPT = pMap->aPTs[(GCPtr - pMap->GCPtr) >> X86_PD_SHIFT].CTX_SUFF(paPaePTs);
    402 # endif
    403 #endif
     414#  endif
     415# endif
    404416    }
    405417    const unsigned  iPt = (GCPtr >> SHW_PT_SHIFT) & SHW_PT_MASK;
    … …  
    418430                 & ((Pde.u & (X86_PTE_RW | X86_PTE_US)) | ~(uint64_t)(X86_PTE_RW | X86_PTE_US));
    419431
    420 #if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
     432# if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE) || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
    421433        /* The NX bit is determined by a bitwise OR between the PT and PD */
    422434        if (   ((SHW_PTE_GET_U(Pte) | Pde.u) & X86_PTE_PAE_NX)
    423 # if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
     435#  if PGM_WITH_NX(PGM_SHW_TYPE, PGM_SHW_TYPE)
    424436            && CPUMIsGuestNXEnabled(pVCpu) /** @todo why do we have to check the guest state here? */
    425 # endif
     437#  endif
    426438           )
    427439            *pfFlags |= X86_PTE_PAE_NX;
    428 #endif
     440# endif
    429441    }
    430442
    … …  
    433445
    434446    return VINF_SUCCESS;
     447#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
    435448}
    436449
    … …  
    453466PGM_SHW_DECL(int, ModifyPage)(PVMCPU pVCpu, RTGCUINTPTR GCPtr, size_t cb, uint64_t fFlags, uint64_t fMask, uint32_t fOpFlags)
    454467{
     468#if PGM_SHW_TYPE == PGM_TYPE_NONE
     469    RT_NOREF(pVCpu, GCPtr, cb, fFlags, fMask, fOpFlags);
     470    AssertFailed();
     471    return VERR_PGM_SHW_NONE_IPE;
     472
     473#else  /* PGM_SHW_TYPE != PGM_TYPE_NONE */
    455474    PVM pVM = pVCpu->CTX_SUFF(pVM);
    456     int rc;
    457 
    458475    PGM_LOCK_ASSERT_OWNER(pVM);
    459476
    … …  
    461478     * Walk page tables and pages till we're done.
    462479     */
     480    int rc;
    463481    for (;;)
    464482    {
    … …  
    466484         * Get the PDE.
    467485         */
    468 #if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
     486# if PGM_SHW_TYPE == PGM_TYPE_AMD64 || PGM_SHW_TYPE == PGM_TYPE_NESTED_AMD64
    469487        X86PDEPAE       Pde;
    470488        /* PML4 */
    … …  
    491509        Pde = pPd->a[iPd];
    492510
    493 #elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
     511# elif PGM_SHW_TYPE == PGM_TYPE_PAE || PGM_SHW_TYPE == PGM_TYPE_NESTED_PAE
    494512        X86PDEPAE       Pde = pgmShwGetPaePDE(pVCpu, GCPtr);
    495513
    496 #elif PGM_SHW_TYPE == PGM_TYPE_EPT
     514# elif PGM_SHW_TYPE == PGM_TYPE_EPT
    497515        const unsigned  iPd = ((GCPtr >> SHW_PD_SHIFT) & SHW_PD_MASK);
    498516        PEPTPD          pPDDst;
    … …  
    508526        Pde = pPDDst->a[iPd];
    509527
    510 #else /* PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
     528# else /* PGM_TYPE_32BIT || PGM_SHW_TYPE == PGM_TYPE_NESTED_32BIT */
    511529        X86PDE          Pde = pgmShwGet32BitPDE(pVCpu, GCPtr);
    512 #endif
     530# endif
    513531        if (!Pde.n.u1Present)
    514532            return VERR_PAGE_TABLE_NOT_PRESENT;
    … …  
    566584
    567585                SHW_PTE_ATOMIC_SET2(pPT->a[iPTE], NewPte);
    568 #if PGM_SHW_TYPE == PGM_TYPE_EPT
     586# if PGM_SHW_TYPE == PGM_TYPE_EPT
    569587                HMInvalidatePhysPage(pVM, (RTGCPHYS)GCPtr);
    570 #else
     588# else
    571589                PGM_INVL_PG_ALL_VCPU(pVM, GCPtr);
    572 #endif
     590# endif
    573591            }
    574592
    … …  
    581599        }
    582600    }
     601#endif /* PGM_SHW_TYPE != PGM_TYPE_NONE */
    583602}
    584603
    … …  
    594613PGM_SHW_DECL(int, Relocate)(PVMCPU pVCpu, RTGCPTR offDelta)
    595614{
     615# if PGM_SHW_TYPE != PGM_TYPE_NONE
    596616    pVCpu->pgm.s.pShwPageCR3RC += offDelta;
     617# else
     618    RT_NOREF(pVCpu, offDelta);
     619# endif
    597620    return VINF_SUCCESS;
    598621}

  • trunk/src/VBox/VMM/VMMR3/PGM.cpp

    r73271 r73324  
    25392539    AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
    25402540
    2541     Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
     2541    Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL || pVCpu->pgm.s.enmShadowMode == PGMMODE_NONE);
    25422542    AssertMsg(   pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED_32BIT
    25432543              || CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),

  • trunk/src/VBox/VMM/VMMR3/VMMSwitcher.cpp

    r73097 r73324  
    10111011static RTRCPTR vmmR3SwitcherGetHyperGDT(PVM pVM)
    10121012{
    1013     if (HMIsRawModeCtxNeeded(pVM))
     1013    if (VM_IS_RAW_MODE_ENABLED(pVM) || HMIsRawModeCtxNeeded(pVM))
    10141014        return SELMGetHyperGDT(pVM);
    10151015# if HC_ARCH_BITS != 32

  • trunk/src/VBox/VMM/include/PGMInternal.h

    r73285 r73324  
    214214#define PGM_TYPE_NESTED_AMD64           8
    215215#define PGM_TYPE_EPT                    9
    216 #define PGM_TYPE_MAX                    PGM_TYPE_EPT
    217 #define PGM_TYPE_END                    (PGM_TYPE_EPT + 1)
     216#define PGM_TYPE_NONE                   10 /**< Dummy shadow paging mode for NEM. */
     217#define PGM_TYPE_END                    (PGM_TYPE_NONE + 1)
    218218#define PGM_TYPE_FIRST_SHADOW           PGM_TYPE_32BIT /**< The first type used by shadow paging. */
    219219/** @} */
    … …  
    30233023#define PGM_SHW_NAME_RC_EPT_STR(name)                   "pgmRCShwEPT" #name
    30243024#define PGM_SHW_NAME_R0_EPT_STR(name)                   "pgmR0ShwEPT" #name
     3025#define PGM_SHW_NAME_NONE(name)                         PGM_CTX(pgm,ShwNone##name)
     3026#define PGM_SHW_NAME_RC_NONE_STR(name)                  "pgmRCShwNone" #name
     3027#define PGM_SHW_NAME_R0_NONE_STR(name)                  "pgmR0ShwNone" #name
    30253028#define PGM_SHW_DECL(type, name)                        PGM_CTX_DECL(type) PGM_SHW_NAME(name)
    30263029
    … …  
    30553058#define PGM_BTH_NAME_EPT_PAE(name)                      PGM_CTX(pgm,BthEPTPAE##name)
    30563059#define PGM_BTH_NAME_EPT_AMD64(name)                    PGM_CTX(pgm,BthEPTAMD64##name)
     3060#define PGM_BTH_NAME_NONE_REAL(name)                    PGM_CTX(pgm,BthNoneReal##name)
     3061#define PGM_BTH_NAME_NONE_PROT(name)                    PGM_CTX(pgm,BthNoneProt##name)
     3062#define PGM_BTH_NAME_NONE_32BIT(name)                   PGM_CTX(pgm,BthNone32Bit##name)
     3063#define PGM_BTH_NAME_NONE_PAE(name)                     PGM_CTX(pgm,BthNonePAE##name)
     3064#define PGM_BTH_NAME_NONE_AMD64(name)                   PGM_CTX(pgm,BthNoneAMD64##name)
    30573065
    30583066#define PGM_BTH_NAME_RC_32BIT_REAL_STR(name)            "pgmRCBth32BitReal" #name
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