VirtualBox

Changeset 73340 in vbox for trunk/src/VBox/VMM/include


Ignore:
Timestamp:
Jul 24, 2018 3:12:17 AM (6 years ago)
Author:
vboxsync
Message:

VMM/GIM: Address todo mentioned in r123944.

Location:
trunk/src/VBox/VMM/include
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/include/GIMHvInternal.h

    r73335 r73340  
    224224 */
    225225/** Start of range 0. */
    226 #define MSR_GIM_HV_RANGE0_START                   UINT32_C(0x40000000)
     226#define MSR_GIM_HV_RANGE0_FIRST                   UINT32_C(0x40000000)
    227227/** Guest OS identification (R/W) */
    228228#define MSR_GIM_HV_GUEST_OS_ID                    UINT32_C(0x40000000)
    … …  
    234234#define MSR_GIM_HV_RESET                          UINT32_C(0x40000003)
    235235/** End of range 0. */
    236 #define MSR_GIM_HV_RANGE0_END                     MSR_GIM_HV_RESET
     236#define MSR_GIM_HV_RANGE0_LAST                    MSR_GIM_HV_RESET
    237237
    238238/** Start of range 1. */
    239 #define MSR_GIM_HV_RANGE1_START                   UINT32_C(0x40000010)
     239#define MSR_GIM_HV_RANGE1_FIRST                   UINT32_C(0x40000010)
    240240/** Virtual processor's (VCPU) runtime (R) */
    241241#define MSR_GIM_HV_VP_RUNTIME                     UINT32_C(0x40000010)
    242242/** End of range 1. */
    243 #define MSR_GIM_HV_RANGE1_END                     MSR_GIM_HV_VP_RUNTIME
     243#define MSR_GIM_HV_RANGE1_LAST                    MSR_GIM_HV_VP_RUNTIME
    244244
    245245/** Start of range 2. */
    246 #define MSR_GIM_HV_RANGE2_START                   UINT32_C(0x40000020)
     246#define MSR_GIM_HV_RANGE2_FIRST                   UINT32_C(0x40000020)
    247247/** Per-VM reference counter (R) */
    248248#define MSR_GIM_HV_TIME_REF_COUNT                 UINT32_C(0x40000020)
    … …  
    254254#define MSR_GIM_HV_APIC_FREQ                      UINT32_C(0x40000023)
    255255/** End of range 2. */
    256 #define MSR_GIM_HV_RANGE2_END                     MSR_GIM_HV_APIC_FREQ
     256#define MSR_GIM_HV_RANGE2_LAST                    MSR_GIM_HV_APIC_FREQ
    257257
    258258/** Start of range 3. */
    259 #define MSR_GIM_HV_RANGE3_START                   UINT32_C(0x40000070)
     259#define MSR_GIM_HV_RANGE3_FIRST                   UINT32_C(0x40000070)
    260260/** Access to APIC EOI (End-Of-Interrupt) register (W) */
    261261#define MSR_GIM_HV_EOI                            UINT32_C(0x40000070)
    … …  
    267267#define MSR_GIM_HV_APIC_ASSIST_PAGE               UINT32_C(0x40000073)
    268268/** End of range 3. */
    269 #define MSR_GIM_HV_RANGE3_END                     MSR_GIM_HV_APIC_ASSIST_PAGE
     269#define MSR_GIM_HV_RANGE3_LAST                    MSR_GIM_HV_APIC_ASSIST_PAGE
    270270
    271271/** Start of range 4. */
    272 #define MSR_GIM_HV_RANGE4_START                   UINT32_C(0x40000080)
     272#define MSR_GIM_HV_RANGE4_FIRST                   UINT32_C(0x40000080)
    273273/** Control behaviour of synthetic interrupt controller (R/W) */
    274274#define MSR_GIM_HV_SCONTROL                       UINT32_C(0x40000080)
    … …  
    282282#define MSR_GIM_HV_EOM                            UINT32_C(0x40000084)
    283283/** End of range 4. */
    284 #define MSR_GIM_HV_RANGE4_END                     MSR_GIM_HV_EOM
     284#define MSR_GIM_HV_RANGE4_LAST                    MSR_GIM_HV_EOM
    285285
    286286/** Start of range 5. */
    287 #define MSR_GIM_HV_RANGE5_START                   UINT32_C(0x40000090)
     287#define MSR_GIM_HV_RANGE5_FIRST                   UINT32_C(0x40000090)
    288288/** Configures synthetic interrupt source 0 (R/W) */
    289289#define MSR_GIM_HV_SINT0                          UINT32_C(0x40000090)
    … …  
    319319#define MSR_GIM_HV_SINT15                         UINT32_C(0x4000009F)
    320320/** End of range 5. */
    321 #define MSR_GIM_HV_RANGE5_END                     MSR_GIM_HV_SINT15
     321#define MSR_GIM_HV_RANGE5_LAST                    MSR_GIM_HV_SINT15
    322322
    323323/** Start of range 6. */
    324 #define MSR_GIM_HV_RANGE6_START                   UINT32_C(0x400000B0)
     324#define MSR_GIM_HV_RANGE6_FIRST                   UINT32_C(0x400000B0)
    325325/** Configures register for synthetic timer 0 (R/W) */
    326326#define MSR_GIM_HV_STIMER0_CONFIG                 UINT32_C(0x400000B0)
    … …  
    340340#define MSR_GIM_HV_STIMER3_COUNT                  UINT32_C(0x400000B7)
    341341/** End of range 6. */
    342 #define MSR_GIM_HV_RANGE6_END                     MSR_GIM_HV_STIMER3_COUNT
     342#define MSR_GIM_HV_RANGE6_LAST                    MSR_GIM_HV_STIMER3_COUNT
    343343
    344344/** Start of range 7. */
    345 #define MSR_GIM_HV_RANGE7_START                   UINT32_C(0x400000C1)
     345#define MSR_GIM_HV_RANGE7_FIRST                   UINT32_C(0x400000C1)
    346346/** Trigger to transition to power state C1 (R) */
    347347#define MSR_GIM_HV_POWER_STATE_TRIGGER_C1         UINT32_C(0x400000C1)
    … …  
    351351#define MSR_GIM_HV_POWER_STATE_TRIGGER_C3         UINT32_C(0x400000C3)
    352352/** End of range 7. */
    353 #define MSR_GIM_HV_RANGE7_END                     MSR_GIM_HV_POWER_STATE_TRIGGER_C3
     353#define MSR_GIM_HV_RANGE7_LAST                    MSR_GIM_HV_POWER_STATE_TRIGGER_C3
    354354
    355355/** Start of range 8. */
    356 #define MSR_GIM_HV_RANGE8_START                   UINT32_C(0x400000D1)
     356#define MSR_GIM_HV_RANGE8_FIRST                   UINT32_C(0x400000D1)
    357357/** Configure the recipe for power state transitions to C1 (R/W) */
    358358#define MSR_GIM_HV_POWER_STATE_CONFIG_C1          UINT32_C(0x400000D1)
    … …  
    362362#define MSR_GIM_HV_POWER_STATE_CONFIG_C3          UINT32_C(0x400000D3)
    363363/** End of range 8. */
    364 #define MSR_GIM_HV_RANGE8_END                     MSR_GIM_HV_POWER_STATE_CONFIG_C3
     364#define MSR_GIM_HV_RANGE8_LAST                    MSR_GIM_HV_POWER_STATE_CONFIG_C3
    365365
    366366/** Start of range 9. */
    367 #define MSR_GIM_HV_RANGE9_START                   UINT32_C(0x400000E0)
     367#define MSR_GIM_HV_RANGE9_FIRST                   UINT32_C(0x400000E0)
    368368/** Map the guest's retail partition stats page (R/W) */
    369369#define MSR_GIM_HV_STATS_PART_RETAIL_PAGE         UINT32_C(0x400000E0)
    … …  
    375375#define MSR_GIM_HV_STATS_VP_INTERNAL_PAGE         UINT32_C(0x400000E3)
    376376/** End of range 9. */
    377 #define MSR_GIM_HV_RANGE9_END                     MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
     377#define MSR_GIM_HV_RANGE9_LAST                    MSR_GIM_HV_STATS_VP_INTERNAL_PAGE
    378378
    379379/** Start of range 10. */
    380 #define MSR_GIM_HV_RANGE10_START                  UINT32_C(0x400000F0)
     380#define MSR_GIM_HV_RANGE10_FIRST                  UINT32_C(0x400000F0)
    381381/** Trigger the guest's transition to idle power state (R) */
    382382#define MSR_GIM_HV_GUEST_IDLE                     UINT32_C(0x400000F0)
    … …  
    392392#define MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER     UINT32_C(0x400000F5)
    393393/** End of range 10. */
    394 #define MSR_GIM_HV_RANGE10_END                    MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
     394#define MSR_GIM_HV_RANGE10_LAST                   MSR_GIM_HV_SYNTH_DEBUG_PENDING_BUFFER
    395395
    396396/** Start of range 11. */
    397 #define MSR_GIM_HV_RANGE11_START                  UINT32_C(0x400000FF)
     397#define MSR_GIM_HV_RANGE11_FIRST                  UINT32_C(0x400000FF)
    398398/** Undocumented debug options MSR. */
    399399#define MSR_GIM_HV_DEBUG_OPTIONS_MSR              UINT32_C(0x400000FF)
    400400/** End of range 11. */
    401 #define MSR_GIM_HV_RANGE11_END                    MSR_GIM_HV_DEBUG_OPTIONS_MSR
     401#define MSR_GIM_HV_RANGE11_LAST                   MSR_GIM_HV_DEBUG_OPTIONS_MSR
    402402
    403403/** Start of range 12. */
    404 #define MSR_GIM_HV_RANGE12_START                  UINT32_C(0x40000100)
     404#define MSR_GIM_HV_RANGE12_FIRST                  UINT32_C(0x40000100)
    405405/** Guest crash MSR 0. */
    406406#define MSR_GIM_HV_CRASH_P0                       UINT32_C(0x40000100)
    … …  
    416416#define MSR_GIM_HV_CRASH_CTL                      UINT32_C(0x40000105)
    417417/** End of range 12. */
    418 #define MSR_GIM_HV_RANGE12_END                    MSR_GIM_HV_CRASH_CTL
    419 /** @} */
    420 
    421 /**
    422  *
    423  * @todo r=bird: Incorrect use of the term 'END' here.
    424  *               The correct term is 'LAST' as it's inclusive.
    425  *               'END' is the term for exclusive range terminators.
    426  *
    427  *               See Coding guidelines.
    428  *
    429  */
    430 AssertCompile(MSR_GIM_HV_RANGE0_START  <= MSR_GIM_HV_RANGE0_END);
    431 AssertCompile(MSR_GIM_HV_RANGE1_START  <= MSR_GIM_HV_RANGE1_END);
    432 AssertCompile(MSR_GIM_HV_RANGE2_START  <= MSR_GIM_HV_RANGE2_END);
    433 AssertCompile(MSR_GIM_HV_RANGE3_START  <= MSR_GIM_HV_RANGE3_END);
    434 AssertCompile(MSR_GIM_HV_RANGE4_START  <= MSR_GIM_HV_RANGE4_END);
    435 AssertCompile(MSR_GIM_HV_RANGE5_START  <= MSR_GIM_HV_RANGE5_END);
    436 AssertCompile(MSR_GIM_HV_RANGE6_START  <= MSR_GIM_HV_RANGE6_END);
    437 AssertCompile(MSR_GIM_HV_RANGE7_START  <= MSR_GIM_HV_RANGE7_END);
    438 AssertCompile(MSR_GIM_HV_RANGE8_START  <= MSR_GIM_HV_RANGE8_END);
    439 AssertCompile(MSR_GIM_HV_RANGE9_START  <= MSR_GIM_HV_RANGE9_END);
    440 AssertCompile(MSR_GIM_HV_RANGE10_START <= MSR_GIM_HV_RANGE10_END);
    441 AssertCompile(MSR_GIM_HV_RANGE11_START <= MSR_GIM_HV_RANGE11_END);
     418#define MSR_GIM_HV_RANGE12_LAST                   MSR_GIM_HV_CRASH_CTL
     419/** @} */
     420
     421AssertCompile(MSR_GIM_HV_RANGE0_FIRST  <= MSR_GIM_HV_RANGE0_LAST);
     422AssertCompile(MSR_GIM_HV_RANGE1_FIRST  <= MSR_GIM_HV_RANGE1_LAST);
     423AssertCompile(MSR_GIM_HV_RANGE2_FIRST  <= MSR_GIM_HV_RANGE2_LAST);
     424AssertCompile(MSR_GIM_HV_RANGE3_FIRST  <= MSR_GIM_HV_RANGE3_LAST);
     425AssertCompile(MSR_GIM_HV_RANGE4_FIRST  <= MSR_GIM_HV_RANGE4_LAST);
     426AssertCompile(MSR_GIM_HV_RANGE5_FIRST  <= MSR_GIM_HV_RANGE5_LAST);
     427AssertCompile(MSR_GIM_HV_RANGE6_FIRST  <= MSR_GIM_HV_RANGE6_LAST);
     428AssertCompile(MSR_GIM_HV_RANGE7_FIRST  <= MSR_GIM_HV_RANGE7_LAST);
     429AssertCompile(MSR_GIM_HV_RANGE8_FIRST  <= MSR_GIM_HV_RANGE8_LAST);
     430AssertCompile(MSR_GIM_HV_RANGE9_FIRST  <= MSR_GIM_HV_RANGE9_LAST);
     431AssertCompile(MSR_GIM_HV_RANGE10_FIRST <= MSR_GIM_HV_RANGE10_LAST);
     432AssertCompile(MSR_GIM_HV_RANGE11_FIRST <= MSR_GIM_HV_RANGE11_LAST);
    442433
    443434/** @name Hyper-V MSR - Reset (MSR_GIM_HV_RESET).

  • trunk/src/VBox/VMM/include/GIMKvmInternal.h

    r72469 r73340  
    5151 */
    5252/** Start of range 0. */
    53 #define MSR_GIM_KVM_RANGE0_START                   UINT32_C(0x11)
     53#define MSR_GIM_KVM_RANGE0_FIRST                   UINT32_C(0x11)
    5454/** Old, deprecated wall clock. */
    5555#define MSR_GIM_KVM_WALL_CLOCK_OLD                 UINT32_C(0x11)
    … …  
    5757#define MSR_GIM_KVM_SYSTEM_TIME_OLD                UINT32_C(0x12)
    5858/** End of range 0. */
    59 #define MSR_GIM_KVM_RANGE0_END                     MSR_GIM_KVM_SYSTEM_TIME_OLD
     59#define MSR_GIM_KVM_RANGE0_LAST                    MSR_GIM_KVM_SYSTEM_TIME_OLD
    6060
    6161/** Start of range 1. */
    62 #define MSR_GIM_KVM_RANGE1_START                   UINT32_C(0x4b564d00)
     62#define MSR_GIM_KVM_RANGE1_FIRST                   UINT32_C(0x4b564d00)
    6363/** Wall clock. */
    6464#define MSR_GIM_KVM_WALL_CLOCK                     UINT32_C(0x4b564d00)
    … …  
    7272#define MSR_GIM_KVM_EOI                            UINT32_C(0x4b564d04)
    7373/** End of range 1. */
    74 #define MSR_GIM_KVM_RANGE1_END                     MSR_GIM_KVM_EOI
    75 
    76 AssertCompile(MSR_GIM_KVM_RANGE0_START <= MSR_GIM_KVM_RANGE0_END);
    77 AssertCompile(MSR_GIM_KVM_RANGE1_START <= MSR_GIM_KVM_RANGE1_END);
     74#define MSR_GIM_KVM_RANGE1_LAST                    MSR_GIM_KVM_EOI
     75
     76AssertCompile(MSR_GIM_KVM_RANGE0_FIRST <= MSR_GIM_KVM_RANGE0_LAST);
     77AssertCompile(MSR_GIM_KVM_RANGE1_FIRST <= MSR_GIM_KVM_RANGE1_LAST);
    7878
    7979/** KVM page size.  */
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