Index: /trunk/include/VBox/err.h
===================================================================
--- /trunk/include/VBox/err.h	(revision 73388)
+++ /trunk/include/VBox/err.h	(revision 73389)
@@ -657,4 +657,6 @@
 /** Invalid/unsupported nested hardware virtualization configuration. */
 #define VERR_CPUM_INVALID_HWVIRT_CONFIG         (-1767)
+/** Invalid nested hardware virtualization feature combination. */
+#define VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO     (-1768)
 /** @} */
 
@@ -2050,10 +2052,8 @@
 /** Unable to switch due to invalid host state. */
 #define VERR_VMX_INVALID_HOST_STATE                 (-4006)
-/** IA32_FEATURE_CONTROL MSR not setup correcty (turn on VMX in the host system BIOS) */
-#define VERR_VMX_ILLEGAL_FEATURE_CONTROL_MSR        (-4007)
-/** Invalid CPU mode for VMX execution. */
-#define VERR_VMX_UNSUPPORTED_MODE                   (-4008)
-/** VMX CPU extension not available */
+/** VMX CPU extension not available in hardware. */
 #define VERR_VMX_NO_VMX                             (-4009)
+/** VMX CPU extension not supported as something went wrong during init. */
+#define VERR_VMX_NOT_SUPPORTED                      (-4010)
 /** CPU was incorrectly left in VMX root mode; incompatible with VirtualBox */
 #define VERR_VMX_IN_VMX_ROOT_MODE                   (-4011)
Index: /trunk/include/VBox/vmm/cpum.h
===================================================================
--- /trunk/include/VBox/vmm/cpum.h	(revision 73388)
+++ /trunk/include/VBox/vmm/cpum.h	(revision 73389)
@@ -1117,11 +1117,136 @@
     uint32_t        uSvmMaxAsid;
 
-    /** @todo VMX features. */
-    /** VMX: INS/OUTS VM-exit instruction info. */
+    /** @name VMX basic controls.
+     * @{ */
+    /** VMX: Supports INS/OUTS VM-exit instruction info. */
     uint32_t        fVmxInsOutInfo : 1;
-    uint32_t        fVmxPadding0 : 31;
+    /** @} */
+
+    /** @name VMX Pin-based controls.
+     * @{ */
+    /** VMX: Supports external interrupt VM-exit. */
+    uint32_t        fVmxExtIntExit : 1;
+    /** VMX: Supports NMI VM-exit. */
+    uint32_t        fVmxNmiExit : 1;
+    /** VMX: Supports Virtual NMIs. */
+    uint32_t        fVmxVirtNmi : 1;
+    /** VMX: Supports preemption timer. */
+    uint32_t        fVmxPreemptTimer : 1;
+    /** @} */
+
+    /** @name VMX Processor-based controls.
+     * @{ */
+    /** VMX: Supports Interrupt-window exiting. */
+    uint32_t        fVmxIntWindowExit : 1;
+    /** VMX: Supports TSC offsetting. */
+    uint32_t        fVmxTscOffsetting : 1;
+    /** VMX: Supports HLT exiting. */
+    uint32_t        fVmxHltExit : 1;
+    /** VMX: Supports INVLPG exiting. */
+    uint32_t        fVmxInvlpgExit : 1;
+    /** VMX: Supports MWAIT exiting. */
+    uint32_t        fVmxMwaitExit : 1;
+    /** VMX: Supports RDPMC exiting. */
+    uint32_t        fVmxRdpmcExit : 1;
+    /** VMX: Supports RDTSC exiting. */
+    uint32_t        fVmxRdtscExit : 1;
+    /** VMX: Supports CR3-load exiting. */
+    uint32_t        fVmxCr3LoadExit : 1;
+    /** VMX: Supports CR3-store exiting. */
+    uint32_t        fVmxCr3StoreExit : 1;
+    /** VMX: Supports CR8-load exiting. */
+    uint32_t        fVmxCr8LoadExit : 1;
+    /** VMX: Supports CR8-store exiting. */
+    uint32_t        fVmxCr8StoreExit : 1;
+    /** VMX: Supports TPR shadow. */
+    uint32_t        fVmxTprShadow : 1;
+    /** VMX: Supports NMI-window exiting. */
+    uint32_t        fVmxNmiWindowExit : 1;
+    /** VMX: Supports Mov-DRx exiting. */
+    uint32_t        fVmxMovDRxExit : 1;
+    /** VMX: Supports Unconditional I/O exiting. */
+    uint32_t        fVmxUncondIoExit : 1;
+    /** VMX: Supportgs I/O bitmaps. */
+    uint32_t        fVmxUseIoBitmaps : 1;
+    /** VMX: Supports Monitor Trap Flag. */
+    uint32_t        fVmxMonitorTrapFlag : 1;
+    /** VMX: Supports MSR bitmap. */
+    uint32_t        fVmxUseMsrBitmaps : 1;
+    /** VMX: Supports MONITOR exiting. */
+    uint32_t        fVmxMonitorExit : 1;
+    /** VMX: Supports PAUSE exiting. */
+    uint32_t        fVmxPauseExit : 1;
+    /** VMX: Supports secondary processor-based VM-execution controls. */
+    uint32_t        fVmxSecondaryExecCtls : 1;
+    /** @} */
+
+    /** @name VMX Secondary processor-based controls.
+     * @{ */
+    /** VMX: Supports virtualize-APIC access. */
+    uint32_t        fVmxVirtApicAccess : 1;
+    /** VMX: Supports EPT (Extended Page Tables). */
+    uint32_t        fVmxEpt : 1;
+    /** VMX: Supports descriptor-table exiting. */
+    uint32_t        fVmxDescTableExit : 1;
+    /** VMX: Supports RDTSCP. */
+    uint32_t        fVmxRdtscp : 1;
+    /** VMX: Supports virtualize-x2APIC access. */
+    uint32_t        fVmxVirtX2ApicAccess : 1;
+    /** VMX: Supports VPID. */
+    uint32_t        fVmxVpid : 1;
+    /** VMX: Supports WBIND exiting. */
+    uint32_t        fVmxWbinvdExit : 1;
+    /** VMX: Supports Unrestricted guest. */
+    uint32_t        fVmxUnrestrictedGuest : 1;
+    /** VMX: Supports Pause-loop exiting. */
+    uint32_t        fVmxPauseLoopExit : 1;
+    /** VMX: Supports INVPCID. */
+    uint32_t        fVmxInvpcid : 1;
+    /** @} */
+
+    /** @name VMX VM-entry controls.
+     * @{ */
+    /** VMX: Supports load-debug controls on VM-entry. */
+    uint32_t        fVmxEntryLoadDebugCtls : 1;
+    /** VMX: Supports IA32e mode guest. */
+    uint32_t        fVmxIa32eModeGuest : 1;
+    /** VMX: Supports load guest EFER MSR on VM-entry. */
+    uint32_t        fVmxEntryLoadEferMsr : 1;
+    /** @} */
+
+    /** @name VMX VM-exit controls.
+     * @{ */
+    /** VMX: Supports save debug controls on VM-exit. */
+    uint32_t        fVmxExitSaveDebugCtls : 1;
+    /** VMX: Supports host-address space size. */
+    uint32_t        fVmxHostAddrSpaceSize : 1;
+    /** VMX: Supports acknowledge external interrupt on VM-exit. */
+    uint32_t        fVmxExitAckExtInt : 1;
+    /** VMX: Supports save guest EFER MSR on VM-exit. */
+    uint32_t        fVmxExitSaveEferMsr : 1;
+    /** VMX: Supports load host EFER MSR on VM-exit. */
+    uint32_t        fVmxExitLoadEferMsr : 1;
+    /** VMX: Supports save VMX preemption timer on VM-exit. */
+    uint32_t        fVmxSavePreemptTimer : 1;
+    /** @} */
+
+    /** @name VMX Miscellaneous data.
+     * @{ */
+    /** VMX: Supports storing EFER.LMA on VM-exits into IA32e-mode guest field. */
+    uint32_t        fVmxExitStoreEferLma : 1;
+    /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
+     *  VMWRITE cannot modify read-only VM-exit information fields. */
+    uint32_t        fVmxVmwriteAll : 1;
+    /** VMX: Supports injection of software interrupts, ICEBP on VM-entry for zero
+     *  length instructions. */
+    uint32_t        fVmxEntryInjectSoftInt : 1;
+    /** @} */
+
+    /** VMX: Padding / reserved for future features. */
+    uint32_t        fVmxPadding0 : 16;
+    uint32_t        fVmxPadding1;
 } CPUMFEATURES;
 #ifndef VBOX_FOR_DTRACE_LIB
-AssertCompileSize(CPUMFEATURES, 32);
+AssertCompileSize(CPUMFEATURES, 40);
 #endif
 /** Pointer to a CPU feature structure. */
Index: /trunk/include/VBox/vmm/hm.h
===================================================================
--- /trunk/include/VBox/vmm/hm.h	(revision 73388)
+++ /trunk/include/VBox/vmm/hm.h	(revision 73389)
@@ -31,4 +31,5 @@
 #include <VBox/vmm/vmm.h>
 #include <VBox/vmm/hm_svm.h>
+#include <VBox/vmm/hm_vmx.h>
 #include <VBox/vmm/trpm.h>
 #include <iprt/mp.h>
@@ -133,5 +134,10 @@
 VMM_INT_DECL(bool)              HMIsSvmActive(PVM pVM);
 VMM_INT_DECL(bool)              HMIsVmxActive(PVM pVM);
+VMM_INT_DECL(bool)              HMIsVmxSupported(PVM pVM);
 VMM_INT_DECL(void)              HMHCPagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
+VMM_INT_DECL(int)               HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs);
+#if 0
+VMM_INT_DECL(int)               HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue);
+#endif
 /** @} */
 
@@ -155,8 +161,8 @@
 VMM_INT_DECL(int)               HMInvalidatePageOnAllVCpus(PVM pVM, RTGCPTR GCVirt);
 VMM_INT_DECL(int)               HMInvalidatePhysPage(PVM pVM, RTGCPHYS GCPhys);
-VMM_INT_DECL(bool)              HMIsNestedPagingActive(PVM pVM);
 VMM_INT_DECL(bool)              HMAreNestedPagingAndFullGuestExecEnabled(PVM pVM);
 VMM_INT_DECL(bool)              HMIsLongModeAllowed(PVM pVM);
-VMM_INT_DECL(bool)              HMAreMsrBitmapsAvailable(PVM pVM);
+VMM_INT_DECL(bool)              HMIsNestedPagingActive(PVM pVM);
+VMM_INT_DECL(bool)              HMIsMsrBitmapActive(PVM pVM);
 VMM_INT_DECL(bool)              HMSvmIsVGifActive(PVM pVM);
 VMM_INT_DECL(uint64_t)          HMSvmNstGstApplyTscOffset(PVMCPU pVCpu, uint64_t uTicks);
@@ -166,12 +172,14 @@
 #else /* Nops in RC: */
 # define HMFlushTLB(pVCpu)                              do { } while (0)
-# define HMIsNestedPagingActive(pVM)                    false
+# define HMFlushTLBOnAllVCpus(pVM)                      do { } while (0)
+# define HMInvalidatePageOnAllVCpus(pVM, GCVirt)        do { } while (0)
+# define HMInvalidatePhysPage(pVM,  GCVirt)             do { } while (0)
 # define HMAreNestedPagingAndFullGuestExecEnabled(pVM)  false
 # define HMIsLongModeAllowed(pVM)                       false
-# define HMAreMsrBitmapsAvailable(pVM)                  false
-# define HMFlushTLBOnAllVCpus(pVM)                      do { } while (0)
-# define HMSvmNstGstVmExitNotify(pVCpu, pCtx)           do { } while (0)
+# define HMIsNestedPagingActive(pVM)                    false
+# define HMIsMsrBitmapsActive(pVM)                      false
 # define HMSvmIsVGifActive(pVM)                         false
 # define HMSvmNstGstApplyTscOffset(pVCpu, uTicks)       (uTicks)
+# define HMSvmNstGstVmExitNotify(pVCpu, pCtx)           do { } while (0)
 #endif
 
@@ -243,5 +251,4 @@
 VMMR3DECL(const char *)         HMR3GetVmxExitName(uint32_t uExit);
 VMMR3DECL(const char *)         HMR3GetSvmExitName(uint32_t uExit);
-
 /** @} */
 #endif /* IN_RING3 */
Index: /trunk/include/VBox/vmm/hm_vmx.h
===================================================================
--- /trunk/include/VBox/vmm/hm_vmx.h	(revision 73388)
+++ /trunk/include/VBox/vmm/hm_vmx.h	(revision 73389)
@@ -831,4 +831,19 @@
 
 /**
+ * VMX tagged-TLB flush types.
+ */
+typedef enum
+{
+    VMXTLBFLUSHTYPE_EPT,
+    VMXTLBFLUSHTYPE_VPID,
+    VMXTLBFLUSHTYPE_EPT_VPID,
+    VMXTLBFLUSHTYPE_NONE
+} VMXTLBFLUSHTYPE;
+/** Pointer to a VMXTLBFLUSHTYPE enum. */
+typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
+/** Pointer to a const VMXTLBFLUSHTYPE enum. */
+typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
+
+/**
  * VMX controls MSR.
  */
@@ -852,20 +867,7 @@
 
 /**
- * VMX tagged-TLB flush types.
- */
-typedef enum
-{
-    VMXTLBFLUSHTYPE_EPT,
-    VMXTLBFLUSHTYPE_VPID,
-    VMXTLBFLUSHTYPE_EPT_VPID,
-    VMXTLBFLUSHTYPE_NONE
-} VMXTLBFLUSHTYPE;
-/** Pointer to a VMXTLBFLUSHTYPE enum. */
-typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
-/** Pointer to a const VMXTLBFLUSHTYPE enum. */
-typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
-
-/**
  * VMX MSRs.
+ * @remarks Although treated as a plain-old data (POD) in several places, please
+ *          update HMVmxGetHostMsr() if new MSRs are added here.
  */
 typedef struct VMXMSRS
@@ -888,10 +890,15 @@
     uint64_t        u64Cr4Fixed1;
     uint64_t        u64VmcsEnum;
-    uint64_t        u64Vmfunc;
+    uint64_t        u64VmFunc;
     uint64_t        u64EptVpidCaps;
+    uint64_t        a_u64Reserved[2];
 } VMXMSRS;
 AssertCompileSizeAlignment(VMXMSRS, 8);
+AssertCompileSize(VMXMSRS, 168);
 /** Pointer to a VMXMSRS struct. */
 typedef VMXMSRS *PVMXMSRS;
+/** Pointer to a const VMXMSRS struct. */
+typedef const VMXMSRS *PCVMXMSRS;
+
 
 /** @name VMX Basic Exit Reasons.
@@ -1098,65 +1105,139 @@
  * @{
  */
+/** VMCS (and related regions) memory type - Uncacheable. */
+#define VMX_BASIC_MEM_TYPE_UC                                    0
+/** VMCS (and related regions) memory type - Write back. */
+#define VMX_BASIC_MEM_TYPE_WB                                    6
+/** Bit fields for MSR_IA32_VMX_BASIC.  */
 /** VMCS revision identifier used by the processor. */
-#define MSR_IA32_VMX_BASIC_VMCS_ID(a)                           ((a) & 0x7fffffff)
-/** Shift to get the VMCS size. */
-#define MSR_IA32_VMX_BASIC_VMCS_SIZE_SHIFT                      32
+#define VMX_BF_BASIC_VMCS_ID_SHIFT                              0
+#define VMX_BF_BASIC_VMCS_ID_MASK                               UINT64_C(0x000000007fffffff)
+/** Bit 32 is reserved as RAZ. */
+#define VMX_BF_BASIC_RSVD_32_SHIFT                              31
+#define VMX_BF_BASIC_RSVD_32_MASK                               UINT64_C(0x0000000080000000)
 /** VMCS size in bytes. */
-#define MSR_IA32_VMX_BASIC_VMCS_SIZE(a)                         (((a) >> 32) & 0x1fff)
-/** Shift to get the width of physical addresses and associated memory regions. */
-#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT                48
-/** Width of physical addresses used for the VMCS and associated memory regions. */
-#define MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(a)                   (((a) >> 48) & 1)
-/** Shift to get the dual-monitor treatment of SMI and SMM. */
-#define MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT                       49
+#define VMX_BF_BASIC_VMCS_SIZE_SHIFT                            32
+#define VMX_BF_BASIC_VMCS_SIZE_MASK                             UINT64_C(0x00001fff00000000)
+/** Bits 45:47 are reserved. */
+#define VMX_BF_BASIC_RSVD_45_47_SHIFT                           45
+#define VMX_BF_BASIC_RSVD_45_47_MASK                            UINT64_C(0x0000e00000000000)
+/** Width of physical addresses used for the VMCS and associated memory regions
+ *  (always 0 on CPUs that support Intel 64 architecture). */
+#define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT                       48
+#define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK                        UINT64_C(0x0001000000000000)
 /** Dual-monitor treatment of SMI and SMM supported. */
-#define MSR_IA32_VMX_BASIC_DUAL_MON(a)                          (((a) >> 49) & 1)
-/** Shift to get the memory type that must be used for the VMCS and associated
- *  memory regions. */
-#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT                  50
+#define VMX_BF_BASIC_DUAL_MON_SHIFT                             49
+#define VMX_BF_BASIC_DUAL_MON_MASK                              UINT64_C(0x0002000000000000)
 /** Memory type that must be used for the VMCS and associated memory regions. */
-#define MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(a)                     (((a) >> 50) & 0xf)
-/** Shift to get the additional VM-exit information for INS/OUTS. */
-#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT                  54
-/** Additional VM-exit information for INS/OUTS. */
-#define MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(a)                     (((a) >> 54) & 1)
-/** Shift to get the VMCS true controls. */
-#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT                  55
-/** Whether default 1 bits in control MSRs (pin/proc/exit/entry) may be
- *  cleared to 0 and that 'true' control MSRs are supported. */
-#define MSR_IA32_VMX_BASIC_TRUE_CONTROLS(a)                     (((a) >> 55) & 1)
-/** @} */
-
-
-/** @name VMX MSR - Misc VMX info.
- * @{
- */
-/** Relationship between the preemption timer and tsc; count down every time bit
- *  x of the tsc changes. */
-#define MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(a)                    ((a) & 0x1f)
+#define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT                        50
+#define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK                         UINT64_C(0x003c000000000000)
+/** VM-exit instruction information for INS/OUTS. */
+#define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT                        54
+#define VMX_BF_BASIC_VMCS_INS_OUTS_MASK                         UINT64_C(0x0040000000000000)
+/** Whether 'true' VMX controls MSRs are supported for handling of default1 class
+ *  bits in VMX control MSRs. */
+#define VMX_BF_BASIC_TRUE_CTLS_SHIFT                            55
+#define VMX_BF_BASIC_TRUE_CTLS_MASK                             UINT64_C(0x0080000000000000)
+/** Bits 56:63 are reserved and RAZ. */
+#define VMX_BF_BASIC_RSVD_56_63_SHIFT                           56
+#define VMX_BF_BASIC_RSVD_56_63_MASK                            UINT64_C(0xff00000000000000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
+                            (VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
+                             VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
+/** @} */
+
+
+/** @name VMX MSR - Miscellaneous data.
+ * Bit fields for MSR_IA32_VMX_MISC.
+ * @{
+ */
 /** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
-#define MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(a)               (((a) >> 5) & 1)
+#define VMX_MISC_EXIT_STORE_EFER_LMA                            RT_BIT(5)
+/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
+ * VMWRITE cannot modify read-only VM-exit information fields. */
+#define VMX_MISC_VMWRITE_ALL                                    RT_BIT(29)
+/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
+ *  instructions. */
+#define VMX_MISC_ENTRY_INJECT_SOFT_INT                          RT_BIT(30)
+/** Maximum number of MSRs in the VMCS, (n+1)*512. */
+#define VMX_MISC_MAX_MSRS(a_MiscMsr)                            (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
+/** Relationship between the preemption timer and tsc. */
+#define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT                     0
+#define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK                      UINT64_C(0x000000000000001f)
+/** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
+#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT                   5
+#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK                    UINT64_C(0x0000000000000020)
 /** Activity states supported by the implementation. */
-#define MSR_IA32_VMX_MISC_ACTIVITY_STATES(a)                    (((a) >> 6) & 0x7)
+#define VMX_BF_MISC_ACTIVITY_STATES_SHIFT                       6
+#define VMX_BF_MISC_ACTIVITY_STATES_MASK                        UINT64_C(0x00000000000001c0)
+/** Bits 9:13 is reserved, RAZ. */
+#define VMX_BF_MISC_RSVD_9_13_SHIFT                             9
+#define VMX_BF_MISC_RSVD_9_13_MASK                              UINT64_C(0x0000000000003e00)
+/** Whether Intel PT (Processor Trace) can be used in VMX operation.  */
+#define VMX_BF_MISC_PT_SHIFT                                    14
+#define VMX_BF_MISC_PT_MASK                                     UINT64_C(0x0000000000004000)
+/** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
+#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT                   15
+#define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK                    UINT64_C(0x0000000000008000)
 /** Number of CR3 target values supported by the processor. (0-256) */
-#define MSR_IA32_VMX_MISC_CR3_TARGET(a)                         (((a) >> 16) & 0x1ff)
-/** Maximum number of MSRs in the VMCS. (N+1)*512. */
-#define MSR_IA32_VMX_MISC_MAX_MSR(a)                            (((((a) >> 25) & 0x7) + 1) * 512)
-/** Whether RDMSR can be used to read IA32_SMBASE_MSR in SMM. */
-#define MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(a)               (((a) >> 15) & 1)
-/** Whether bit 2 of IA32_SMM_MONITOR_CTL can be set to 1. */
-#define MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(a)                 (((a) >> 28) & 1)
-/** Whether VMWRITE can be used to write VM-exit information fields. */
-#define MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(a)                (((a) >> 29) & 1)
-/** MSEG revision identifier used by the processor. */
-#define MSR_IA32_VMX_MISC_MSEG_ID(a)                            ((a) >> 32)
-/** @} */
-
-
-/** @name VMX MSR - VMCS enumeration field info
- * @{
- */
-/** Highest field index. */
-#define MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(a)                 (((a) >> 1) & 0x1ff)
+#define VMX_BF_MISC_CR3_TARGET_SHIFT                            16
+#define VMX_BF_MISC_CR3_TARGET_MASK                             UINT64_C(0x0000000001ff0000)
+/** Maximum number of MSRs in the VMCS. */
+#define VMX_BF_MISC_MAX_MSRS_SHIFT                              25
+#define VMX_BF_MISC_MAX_MSRS_MASK                               UINT64_C(0x000000000e000000)
+/** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
+ *  SMIs. */
+#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT                      28
+#define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK                       UINT64_C(0x0000000010000000)
+/** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
+ * VMWRITE cannot modify read-only VM-exit information fields. */
+#define VMX_BF_MISC_VMWRITE_ALL_SHIFT                           29
+#define VMX_BF_MISC_VMWRITE_ALL_MASK                            UINT64_C(0x0000000020000000)
+/** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
+ *  instructions. */
+#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT                 30
+#define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK                  UINT64_C(0x0000000040000000)
+/** Bit 31 is reserved, RAZ. */
+#define VMX_BF_MISC_RSVD_31_SHIFT                               31
+#define VMX_BF_MISC_RSVD_31_MASK                                UINT64_C(0x0000000080000000)
+/** 32-bit MSEG revision ID used by the processor. */
+#define VMX_BF_MISC_MSEG_ID_SHIFT                               32
+#define VMX_BF_MISC_MSEG_ID_MASK                                UINT64_C(0xffffffff00000000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
+                            (PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
+                             CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
+/** @} */
+
+
+/** @name VMX MSR - VMCS enumeration.
+ * Bit fields for MSR_IA32_VMX_VMCS_ENUM.
+ * @{
+ */
+/** Bit 0 is reserved, RAZ.  */
+#define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT                           0
+#define VMX_BF_VMCS_ENUM_RSVD_0_MASK                            UINT64_C(0x0000000000000001)
+/** Highest index value used in VMCS field encoding. */
+#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT                      1
+#define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK                       UINT64_C(0x00000000000003fe)
+/** Bit 10:63 is reserved, RAZ.  */
+#define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT                       10
+#define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK                        UINT64_C(0xfffffffffffffc00)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
+                            (RSVD_0, HIGHEST_IDX, RSVD_10_63));
+/** @} */
+
+
+/** @name VMX MSR - VM Functions.
+ * Bit fields for MSR_IA32_VMX_VMFUNC.
+ * @{
+ */
+/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
+#define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT                      0
+#define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK                       UINT64_C(0x0000000000000001)
+/** Bits 1:63 are reserved, RAZ. */
+#define VMX_BF_VMFUNC_RSVD_1_63_SHIFT                           1
+#define VMX_BF_VMFUNC_RSVD_1_63_MASK                            UINT64_C(0xfffffffffffffffe)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
+                            (EPTP_SWITCHING, RSVD_1_63));
 /** @} */
 
@@ -1203,17 +1284,17 @@
  * @{
  */
-#define VMX_VMCS16_VPID                                         0x000
-#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR                     0x002
-#define VMX_VMCS16_EPTP_INDEX                                   0x004
-#define VMX_VMCS16_GUEST_ES_SEL                                 0x800
-#define VMX_VMCS16_GUEST_CS_SEL                                 0x802
-#define VMX_VMCS16_GUEST_SS_SEL                                 0x804
-#define VMX_VMCS16_GUEST_DS_SEL                                 0x806
-#define VMX_VMCS16_GUEST_FS_SEL                                 0x808
-#define VMX_VMCS16_GUEST_GS_SEL                                 0x80a
-#define VMX_VMCS16_GUEST_LDTR_SEL                               0x80c
-#define VMX_VMCS16_GUEST_TR_SEL                                 0x80e
-#define VMX_VMCS16_GUEST_INTR_STATUS                            0x810
-#define VMX_VMCS16_GUEST_PML_INDEX                              0x812
+#define VMX_VMCS16_VPID                                         0x0000
+#define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR                     0x0002
+#define VMX_VMCS16_EPTP_INDEX                                   0x0004
+#define VMX_VMCS16_GUEST_ES_SEL                                 0x0800
+#define VMX_VMCS16_GUEST_CS_SEL                                 0x0802
+#define VMX_VMCS16_GUEST_SS_SEL                                 0x0804
+#define VMX_VMCS16_GUEST_DS_SEL                                 0x0806
+#define VMX_VMCS16_GUEST_FS_SEL                                 0x0808
+#define VMX_VMCS16_GUEST_GS_SEL                                 0x080a
+#define VMX_VMCS16_GUEST_LDTR_SEL                               0x080c
+#define VMX_VMCS16_GUEST_TR_SEL                                 0x080e
+#define VMX_VMCS16_GUEST_INTR_STATUS                            0x0810
+#define VMX_VMCS16_GUEST_PML_INDEX                              0x0812
 /** @} */
 
@@ -1222,11 +1303,11 @@
  * @{
  */
-#define VMX_VMCS16_HOST_ES_SEL                                  0xc00
-#define VMX_VMCS16_HOST_CS_SEL                                  0xc02
-#define VMX_VMCS16_HOST_SS_SEL                                  0xc04
-#define VMX_VMCS16_HOST_DS_SEL                                  0xc06
-#define VMX_VMCS16_HOST_FS_SEL                                  0xc08
-#define VMX_VMCS16_HOST_GS_SEL                                  0xc0a
-#define VMX_VMCS16_HOST_TR_SEL                                  0xc0c
+#define VMX_VMCS16_HOST_ES_SEL                                  0x0c00
+#define VMX_VMCS16_HOST_CS_SEL                                  0x0c02
+#define VMX_VMCS16_HOST_SS_SEL                                  0x0c04
+#define VMX_VMCS16_HOST_DS_SEL                                  0x0c06
+#define VMX_VMCS16_HOST_FS_SEL                                  0x0c08
+#define VMX_VMCS16_HOST_GS_SEL                                  0x0c0a
+#define VMX_VMCS16_HOST_TR_SEL                                  0x0c0c
 /** @} */
 
@@ -1251,6 +1332,6 @@
 #define VMX_VMCS64_CTRL_TSC_OFFSET_FULL                         0x2010
 #define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH                         0x2011
-#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL                     0x2012
-#define VMX_VMCS64_CTRL_VAPIC_PAGEADDR_HIGH                     0x2013
+#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL                 0x2012
+#define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH                 0x2013
 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL                    0x2014
 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH                    0x2015
@@ -1299,12 +1380,12 @@
 #define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL                     0x2800
 #define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH                     0x2801
-#define VMX_VMCS64_GUEST_DEBUGCTL_FULL                          0x2802      /**< MSR IA32_DEBUGCTL */
-#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH                          0x2803      /**< MSR IA32_DEBUGCTL */
+#define VMX_VMCS64_GUEST_DEBUGCTL_FULL                          0x2802
+#define VMX_VMCS64_GUEST_DEBUGCTL_HIGH                          0x2803
 #define VMX_VMCS64_GUEST_PAT_FULL                               0x2804
 #define VMX_VMCS64_GUEST_PAT_HIGH                               0x2805
 #define VMX_VMCS64_GUEST_EFER_FULL                              0x2806
 #define VMX_VMCS64_GUEST_EFER_HIGH                              0x2807
-#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL                  0x2808      /**< MSR IA32_PERF_GLOBAL_CTRL */
-#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH                  0x2809      /**< MSR IA32_PERF_GLOBAL_CTRL */
+#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL                  0x2808
+#define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH                  0x2809
 #define VMX_VMCS64_GUEST_PDPTE0_FULL                            0x280a
 #define VMX_VMCS64_GUEST_PDPTE0_HIGH                            0x280b
@@ -1327,6 +1408,6 @@
 #define VMX_VMCS64_HOST_EFER_FULL                               0x2c02
 #define VMX_VMCS64_HOST_EFER_HIGH                               0x2c03
-#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL                   0x2c04      /**< MSR IA32_PERF_GLOBAL_CTRL */
-#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH                   0x2c05      /**< MSR IA32_PERF_GLOBAL_CTRL */
+#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL                   0x2c04
+#define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH                   0x2c05
 /** @} */
 
@@ -1394,5 +1475,5 @@
 #define VMX_VMCS32_GUEST_ACTIVITY_STATE                         0x4826
 #define VMX_VMCS32_GUEST_SMBASE                                 0x4828
-#define VMX_VMCS32_GUEST_SYSENTER_CS                            0x482a  /**< MSR IA32_SYSENTER_CS */
+#define VMX_VMCS32_GUEST_SYSENTER_CS                            0x482a
 #define VMX_VMCS32_PREEMPT_TIMER_VALUE                          0x482e
 /** @} */
@@ -1418,4 +1499,5 @@
 #define VMX_VMCS_CTRL_CR3_TARGET_VAL31                          0x600e
 /** @} */
+
 
 /** @name Natural width read-only data fields.
@@ -1452,6 +1534,6 @@
 #define VMX_VMCS_GUEST_RFLAGS                                   0x6820
 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS                      0x6822
-#define VMX_VMCS_GUEST_SYSENTER_ESP                             0x6824  /**< MSR IA32_SYSENTER_ESP */
-#define VMX_VMCS_GUEST_SYSENTER_EIP                             0x6826  /**< MSR IA32_SYSENTER_EIP */
+#define VMX_VMCS_GUEST_SYSENTER_ESP                             0x6824
+#define VMX_VMCS_GUEST_SYSENTER_EIP                             0x6826
 /** @} */
 
@@ -1480,15 +1562,36 @@
 /** External interrupts cause VM-exits if set; otherwise dispatched through the
  *  guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT                     RT_BIT(0)
+#define VMX_PIN_CTLS_EXT_INT_EXIT                               RT_BIT(0)
 /** Non-maskable interrupts cause VM-exits if set; otherwise dispatched through
  *  the guest's IDT. */
-#define VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT                         RT_BIT(3)
+#define VMX_PIN_CTLS_NMI_EXIT                                   RT_BIT(3)
 /** Virtual NMIs. */
-#define VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI                      RT_BIT(5)
+#define VMX_PIN_CTLS_VIRT_NMI                                   RT_BIT(5)
 /** Activate VMX preemption timer. */
-#define VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER                    RT_BIT(6)
+#define VMX_PIN_CTLS_PREEMPT_TIMER                              RT_BIT(6)
 /** Process interrupts with the posted-interrupt notification vector. */
-#define VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR                      RT_BIT(7)
-/* All other bits are reserved and must be set according to MSR IA32_VMX_PROCBASED_CTLS. */
+#define VMX_PIN_CTLS_POSTED_INT                                 RT_BIT(7)
+/** Default1 class when true capability MSRs are not supported. */
+#define VMX_PIN_CTLS_DEFAULT1                                   UINT32_C(0x00000016)
+/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
+ *  controls field in the VMCS. */
+#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT                      0
+#define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK                       UINT32_C(0x00000001)
+#define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT                         1
+#define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK                          UINT32_C(0x00000006)
+#define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT                          3
+#define VMX_BF_PIN_CTLS_NMI_EXIT_MASK                           UINT32_C(0x00000008)
+#define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT                           4
+#define VMX_BF_PIN_CTLS_UNDEF_4_MASK                            UINT32_C(0x00000010)
+#define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT                          5
+#define VMX_BF_PIN_CTLS_VIRT_NMI_MASK                           UINT32_C(0x00000020)
+#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT                     6
+#define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK                      UINT32_C(0x00000040)
+#define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT                        7
+#define VMX_BF_PIN_CTLS_POSTED_INT_MASK                         UINT32_C(0x00000080)
+#define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT                        8
+#define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK                         UINT32_C(0xffffff00)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
+                            (EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
 /** @} */
 
@@ -1498,47 +1601,111 @@
  */
 /** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
-#define VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT                 RT_BIT(2)
+#define VMX_PROC_CTLS_INT_WINDOW_EXIT                           RT_BIT(2)
 /** Use timestamp counter offset. */
-#define VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING              RT_BIT(3)
+#define VMX_PROC_CTLS_USE_TSC_OFFSETTING                        RT_BIT(3)
 /** VM-exit when executing the HLT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT                        RT_BIT(7)
+#define VMX_PROC_CTLS_HLT_EXIT                                  RT_BIT(7)
 /** VM-exit when executing the INVLPG instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT                     RT_BIT(9)
+#define VMX_PROC_CTLS_INVLPG_EXIT                               RT_BIT(9)
 /** VM-exit when executing the MWAIT instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT                      RT_BIT(10)
+#define VMX_PROC_CTLS_MWAIT_EXIT                                RT_BIT(10)
 /** VM-exit when executing the RDPMC instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT                      RT_BIT(11)
+#define VMX_PROC_CTLS_RDPMC_EXIT                                RT_BIT(11)
 /** VM-exit when executing the RDTSC/RDTSCP instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT                      RT_BIT(12)
+#define VMX_PROC_CTLS_RDTSC_EXIT                                RT_BIT(12)
 /** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT                   RT_BIT(15)
+#define VMX_PROC_CTLS_CR3_LOAD_EXIT                             RT_BIT(15)
 /** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT                  RT_BIT(16)
+#define VMX_PROC_CTLS_CR3_STORE_EXIT                            RT_BIT(16)
 /** VM-exit on CR8 loads. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT                   RT_BIT(19)
+#define VMX_PROC_CTLS_CR8_LOAD_EXIT                             RT_BIT(19)
 /** VM-exit on CR8 stores. */
-#define VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT                  RT_BIT(20)
+#define VMX_PROC_CTLS_CR8_STORE_EXIT                            RT_BIT(20)
 /** Use TPR shadow. */
-#define VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW                  RT_BIT(21)
+#define VMX_PROC_CTLS_USE_TPR_SHADOW                            RT_BIT(21)
 /** VM-exit when virtual NMI blocking is disabled. */
-#define VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT                 RT_BIT(22)
+#define VMX_PROC_CTLS_NMI_WINDOW_EXIT                           RT_BIT(22)
 /** VM-exit when executing a MOV DRx instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT                     RT_BIT(23)
+#define VMX_PROC_CTLS_MOV_DR_EXIT                               RT_BIT(23)
 /** VM-exit when executing IO instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT                  RT_BIT(24)
+#define VMX_PROC_CTLS_UNCOND_IO_EXIT                            RT_BIT(24)
 /** Use IO bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS                  RT_BIT(25)
+#define VMX_PROC_CTLS_USE_IO_BITMAPS                            RT_BIT(25)
 /** Monitor trap flag. */
-#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG               RT_BIT(27)
+#define VMX_PROC_CTLS_MONITOR_TRAP_FLAG                         RT_BIT(27)
 /** Use MSR bitmaps. */
-#define VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS                 RT_BIT(28)
+#define VMX_PROC_CTLS_USE_MSR_BITMAPS                           RT_BIT(28)
 /** VM-exit when executing the MONITOR instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT                    RT_BIT(29)
+#define VMX_PROC_CTLS_MONITOR_EXIT                              RT_BIT(29)
 /** VM-exit when executing the PAUSE instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT                      RT_BIT(30)
+#define VMX_PROC_CTLS_PAUSE_EXIT                                RT_BIT(30)
 /** Whether the secondary processor based VM-execution controls are used. */
-#define VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL         RT_BIT(31)
+#define VMX_PROC_CTLS_USE_SECONDARY_CTLS                        RT_BIT(31)
+/** Default1 class when true-capability MSRs are not supported. */
+#define VMX_PROC_CTLS_DEFAULT1                                  UINT32_C(0x0401e172)
+/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
+ *  controls field in the VMCS. */
+#define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT                        0
+#define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK                         UINT32_C(0x00000003)
+#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT                  2
+#define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK                   UINT32_C(0x00000004)
+#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT               3
+#define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK                UINT32_C(0x00000008)
+#define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT                        4
+#define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK                         UINT32_C(0x00000070)
+#define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT                         7
+#define VMX_BF_PROC_CTLS_HLT_EXIT_MASK                          UINT32_C(0x00000080)
+#define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT                          8
+#define VMX_BF_PROC_CTLS_UNDEF_8_MASK                           UINT32_C(0x00000100)
+#define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT                      9
+#define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK                       UINT32_C(0x00000200)
+#define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT                       10
+#define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK                        UINT32_C(0x00000400)
+#define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT                       11
+#define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK                        UINT32_C(0x00000800)
+#define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT                       12
+#define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK                        UINT32_C(0x00001000)
+#define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT                      13
+#define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK                       UINT32_C(0x00006000)
+#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT                    15
+#define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK                     UINT32_C(0x00008000)
+#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT                   16
+#define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK                    UINT32_C(0x00010000)
+#define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT                      17
+#define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK                       UINT32_C(0x00060000)
+#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT                    19
+#define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK                     UINT32_C(0x00080000)
+#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT                   20
+#define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK                    UINT32_C(0x00100000)
+#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT                   21
+#define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK                    UINT32_C(0x00200000)
+#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT                  22
+#define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK                   UINT32_C(0x00400000)
+#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT                      23
+#define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK                       UINT32_C(0x00800000)
+#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT                   24
+#define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK                    UINT32_C(0x01000000)
+#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT                   25
+#define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK                    UINT32_C(0x02000000)
+#define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT                         26
+#define VMX_BF_PROC_CTLS_UNDEF_26_MASK                          UINT32_C(0x4000000)
+#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT                27
+#define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK                 UINT32_C(0x08000000)
+#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT                  28
+#define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK                   UINT32_C(0x10000000)
+#define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT                     29
+#define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK                      UINT32_C(0x20000000)
+#define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT                       30
+#define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK                        UINT32_C(0x40000000)
+#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT               31
+#define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK                UINT32_C(0x80000000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
+                            (UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
+                             MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
+                             CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
+                             USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
+                             USE_SECONDARY_CTLS));
 /** @} */
 
@@ -1548,47 +1715,102 @@
  */
 /** Virtualize APIC access. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC                      RT_BIT(0)
+#define VMX_PROC_CTLS2_VIRT_APIC_ACCESS                         RT_BIT(0)
 /** EPT supported/enabled. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_EPT                            RT_BIT(1)
+#define VMX_PROC_CTLS2_EPT                                      RT_BIT(1)
 /** Descriptor table instructions cause VM-exits. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT          RT_BIT(2)
+#define VMX_PROC_CTLS2_DESC_TABLE_EXIT                          RT_BIT(2)
 /** RDTSCP supported/enabled. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP                         RT_BIT(3)
+#define VMX_PROC_CTLS2_RDTSCP                                   RT_BIT(3)
 /** Virtualize x2APIC mode. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC                    RT_BIT(4)
+#define VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS                       RT_BIT(4)
 /** VPID supported/enabled. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VPID                           RT_BIT(5)
+#define VMX_PROC_CTLS2_VPID                                     RT_BIT(5)
 /** VM-exit when executing the WBINVD instruction. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT                    RT_BIT(6)
+#define VMX_PROC_CTLS2_WBINVD_EXIT                              RT_BIT(6)
 /** Unrestricted guest execution. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST             RT_BIT(7)
+#define VMX_PROC_CTLS2_UNRESTRICTED_GUEST                       RT_BIT(7)
 /** APIC register virtualization. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT                  RT_BIT(8)
+#define VMX_PROC_CTLS2_APIC_REG_VIRT                            RT_BIT(8)
 /** Virtual-interrupt delivery. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY             RT_BIT(9)
+#define VMX_PROC_CTLS2_VIRT_INT_DELIVERY                        RT_BIT(9)
 /** A specified number of pause loops cause a VM-exit. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT                RT_BIT(10)
+#define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT                          RT_BIT(10)
 /** VM-exit when executing RDRAND instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT                    RT_BIT(11)
+#define VMX_PROC_CTLS2_RDRAND_EXIT                              RT_BIT(11)
 /** Enables INVPCID instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_INVPCID                        RT_BIT(12)
+#define VMX_PROC_CTLS2_INVPCID                                  RT_BIT(12)
 /** Enables VMFUNC instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC                         RT_BIT(13)
+#define VMX_PROC_CTLS2_VMFUNC                                   RT_BIT(13)
 /** Enables VMCS shadowing. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING                 RT_BIT(14)
+#define VMX_PROC_CTLS2_VMCS_SHADOWING                           RT_BIT(14)
 /** Enables ENCLS VM-exits. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT                     RT_BIT(15)
+#define VMX_PROC_CTLS2_ENCLS_EXIT                               RT_BIT(15)
 /** VM-exit when executing RDSEED. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT                    RT_BIT(16)
+#define VMX_PROC_CTLS2_RDSEED_EXIT                              RT_BIT(16)
 /** Enables page-modification logging. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_PML                            RT_BIT(17)
+#define VMX_PROC_CTLS2_PML                                      RT_BIT(17)
 /** Controls whether EPT-violations may cause \#VE instead of exits. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE                         RT_BIT(18)
+#define VMX_PROC_CTLS2_EPT_VE                                   RT_BIT(18)
 /** Conceal VMX non-root operation from Intel processor trace (PT). */
-#define VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT                RT_BIT(19)
+#define VMX_PROC_CTLS2_CONCEAL_FROM_PT                          RT_BIT(19)
 /** Enables XSAVES/XRSTORS instructions. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS                 RT_BIT(20)
+#define VMX_PROC_CTLS2_XSAVES_XRSTORS                           RT_BIT(20)
 /** Use TSC scaling. */
-#define VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING                    RT_BIT(25)
+#define VMX_PROC_CTLS2_TSC_SCALING                              RT_BIT(25)
+/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
+ *  VM-execution controls field in the VMCS. */
+#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT                0
+#define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK                 UINT32_C(0x00000001)
+#define VMX_BF_PROC_CTLS2_EPT_SHIFT                             1
+#define VMX_BF_PROC_CTLS2_EPT_MASK                              UINT32_C(0x00000002)
+#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT                 2
+#define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK                  UINT32_C(0x00000004)
+#define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT                          3
+#define VMX_BF_PROC_CTLS2_RDTSCP_MASK                           UINT32_C(0x00000008)
+#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT              4
+#define VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_MASK               UINT32_C(0x00000010)
+#define VMX_BF_PROC_CTLS2_VPID_SHIFT                            5
+#define VMX_BF_PROC_CTLS2_VPID_MASK                             UINT32_C(0x00000020)
+#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT                     6
+#define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK                      UINT32_C(0x00000040)
+#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT              7
+#define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK               UINT32_C(0x00000080)
+#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT                   8
+#define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK                    UINT32_C(0x00000100)
+#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT               9
+#define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK                UINT32_C(0x00000200)
+#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT                 10
+#define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK                  UINT32_C(0x00000400)
+#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT                     11
+#define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK                      UINT32_C(0x00000800)
+#define VMX_BF_PROC_CTLS2_INVPCID_SHIFT                         12
+#define VMX_BF_PROC_CTLS2_INVPCID_MASK                          UINT32_C(0x00001000)
+#define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT                          13
+#define VMX_BF_PROC_CTLS2_VMFUNC_MASK                           UINT32_C(0x00002000)
+#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT                  14
+#define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK                   UINT32_C(0x00004000)
+#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT                      15
+#define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK                       UINT32_C(0x00008000)
+#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT                     16
+#define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK                      UINT32_C(0x00010000)
+#define VMX_BF_PROC_CTLS2_PML_SHIFT                             17
+#define VMX_BF_PROC_CTLS2_PML_MASK                              UINT32_C(0x00020000)
+#define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT                          18
+#define VMX_BF_PROC_CTLS2_EPT_VE_MASK                           UINT32_C(0x00040000)
+#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT                 19
+#define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK                  UINT32_C(0x00080000)
+#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT                  20
+#define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK                   UINT32_C(0x00100000)
+#define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT                     21
+#define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK                      UINT32_C(0x01e00000)
+#define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT                     25
+#define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK                      UINT32_C(0x02000000)
+#define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT                     26
+#define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK                      UINT32_C(0xfc000000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
+                            (VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_ACCESS, VPID, WBINVD_EXIT,
+                             UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
+                             VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
+                             TSC_SCALING, UNDEF_26_31));
 /** @} */
 
@@ -1599,17 +1821,46 @@
 /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG                          RT_BIT(2)
-/** 64 bits guest mode. Must be 0 for CPUs that don't support AMD64. */
-#define VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST                    RT_BIT(9)
+#define VMX_ENTRY_CTLS_LOAD_DEBUG                               RT_BIT(2)
+/** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
+#define VMX_ENTRY_CTLS_IA32E_MODE_GUEST                         RT_BIT(9)
 /** In SMM mode after VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_ENTRY_SMM                           RT_BIT(10)
+#define VMX_ENTRY_CTLS_ENTRY_TO_SMM                             RT_BIT(10)
 /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
-#define VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON                  RT_BIT(11)
+#define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON                      RT_BIT(11)
 /** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR                 RT_BIT(13)
+#define VMX_ENTRY_CTLS_LOAD_PERF_MSR                            RT_BIT(13)
 /** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR                  RT_BIT(14)
+#define VMX_ENTRY_CTLS_LOAD_PAT_MSR                             RT_BIT(14)
 /** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
-#define VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR                 RT_BIT(15)
+#define VMX_ENTRY_CTLS_LOAD_EFER_MSR                            RT_BIT(15)
+/** Default1 class when true-capability MSRs are not supported. */
+#define VMX_ENTRY_CTLS_DEFAULT1                                 UINT32_C(0x000011ff)
+/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
+ *  VMCS. */
+#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT                       0
+#define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK                        UINT32_C(0x00000003)
+#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT                      2
+#define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK                       UINT32_C(0x00000004)
+#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT                       3
+#define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK                        UINT32_C(0x000001f8)
+#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT                9
+#define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK                 UINT32_C(0x00000200)
+#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT                       10
+#define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK                        UINT32_C(0x00000400)
+#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT             11
+#define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK              UINT32_C(0x00000800)
+#define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT                        12
+#define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK                         UINT32_C(0x00001000)
+#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT                   13
+#define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK                    UINT32_C(0x00002000)
+#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT                    14
+#define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK                     UINT32_C(0x00004000)
+#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT                   15
+#define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK                    UINT32_C(0x00008000)
+#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_SHIFT                     16
+#define VMX_BF_ENTRY_CTLS_UNDEF_16_31_MASK                      UINT32_C(0xffff0000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
+                            (UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
+                             LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, UNDEF_16_31));
 /** @} */
 
@@ -1620,29 +1871,59 @@
 /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
-#define VMX_VMCS_CTRL_EXIT_SAVE_DEBUG                           RT_BIT(2)
+#define VMX_EXIT_CTLS_SAVE_DEBUG                                RT_BIT(2)
 /** Return to long mode after a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE                 RT_BIT(9)
-/** Whether the IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR                        RT_BIT(12)
+#define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE                      RT_BIT(9)
+/** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
+#define VMX_EXIT_CTLS_LOAD_PERF_MSR                             RT_BIT(12)
 /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_ACK_EXT_INT                          RT_BIT(15)
+#define VMX_EXIT_CTLS_ACK_EXT_INT                               RT_BIT(15)
 /** Whether the guest IA32_PAT MSR is saved on VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR                   RT_BIT(18)
+#define VMX_EXIT_CTLS_SAVE_PAT_MSR                              RT_BIT(18)
 /** Whether the host IA32_PAT MSR is loaded on VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR                    RT_BIT(19)
+#define VMX_EXIT_CTLS_LOAD_PAT_MSR                              RT_BIT(19)
 /** Whether the guest IA32_EFER MSR is saved on VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR                  RT_BIT(20)
+#define VMX_EXIT_CTLS_SAVE_EFER_MSR                             RT_BIT(20)
 /** Whether the host IA32_EFER MSR is loaded on VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR                   RT_BIT(21)
+#define VMX_EXIT_CTLS_LOAD_EFER_MSR                             RT_BIT(21)
 /** Whether the value of the VMX preemption timer is saved on every VM-exit. */
-#define VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER               RT_BIT(22)
-/** @} */
-
-
-/** @name VM function controls.
- * @{
- */
-/** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
-#define VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING                     RT_BIT_64(0)
+#define VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER                    RT_BIT(22)
+/** Default1 class when true-capability MSRs are not supported.  */
+#define VMX_EXIT_CTLS_DEFAULT1                                  UINT32_C(0x00036dff)
+/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
+ *  VMCS. */
+#define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT                        0
+#define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK                         UINT32_C(0x00000003)
+#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT                       2
+#define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK                        UINT32_C(0x00000004)
+#define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT                        3
+#define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK                         UINT32_C(0x000001f8)
+#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT             9
+#define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK              UINT32_C(0x00000200)
+#define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT                      10
+#define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK                       UINT32_C(0x00000c00)
+#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT                    12
+#define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK                     UINT32_C(0x00001000)
+#define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT                      13
+#define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK                       UINT32_C(0x00006000)
+#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT                      15
+#define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK                       UINT32_C(0x00008000)
+#define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT                      16
+#define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK                       UINT32_C(0x00030000)
+#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT                     18
+#define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK                      UINT32_C(0x00040000)
+#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT                     19
+#define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK                      UINT32_C(0x00080000)
+#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT                    20
+#define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK                     UINT32_C(0x00100000)
+#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT                    21
+#define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK                     UINT32_C(0x00200000)
+#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT               22
+#define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK                UINT32_C(0x00400000)
+#define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT                      23
+#define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK                       UINT32_C(0xff800000)
+RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
+                            (UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
+                             ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
+                             SAVE_PREEMPT_TIMER, UNDEF_23_31));
 /** @} */
 
@@ -2037,4 +2318,10 @@
 
 
+/** @defgroup grp_hm_vmx_emu    VMX emulation.
+ * @{
+ */
+/** @todo declare these with a prefix that immediately identifies that they are
+ *        emulated by VirtualBox and not defined by Intel, see @bugref{9180#c6}.
+ */
 /** VMCS revision identifier used for emulating VMX (bit 31 MBZ). Bump this
  *  arbitarily chosen identifier if incompatible changes to the layout of our VMCS
@@ -2042,8 +2329,6 @@
 #define VMX_VMCS_REVISION_ID                                    UINT32_C(0x1d000001)
 AssertCompile(!(VMX_VMCS_REVISION_ID & RT_BIT(31)));
-/** VMCS (and related regions) memory type - Uncacheable. */
-#define VMX_VMCS_MEM_TYPE_UC                                    0
-/** VMCS (and related regions) memory type - Write back. */
-#define VMX_VMCS_MEM_TYPE_WB                                    6
+
+/** @} */
 
 
Index: /trunk/include/iprt/x86.h
===================================================================
--- /trunk/include/iprt/x86.h	(revision 73388)
+++ /trunk/include/iprt/x86.h	(revision 73389)
@@ -1402,7 +1402,7 @@
 /** Allowed settings for proc-based VM execution controls. */
 #define MSR_IA32_VMX_PROCBASED_CTLS         0x482
-/** Allowed settings for the VMX exit controls. */
+/** Allowed settings for the VM-exit controls. */
 #define MSR_IA32_VMX_EXIT_CTLS              0x483
-/** Allowed settings for the VMX entry controls. */
+/** Allowed settings for the VM-entry controls. */
 #define MSR_IA32_VMX_ENTRY_CTLS             0x484
 /** Misc VMX info. */
Index: /trunk/src/VBox/HostDrivers/Support/SUPDrv.cpp
===================================================================
--- /trunk/src/VBox/HostDrivers/Support/SUPDrv.cpp	(revision 73388)
+++ /trunk/src/VBox/HostDrivers/Support/SUPDrv.cpp	(revision 73389)
@@ -4331,10 +4331,10 @@
 
                     vtCaps.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS);
-                    if (vtCaps.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+                    if (vtCaps.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
                     {
                         vtCaps.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
-                        if (vtCaps.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
+                        if (vtCaps.n.allowed1 & VMX_PROC_CTLS2_EPT)
                             *pfCaps |= SUPVTCAPS_NESTED_PAGING;
-                        if (vtCaps.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
+                        if (vtCaps.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
                             *pfCaps |= SUPVTCAPS_VTX_UNRESTRICTED_GUEST;
                     }
Index: /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp	(revision 73389)
@@ -1292,18 +1292,12 @@
 {
     RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    if (pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmx)
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
     {
-        uint64_t const fVmcsRevisionId  = VMX_VMCS_REVISION_ID;
-        uint64_t const f32BitAddrLimit  = 0;
-        uint64_t const fDualMonSmiSmm   = 0;
-        uint64_t const fVmcsMemType     = VMX_VMCS_MEM_TYPE_WB;
-        uint64_t const fVmcsInsOutsInfo = pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures.fVmxInsOutInfo;
-        uint64_t const fTrueCapMsrs     = 0;
-        *puValue = fVmcsRevisionId
-                 | (f32BitAddrLimit  << MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH_SHIFT)
-                 | (fDualMonSmiSmm   << MSR_IA32_VMX_BASIC_DUAL_MON_SHIFT)
-                 | (fVmcsMemType     << MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE_SHIFT)
-                 | (fVmcsInsOutsInfo << MSR_IA32_VMX_BASIC_VMCS_INS_OUTS_SHIFT)
-                 | (fTrueCapMsrs     << MSR_IA32_VMX_BASIC_TRUE_CONTROLS_SHIFT);
+        *puValue = RT_BF_MAKE(VMX_BF_BASIC_VMCS_ID,       VMX_VMCS_REVISION_ID          )
+                 | RT_BF_MAKE(VMX_BF_BASIC_DUAL_MON,      0                             )
+                 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_MEM_TYPE, VMX_BASIC_MEM_TYPE_WB         )
+                 | RT_BF_MAKE(VMX_BF_BASIC_VMCS_INS_OUTS, pGuestFeatures->fVmxInsOutInfo)
+                 | RT_BF_MAKE(VMX_BF_BASIC_TRUE_CTLS,     0                             );
     }
     else
@@ -1316,6 +1310,20 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxPinbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        uint32_t const fFeatures = (pGuestFeatures->fVmxExtIntExit   << VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT )
+                                 | (pGuestFeatures->fVmxNmiExit      << VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT     )
+                                 | (pGuestFeatures->fVmxVirtNmi      << VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT     )
+                                 | (pGuestFeatures->fVmxPreemptTimer << VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT);
+        uint32_t const fVal      = VMX_PIN_CTLS_DEFAULT1;
+        uint32_t const fZap      = fFeatures | VMX_PIN_CTLS_DEFAULT1;
+        AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
+                        VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
+        *puValue = RT_MAKE_U64(fVal, fZap);
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
@@ -1325,6 +1333,37 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcbasedCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        uint32_t const fFeatures = (pGuestFeatures->fVmxIntWindowExit     << VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT   )
+                                 | (pGuestFeatures->fVmxTscOffsetting     << VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT)
+                                 | (pGuestFeatures->fVmxHltExit           << VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT          )
+                                 | (pGuestFeatures->fVmxInvlpgExit        << VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT       )
+                                 | (pGuestFeatures->fVmxMwaitExit         << VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT        )
+                                 | (pGuestFeatures->fVmxRdpmcExit         << VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT        )
+                                 | (pGuestFeatures->fVmxRdtscExit         << VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT        )
+                                 | (pGuestFeatures->fVmxCr3LoadExit       << VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT     )
+                                 | (pGuestFeatures->fVmxCr3StoreExit      << VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT    )
+                                 | (pGuestFeatures->fVmxCr8LoadExit       << VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT     )
+                                 | (pGuestFeatures->fVmxCr8StoreExit      << VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT    )
+                                 | (pGuestFeatures->fVmxTprShadow         << VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT    )
+                                 | (pGuestFeatures->fVmxNmiWindowExit     << VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT   )
+                                 | (pGuestFeatures->fVmxMovDRxExit        << VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT       )
+                                 | (pGuestFeatures->fVmxUncondIoExit      << VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT    )
+                                 | (pGuestFeatures->fVmxUseIoBitmaps      << VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT    )
+                                 | (pGuestFeatures->fVmxMonitorTrapFlag   << VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT )
+                                 | (pGuestFeatures->fVmxUseMsrBitmaps     << VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT   )
+                                 | (pGuestFeatures->fVmxMonitorExit       << VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT      )
+                                 | (pGuestFeatures->fVmxPauseExit         << VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT        )
+                                 | (pGuestFeatures->fVmxSecondaryExecCtls << VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT);
+        uint32_t const fVal      = VMX_PROC_CTLS_DEFAULT1;
+        uint32_t const fZap      = fFeatures | VMX_PROC_CTLS_DEFAULT1;
+        AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
+                        VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
+        *puValue = RT_MAKE_U64(fVal, fZap);
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
@@ -1334,6 +1373,22 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxExitCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        uint32_t const fFeatures = (pGuestFeatures->fVmxExitSaveDebugCtls << VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT          )
+                                 | (pGuestFeatures->fVmxHostAddrSpaceSize << VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT)
+                                 | (pGuestFeatures->fVmxExitAckExtInt     << VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT         )
+                                 | (pGuestFeatures->fVmxExitSaveEferMsr   << VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT       )
+                                 | (pGuestFeatures->fVmxExitLoadEferMsr   << VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT       )
+                                 | (pGuestFeatures->fVmxSavePreemptTimer  << VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT  );
+        uint32_t const fVal      = VMX_EXIT_CTLS_DEFAULT1;
+        uint32_t const fZap      = fFeatures | VMX_EXIT_CTLS_DEFAULT1;
+        AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
+                        VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
+        *puValue = RT_MAKE_U64(fVal, fZap);
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
@@ -1343,6 +1398,20 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxEntryCtls(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        uint32_t const fFeatures = (pGuestFeatures->fVmxEntryLoadDebugCtls << VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT      )
+                                 | (pGuestFeatures->fVmxIa32eModeGuest     << VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT)
+                                 | (pGuestFeatures->fVmxEntryLoadEferMsr   << VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT   );
+        uint32_t const fDefault1 = VMX_ENTRY_CTLS_DEFAULT1;
+        uint32_t const fVal      = fDefault1;
+        uint32_t const fZap      = fFeatures | fDefault1;
+        AssertMsgReturn((fVal & fZap) == fVal, ("fVal=%#RX32 fZap=%#RX32 fFeatures=%#RX32\n", fVal, fZap, fFeatures),
+                        VERR_CPUM_INVALID_HWVIRT_FEAT_COMBO);
+        *puValue = RT_MAKE_U64(fVal, fZap);
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
@@ -1352,6 +1421,13 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxMisc(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        /** @todo Think about this especially preemption timer TSC shifts.  */
+        *puValue = 0;
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
@@ -1406,6 +1482,24 @@
 static DECLCALLBACK(VBOXSTRICTRC) cpumMsrRd_Ia32VmxProcBasedCtls2(PVMCPU pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue)
 {
-    RT_NOREF_PV(pVCpu); RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
-    *puValue = 0;
+    RT_NOREF_PV(idMsr); RT_NOREF_PV(pRange);
+    PCCPUMFEATURES pGuestFeatures = &pVCpu->CTX_SUFF(pVM)->cpum.s.GuestFeatures;
+    if (pGuestFeatures->fVmx)
+    {
+        uint32_t const fFeatures = (pGuestFeatures->fVmxVirtApicAccess    << VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT  )
+                                 | (pGuestFeatures->fVmxEpt               << VMX_BF_PROC_CTLS2_EPT_SHIFT               )
+                                 | (pGuestFeatures->fVmxDescTableExit     << VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT   )
+                                 | (pGuestFeatures->fVmxRdtscp            << VMX_BF_PROC_CTLS2_RDTSCP_SHIFT            )
+                                 | (pGuestFeatures->fVmxVirtX2ApicAccess  << VMX_BF_PROC_CTLS2_VIRT_X2APIC_ACCESS_SHIFT)
+                                 | (pGuestFeatures->fVmxVpid              << VMX_BF_PROC_CTLS2_VPID_SHIFT              )
+                                 | (pGuestFeatures->fVmxWbinvdExit        << VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT       )
+                                 | (pGuestFeatures->fVmxUnrestrictedGuest << VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT)
+                                 | (pGuestFeatures->fVmxPauseLoopExit     << VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT   )
+                                 | (pGuestFeatures->fVmxInvpcid           << VMX_BF_PROC_CTLS2_INVPCID_SHIFT           );
+        uint32_t const fVal      = 0;
+        uint32_t const fZap      = fFeatures;
+        *puValue = RT_MAKE_U64(fVal, fZap);
+    }
+    else
+        *puValue = 0;
     return VINF_SUCCESS;
 }
Index: /trunk/src/VBox/VMM/VMMAll/HMAll.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/HMAll.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMAll/HMAll.cpp	(revision 73389)
@@ -349,5 +349,5 @@
 
 /**
- * Checks if MSR bitmaps are available. It is assumed that when it's available
+ * Checks if MSR bitmaps are active. It is assumed that when it's available
  * it will be used as well.
  *
@@ -355,5 +355,5 @@
  * @param   pVM         The cross context VM structure.
  */
-VMM_INT_DECL(bool) HMAreMsrBitmapsAvailable(PVM pVM)
+VMM_INT_DECL(bool) HMIsMsrBitmapActive(PVM pVM)
 {
     if (HMIsEnabled(pVM))
@@ -363,8 +363,6 @@
 
         if (   pVM->hm.s.vmx.fSupported
-            && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
-        {
+            && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS))
             return true;
-        }
     }
     return false;
@@ -389,5 +387,5 @@
  * Checks if VT-x is active.
  *
- * @returns true if AMD-V is active.
+ * @returns true if VT-x is active.
  * @param   pVM         The cross context VM structure.
  *
@@ -396,5 +394,19 @@
 VMM_INT_DECL(bool) HMIsVmxActive(PVM pVM)
 {
-    return pVM->hm.s.vmx.fSupported && HMIsEnabled(pVM);
+    return HMIsVmxSupported(pVM) && HMIsEnabled(pVM);
+}
+
+
+/**
+ * Checks if VT-x is supported by the host CPU.
+ *
+ * @returns true if VT-x is supported, false otherwise.
+ * @param   pVM         The cross context VM structure.
+ *
+ * @remarks Works before hmR3InitFinalizeR0.
+ */
+VMM_INT_DECL(bool) HMIsVmxSupported(PVM pVM)
+{
+    return pVM->hm.s.vmx.fSupported;
 }
 
@@ -544,4 +556,84 @@
 
 
+/**
+ * Gets a copy of the VMX host MSRs that were read by HM during ring-0
+ * initialization.
+ *
+ * @return VBox status code.
+ * @param   pVM        The cross context VM structure.
+ * @param   pVmxMsrs   Where to store the VMXMSRS struct (only valid when
+ *                     VINF_SUCCESS is returned).
+ *
+ * @remarks Caller needs to take care not to call this function too early. Call
+ *          after HM initialization is fully complete.
+ */
+VMM_INT_DECL(int) HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs)
+{
+    AssertPtrReturn(pVM,      VERR_INVALID_PARAMETER);
+    AssertPtrReturn(pVmxMsrs, VERR_INVALID_PARAMETER);
+    if (pVM->hm.s.vmx.fSupported)
+    {
+        *pVmxMsrs = pVM->hm.s.vmx.Msrs;
+        return VINF_SUCCESS;
+    }
+    return VERR_VMX_NOT_SUPPORTED;
+}
+
+
+#if 0 /** @todo Update comment hm_vmx.h VMXMSRS struct if this is removed. */
+/**
+ * Gets the specified VMX host MSR that was read by HM during ring-0
+ * initialization.
+ *
+ * @return VBox status code.
+ * @param   pVM        The cross context VM structure.
+ * @param   idMsr      The MSR.
+ * @param   puValue    Where to store the MSR value (only updated when VINF_SUCCESS
+ *                     is returned).
+ *
+ * @remarks Caller needs to take care not to call this function too early. Call
+ *          after HM initialization is fully complete.
+ */
+VMM_INT_DECL(int) HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue)
+{
+    AssertPtrReturn(pVM,     VERR_INVALID_PARAMETER);
+    AssertPtrReturn(puValue, VERR_INVALID_PARAMETER);
+
+    if (!pVM->hm.s.vmx.fSupported)
+        return VERR_VMX_NOT_SUPPORTED;
+
+    PCVMXMSRS pVmxMsrs = &pVM->hm.s.vmx.Msrs;
+    switch (idMsr)
+    {
+        case MSR_IA32_FEATURE_CONTROL:         *puValue =  pVmxMsrs->u64FeatCtrl;      break;
+        case MSR_IA32_VMX_BASIC:               *puValue =  pVmxMsrs->u64Basic;         break;
+        case MSR_IA32_VMX_PINBASED_CTLS:       *puValue =  pVmxMsrs->PinCtls.u;        break;
+        case MSR_IA32_VMX_PROCBASED_CTLS:      *puValue =  pVmxMsrs->ProcCtls.u;       break;
+        case MSR_IA32_VMX_PROCBASED_CTLS2:     *puValue =  pVmxMsrs->ProcCtls2.u;      break;
+        case MSR_IA32_VMX_EXIT_CTLS:           *puValue =  pVmxMsrs->ExitCtls.u;       break;
+        case MSR_IA32_VMX_ENTRY_CTLS:          *puValue =  pVmxMsrs->EntryCtls.u;      break;
+        case MSR_IA32_VMX_TRUE_PINBASED_CTLS:  *puValue =  pVmxMsrs->TruePinCtls.u;    break;
+        case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: *puValue =  pVmxMsrs->TrueProcCtls.u;   break;
+        case MSR_IA32_VMX_TRUE_ENTRY_CTLS:     *puValue =  pVmxMsrs->TrueEntryCtls.u;  break;
+        case MSR_IA32_VMX_TRUE_EXIT_CTLS:      *puValue =  pVmxMsrs->TrueExitCtls.u;   break;
+        case MSR_IA32_VMX_MISC:                *puValue =  pVmxMsrs->u64Misc;          break;
+        case MSR_IA32_VMX_CR0_FIXED0:          *puValue =  pVmxMsrs->u64Cr0Fixed0;     break;
+        case MSR_IA32_VMX_CR0_FIXED1:          *puValue =  pVmxMsrs->u64Cr0Fixed1;     break;
+        case MSR_IA32_VMX_CR4_FIXED0:          *puValue =  pVmxMsrs->u64Cr4Fixed0;     break;
+        case MSR_IA32_VMX_CR4_FIXED1:          *puValue =  pVmxMsrs->u64Cr4Fixed1;     break;
+        case MSR_IA32_VMX_VMCS_ENUM:           *puValue =  pVmxMsrs->u64VmcsEnum;      break;
+        case MSR_IA32_VMX_VMFUNC:              *puValue =  pVmxMsrs->u64VmFunc;        break;
+        case MSR_IA32_VMX_EPT_VPID_CAP:        *puValue =  pVmxMsrs->u64EptVpidCaps;   break;
+        default:
+        {
+            AssertMsgFailed(("Invalid MSR %#x\n", idMsr));
+            return VERR_NOT_FOUND;
+        }
+    }
+    return VINF_SUCCESS;
+}
+#endif
+
+
 #ifndef IN_RC
 /**
Index: /trunk/src/VBox/VMM/VMMR0/HMR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR0/HMR0.cpp	(revision 73389)
@@ -122,5 +122,5 @@
         uint64_t                    u64HostSmmMonitorCtl;
 
-        /** VMX MSR values */
+        /** VMX MSR values. */
         VMXMSRS                     Msrs;
 
@@ -298,5 +298,4 @@
  *      - AAN92  - B1.
  *      - AAJ124 - C0, D0.
- *
  *      - AAP86  - B1.
  *
@@ -387,5 +386,5 @@
              * depends on bit 49 of MSR_IA32_VMX_BASIC while table 35-2 says that this MSR is
              * available if either VMX or SMX is supported. */
-            if (MSR_IA32_VMX_BASIC_DUAL_MON(g_HmR0.vmx.Msrs.u64Basic))
+            if (RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_DUAL_MON))
                 g_HmR0.vmx.u64HostSmmMonitorCtl = ASMRdMsr(MSR_IA32_SMM_MONITOR_CTL);
             g_HmR0.vmx.Msrs.PinCtls.u       = ASMRdMsr(MSR_IA32_VMX_PINBASED_CTLS);
@@ -399,5 +398,5 @@
             g_HmR0.vmx.Msrs.u64Cr4Fixed1    = ASMRdMsr(MSR_IA32_VMX_CR4_FIXED1);
             g_HmR0.vmx.Msrs.u64VmcsEnum     = ASMRdMsr(MSR_IA32_VMX_VMCS_ENUM);
-            if (MSR_IA32_VMX_BASIC_TRUE_CONTROLS(g_HmR0.vmx.Msrs.u64Basic))
+            if (RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
             {
                 g_HmR0.vmx.Msrs.TruePinCtls.u   = ASMRdMsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS);
@@ -410,12 +409,12 @@
             g_HmR0.uMaxAsid = 0x10000; /* exclusive */
 
-            if (g_HmR0.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+            if (g_HmR0.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
             {
                 g_HmR0.vmx.Msrs.ProcCtls2.u = ASMRdMsr(MSR_IA32_VMX_PROCBASED_CTLS2);
-                if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & (VMX_VMCS_CTRL_PROC_EXEC2_EPT | VMX_VMCS_CTRL_PROC_EXEC2_VPID))
+                if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & (VMX_PROC_CTLS2_EPT | VMX_PROC_CTLS2_VPID))
                     g_HmR0.vmx.Msrs.u64EptVpidCaps = ASMRdMsr(MSR_IA32_VMX_EPT_VPID_CAP);
 
-                if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC)
-                    g_HmR0.vmx.Msrs.u64Vmfunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
+                if (g_HmR0.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VMFUNC)
+                    g_HmR0.vmx.Msrs.u64VmFunc = ASMRdMsr(MSR_IA32_VMX_VMFUNC);
             }
 
@@ -438,5 +437,5 @@
 
                 /* Set revision dword at the beginning of the structure. */
-                *(uint32_t *)pvScatchPage = MSR_IA32_VMX_BASIC_VMCS_ID(g_HmR0.vmx.Msrs.u64Basic);
+                *(uint32_t *)pvScatchPage = RT_BF_GET(g_HmR0.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
 
                 /* Make sure we don't get rescheduled to another cpu during this probe. */
@@ -515,8 +514,8 @@
                  * Timer Does Not Count Down at the Rate Specified" erratum.
                  */
-                if (g_HmR0.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER)
+                if (g_HmR0.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER)
                 {
                     g_HmR0.vmx.fUsePreemptTimer   = true;
-                    g_HmR0.vmx.cPreemptTimerShift = MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(g_HmR0.vmx.Msrs.u64Misc);
+                    g_HmR0.vmx.cPreemptTimerShift = RT_BF_GET(g_HmR0.vmx.Msrs.u64Misc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
                     if (hmR0InitIntelIsSubjectToVmxPreemptionTimerErratum())
                         g_HmR0.vmx.cPreemptTimerShift = 0; /* This is about right most of the time here. */
Index: /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp	(revision 73389)
@@ -790,5 +790,5 @@
     {
         /* Write the VMCS revision dword to the VMXON region. */
-        *(uint32_t *)pvCpuPage = MSR_IA32_VMX_BASIC_VMCS_ID(pVM->hm.s.vmx.Msrs.u64Basic);
+        *(uint32_t *)pvCpuPage = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
     }
 
@@ -916,5 +916,5 @@
         hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjGuestMsr, &pVCpu->hm.s.vmx.pvGuestMsr, &pVCpu->hm.s.vmx.HCPhysGuestMsr);
 
-        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
             hmR0VmxPageFree(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap, &pVCpu->hm.s.vmx.HCPhysMsrBitmap);
 
@@ -968,5 +968,5 @@
 
     /* The VMCS size cannot be more than 4096 bytes. See Intel spec. Appendix A.1 "Basic VMX Information". */
-    AssertReturnStmt(MSR_IA32_VMX_BASIC_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64Basic) <= PAGE_SIZE,
+    AssertReturnStmt(RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_SIZE) <= PAGE_SIZE,
                      (&pVM->aCpus[0])->hm.s.u32HMError = VMX_UFC_INVALID_VMCS_SIZE,
                      VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
@@ -985,5 +985,5 @@
 
     /* Allocate the APIC-access page for trapping APIC accesses from the guest. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
+    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     {
         rc = hmR0VmxPageAllocZ(&pVM->hm.s.vmx.hMemObjApicAccess, (PRTR0PTR)&pVM->hm.s.vmx.pbApicAccess,
@@ -1008,5 +1008,5 @@
         /* Get the allocated virtual-APIC page from the APIC device for transparent TPR accesses. */
         if (   PDMHasApic(pVM)
-            && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW))
+            && (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
         {
             rc = APICGetApicPageForCpu(pVCpu, &pVCpu->hm.s.vmx.HCPhysVirtApic, (PRTR0PTR)&pVCpu->hm.s.vmx.pbVirtApic,
@@ -1023,5 +1023,5 @@
          * update HMAreMsrBitmapsAvailable().
          */
-        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
         {
             rc = hmR0VmxPageAllocZ(&pVCpu->hm.s.vmx.hMemObjMsrBitmap, &pVCpu->hm.s.vmx.pvMsrBitmap,
@@ -1251,5 +1251,6 @@
 {
     /* Shouldn't ever happen but there -is- a number. We're well within the recommended 512. */
-    uint32_t const cMaxSupportedMsrs = MSR_IA32_VMX_MISC_MAX_MSR(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc);
+    uint64_t const uVmxMiscMsr       = pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.u64Misc;
+    uint32_t const cMaxSupportedMsrs = VMX_MISC_MAX_MSRS(uVmxMiscMsr);
     if (RT_UNLIKELY(cMsrs > cMaxSupportedMsrs))
     {
@@ -1309,5 +1310,5 @@
 
         /* Now that we're swapping MSRs during the world-switch, allow the guest to read/write them without causing VM-exits. */
-        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
             hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_PASSTHRU_READ, VMXMSREXIT_PASSTHRU_WRITE);
 
@@ -1393,5 +1394,5 @@
 
         /* We're no longer swapping MSRs during the world-switch, intercept guest read/writes to them. */
-        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
             hmR0VmxSetMsrPermission(pVCpu, uMsr, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
 
@@ -1652,5 +1653,5 @@
                         VERR_VMX_VMCS_FIELD_CACHE_INVALID);
 
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
     {
         rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);
@@ -1692,5 +1693,5 @@
     Assert(!RTThreadPreemptIsEnabled(NIL_RTTHREAD));
 
-    if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
+    if (pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR)
     {
         uint64_t u64Val;
@@ -1738,5 +1739,5 @@
 
         /* Verify that the permissions are as expected in the MSR bitmap. */
-        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
         {
             VMXMSREXITREAD  enmRead;
@@ -2295,15 +2296,15 @@
     uint32_t const fZap = pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1;      /* Bits cleared here must always be cleared. */
 
-    fVal |= VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT              /* External interrupts cause a VM-exit. */
-          | VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT;                 /* Non-maskable interrupts (NMIs) cause a VM-exit. */
-
-    if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
-        fVal |= VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI;         /* Use virtual NMIs and virtual-NMI blocking features. */
+    fVal |= VMX_PIN_CTLS_EXT_INT_EXIT                        /* External interrupts cause a VM-exit. */
+          | VMX_PIN_CTLS_NMI_EXIT;                           /* Non-maskable interrupts (NMIs) cause a VM-exit. */
+
+    if (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
+        fVal |= VMX_PIN_CTLS_VIRT_NMI;                        /* Use virtual NMIs and virtual-NMI blocking features. */
 
     /* Enable the VMX preemption timer. */
     if (pVM->hm.s.vmx.fUsePreemptTimer)
     {
-        Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
-        fVal |= VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER;
+        Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
+        fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
     }
 
@@ -2312,7 +2313,7 @@
     if (pVM->hm.s.fPostedIntrs)
     {
-        Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
-        Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
-        fVal |= VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR;
+        Assert(pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT);
+        Assert(pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
+        fVal |= VMX_PIN_CTL_POSTED_INT;
     }
 #endif
@@ -2351,10 +2352,10 @@
 
     /* WBINVD causes a VM-exit. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT;
+    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
+        fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
 
     /* Enable EPT (aka nested-paging). */
     if (pVM->hm.s.fNestedPaging)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_EPT;
+        fVal |= VMX_PROC_CTLS2_EPT;
 
     /*
@@ -2362,15 +2363,15 @@
      * it to the guest. Without this, guest executing INVPCID would cause a #UD.
      */
-    if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_INVPCID)
+    if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID)
         && pVM->cpum.ro.GuestFeatures.fInvpcid)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_INVPCID;
+        fVal |= VMX_PROC_CTLS2_INVPCID;
 
     /* Enable VPID. */
     if (pVM->hm.s.vmx.fVpid)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_VPID;
+        fVal |= VMX_PROC_CTLS2_VPID;
 
     /* Enable Unrestricted guest execution. */
     if (pVM->hm.s.vmx.fUnrestrictedGuest)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST;
+        fVal |= VMX_PROC_CTLS2_UNRESTRICTED_GUEST;
 
 #if 0
@@ -2378,21 +2379,21 @@
     {
         /* Enable APIC-register virtualization. */
-        Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT;
+        Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
+        fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
 
         /* Enable virtual-interrupt delivery. */
-        Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY;
+        Assert(pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
+        fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
     }
 #endif
 
-    /* Enable Virtual-APIC page accesses if supported by the CPU. This is where the TPR shadow resides. */
+    /* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is where the TPR shadow resides. */
     /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
      *        done dynamically. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
+    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
     {
         Assert(pVM->hm.s.vmx.HCPhysApicAccess);
         Assert(!(pVM->hm.s.vmx.HCPhysApicAccess & 0xfff));    /* Bits 11:0 MBZ. */
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC;           /* Virtualize APIC accesses. */
+        fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS;              /* Virtualize APIC accesses. */
         int rc = VMXWriteVmcs64(VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL, pVM->hm.s.vmx.HCPhysApicAccess);
         AssertRCReturn(rc, rc);
@@ -2400,13 +2401,13 @@
 
     /* Enable RDTSCP. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP;
+    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP)
+        fVal |= VMX_PROC_CTLS2_RDTSCP;
 
     /* Enable Pause-Loop exiting. */
-    if (   pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT
+    if (   pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT
         && pVM->hm.s.vmx.cPleGapTicks
         && pVM->hm.s.vmx.cPleWindowTicks)
     {
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT;
+        fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
 
         int rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks);
@@ -2447,17 +2448,17 @@
     uint32_t const fZap = pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;     /* Bits cleared here must be cleared in the VMCS. */
 
-    fVal |= VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT                      /* HLT causes a VM-exit. */
-          | VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING            /* Use TSC-offsetting. */
-          | VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT                   /* MOV DRx causes a VM-exit. */
-          | VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT                /* All IO instructions cause a VM-exit. */
-          | VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT                    /* RDPMC causes a VM-exit. */
-          | VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT                  /* MONITOR causes a VM-exit. */
-          | VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT;                   /* MWAIT causes a VM-exit. */
-
-    /* We toggle VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
-    if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT)
-        ||  (pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0 & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT))
-    {
-        LogRelFunc(("Unsupported VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT combo!"));
+    fVal |= VMX_PROC_CTLS_HLT_EXIT                                    /* HLT causes a VM-exit. */
+          | VMX_PROC_CTLS_USE_TSC_OFFSETTING                          /* Use TSC-offsetting. */
+          | VMX_PROC_CTLS_MOV_DR_EXIT                                 /* MOV DRx causes a VM-exit. */
+          | VMX_PROC_CTLS_UNCOND_IO_EXIT                              /* All IO instructions cause a VM-exit. */
+          | VMX_PROC_CTLS_RDPMC_EXIT                                  /* RDPMC causes a VM-exit. */
+          | VMX_PROC_CTLS_MONITOR_EXIT                                /* MONITOR causes a VM-exit. */
+          | VMX_PROC_CTLS_MWAIT_EXIT;                                 /* MWAIT causes a VM-exit. */
+
+    /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
+    if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
+        ||  (pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
+    {
+        LogRelFunc(("Unsupported VMX_PROC_CTLS_MOV_DR_EXIT combo!"));
         pVCpu->hm.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
         return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
@@ -2468,23 +2469,23 @@
     {
         Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);                /* Paranoia. */
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT
-              | VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
-              | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
+        fVal |= VMX_PROC_CTLS_INVLPG_EXIT
+              | VMX_PROC_CTLS_CR3_LOAD_EXIT
+              | VMX_PROC_CTLS_CR3_STORE_EXIT;
     }
 
     /* Use TPR shadowing if supported by the CPU. */
     if (   PDMHasApic(pVM)
-        && pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+        && pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW)
     {
         Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
         Assert(!(pVCpu->hm.s.vmx.HCPhysVirtApic & 0xfff));        /* Bits 11:0 MBZ. */
         int rc  = VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, 0);
-        rc     |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
+        rc     |= VMXWriteVmcs64(VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL, pVCpu->hm.s.vmx.HCPhysVirtApic);
         AssertRCReturn(rc, rc);
 
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW;           /* CR8 reads from the Virtual-APIC page. */
+        fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW;                     /* CR8 reads from the Virtual-APIC page. */
                                                                   /* CR8 writes cause a VM-exit based on TPR threshold. */
-        Assert(!(fVal & VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT));
-        Assert(!(fVal & VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT));
+        Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
+        Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
     }
     else
@@ -2496,13 +2497,13 @@
         if (pVM->hm.s.fAllow64BitGuests)
         {
-            fVal |= VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT        /* CR8 reads cause a VM-exit. */
-                  | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT;        /* CR8 writes cause a VM-exit. */
+            fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT                  /* CR8 reads cause a VM-exit. */
+                  | VMX_PROC_CTLS_CR8_LOAD_EXIT;                  /* CR8 writes cause a VM-exit. */
         }
     }
 
     /* Use MSR-bitmaps if supported by the CPU. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
-    {
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS;
+    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
+    {
+        fVal |= VMX_PROC_CTLS_USE_MSR_BITMAPS;
 
         Assert(pVCpu->hm.s.vmx.HCPhysMsrBitmap);
@@ -2543,6 +2544,6 @@
 
     /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
-        fVal |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
+    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
+        fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
 
     if ((fVal & fZap) != fVal)
@@ -2560,5 +2561,5 @@
 
     /* Set up secondary processor-based VM-execution controls if the CPU supports it. */
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
         return hmR0VmxSetupProcCtls2(pVCpu);
 
@@ -2762,7 +2763,7 @@
     Assert(!pVM->hm.s.vmx.fSupportsVmcsEfer);
 #if HC_ARCH_BITS == 64
-    if (   (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
-        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR)
-        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR))
+    if (   (pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
+        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_LOAD_EFER_MSR)
+        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1  & VMX_EXIT_CTLS_SAVE_EFER_MSR))
     {
         pVM->hm.s.vmx.fSupportsVmcsEfer = true;
@@ -2785,5 +2786,5 @@
 
         /* Set revision dword at the beginning of the VMCS structure. */
-        *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = MSR_IA32_VMX_BASIC_VMCS_ID(pVM->hm.s.vmx.Msrs.u64Basic);
+        *(uint32_t *)pVCpu->hm.s.vmx.pvVmcs = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_ID);
 
         /* Initialize our VMCS region in memory, set the VMCS launch state to "clear". */
@@ -2960,5 +2961,5 @@
     /* Assertion is right but we would not have updated u32ExitCtls yet. */
 #if 0
-    if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE))
+    if (!(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE))
         Assert(uSelSS != 0);
 #endif
@@ -3233,14 +3234,14 @@
 
         /* Load debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x capable CPUs only supports the 1-setting of this bit. */
-        fVal |= VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG;
+        fVal |= VMX_ENTRY_CTLS_LOAD_DEBUG;
 
         /* Set if the guest is in long mode. This will set/clear the EFER.LMA bit on VM-entry. */
         if (CPUMIsGuestInLongModeEx(&pVCpu->cpum.GstCtx))
         {
-            fVal |= VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST;
-            Log4Func(("VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST\n"));
+            fVal |= VMX_ENTRY_CTLS_IA32E_MODE_GUEST;
+            Log4Func(("VMX_ENTRY_CTLS_IA32E_MODE_GUEST\n"));
         }
         else
-            Assert(!(fVal & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST));
+            Assert(!(fVal & VMX_ENTRY_CTLS_IA32E_MODE_GUEST));
 
         /* If the CPU supports the newer VMCS controls for managing guest/host EFER, use it. */
@@ -3248,16 +3249,16 @@
             && hmR0VmxShouldSwapEferMsr(pVCpu))
         {
-            fVal |= VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR;
-            Log4Func(("VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR\n"));
+            fVal |= VMX_ENTRY_CTLS_LOAD_EFER_MSR;
+            Log4Func(("VMX_ENTRY_CTLS_LOAD_EFER_MSR\n"));
         }
 
         /*
          * The following should -not- be set (since we're not in SMM mode):
-         * - VMX_VMCS_CTRL_ENTRY_ENTRY_SMM
-         * - VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON
+         * - VMX_ENTRY_CTLS_ENTRY_TO_SMM
+         * - VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON
          */
 
-        /** @todo VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR,
-         *        VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR. */
+        /** @todo VMX_ENTRY_CTLS_LOAD_PERF_MSR,
+         *        VMX_ENTRY_CTLS_LOAD_PAT_MSR. */
 
         if ((fVal & fZap) != fVal)
@@ -3300,5 +3301,5 @@
 
         /* Save debug controls (DR7 & IA32_DEBUGCTL_MSR). The first VT-x CPUs only supported the 1-setting of this bit. */
-        fVal |= VMX_VMCS_CTRL_EXIT_SAVE_DEBUG;
+        fVal |= VMX_EXIT_CTLS_SAVE_DEBUG;
 
         /*
@@ -3308,6 +3309,6 @@
          */
 #if HC_ARCH_BITS == 64
-        fVal |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
-        Log4Func(("VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n"));
+        fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
+        Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
 #else
         Assert(   pVCpu->hm.s.vmx.pfnStartVM == VMXR0SwitcherStartVM64
@@ -3317,9 +3318,9 @@
         {
             /* The switcher returns to long mode, EFER is managed by the switcher. */
-            fVal |= VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE;
-            Log4Func(("VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE\n"));
+            fVal |= VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE;
+            Log4Func(("VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE\n"));
         }
         else
-            Assert(!(fVal & VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE));
+            Assert(!(fVal & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE));
 #endif
 
@@ -3328,20 +3329,20 @@
             && hmR0VmxShouldSwapEferMsr(pVCpu))
         {
-            fVal |= VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR
-                  | VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR;
-            Log4Func(("VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR and VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR\n"));
+            fVal |= VMX_EXIT_CTLS_SAVE_EFER_MSR
+                  | VMX_EXIT_CTLS_LOAD_EFER_MSR;
+            Log4Func(("VMX_EXIT_CTLS_SAVE_EFER_MSR and VMX_EXIT_CTLS_LOAD_EFER_MSR\n"));
         }
 
         /* Don't acknowledge external interrupts on VM-exit. We want to let the host do that. */
-        Assert(!(fVal & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT));
-
-        /** @todo VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR,
-         *        VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR,
-         *        VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR. */
+        Assert(!(fVal & VMX_EXIT_CTLS_ACK_EXT_INT));
+
+        /** @todo VMX_EXIT_CTLS_LOAD_PERF_MSR,
+         *        VMX_EXIT_CTLS_SAVE_PAT_MSR,
+         *        VMX_EXIT_CTLS_LOAD_PAT_MSR. */
 
         /* Enable saving of the VMX preemption timer value on VM-exit. */
         if (    pVM->hm.s.vmx.fUsePreemptTimer
-            && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER))
-            fVal |= VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER;
+            && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER))
+            fVal |= VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER;
 
         if ((fVal & fZap) != fVal)
@@ -3377,5 +3378,5 @@
 {
     Assert(!(u32TprThreshold & 0xfffffff0));         /* Bits 31:4 MBZ. */
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW); RT_NOREF_PV(pVCpu);
     return VMXWriteVmcs32(VMX_VMCS32_CTRL_TPR_THRESHOLD, u32TprThreshold);
 }
@@ -3402,5 +3403,5 @@
              * Setup TPR shadowing.
              */
-            if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+            if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
             {
                 Assert(pVCpu->hm.s.vmx.HCPhysVirtApic);
@@ -3489,5 +3490,5 @@
      */
     if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
-        && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
+        && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
     {
         fIntrState |= VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI;
@@ -3679,17 +3680,17 @@
             {
                 /* The guest has paging enabled, let it access CR3 without causing a VM-exit if supported. */
-                uProcCtls &= ~(  VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
-                               | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
+                uProcCtls &= ~(  VMX_PROC_CTLS_CR3_LOAD_EXIT
+                               | VMX_PROC_CTLS_CR3_STORE_EXIT);
             }
             else
             {
                 /* The guest doesn't have paging enabled, make CR3 access cause a VM-exit to update our shadow. */
-                uProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT
-                           | VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
+                uProcCtls |= VMX_PROC_CTLS_CR3_LOAD_EXIT
+                           | VMX_PROC_CTLS_CR3_STORE_EXIT;
             }
 
             /* If we have unrestricted guest execution, we never have to intercept CR3 reads. */
             if (pVM->hm.s.vmx.fUnrestrictedGuest)
-                uProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT;
+                uProcCtls &= ~VMX_PROC_CTLS_CR3_STORE_EXIT;
         }
         else
@@ -4064,5 +4065,5 @@
 #ifdef VBOX_STRICT
     /* Validate. Intel spec. 26.3.1.1 "Checks on Guest Controls Registers, Debug Registers, MSRs" */
-    if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
+    if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
     {
         /* Validate. Intel spec. 17.2 "Debug Registers", recompiler paranoia checks. */
@@ -4079,7 +4080,7 @@
         /* If the CPU supports the monitor trap flag, use it for single stepping in DBGF and avoid intercepting #DB. */
         PVM pVM = pVCpu->CTX_SUFF(pVM);
-        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG)
-        {
-            uProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
+        if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG)
+        {
+            uProcCtls |= VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
             Assert(fSteppingDB == false);
         }
@@ -4176,7 +4177,7 @@
 
     if (fInterceptMovDRx)
-        uProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
+        uProcCtls |= VMX_PROC_CTLS_MOV_DR_EXIT;
     else
-        uProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
+        uProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
 
     /*
@@ -4790,5 +4791,5 @@
 
                 /* We need to intercept reads too, see @bugref{7386#c16}. */
-                if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+                if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_MSR_BITMAPS)
                     hmR0VmxSetMsrPermission(pVCpu, MSR_K6_EFER, VMXMSREXIT_INTERCEPT_READ, VMXMSREXIT_INTERCEPT_WRITE);
                 Log4Func(("MSR[--]: u32Msr=%#RX32 u64Value=%#RX64 cMsrs=%u\n", MSR_K6_EFER, pCtx->msrEFER,
@@ -5025,5 +5026,5 @@
                 rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, &u32Val);                 AssertRC(rc);
                 Log4(("VMX_VMCS32_CTRL_PROC_EXEC               %#RX32\n", u32Val));
-                if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+                if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
                 {
                     rc = VMXReadVmcs32(VMX_VMCS32_CTRL_PROC_EXEC2, &u32Val);            AssertRC(rc);
@@ -5508,5 +5509,5 @@
         case VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL:
         case VMX_VMCS64_CTRL_TSC_OFFSET_FULL:
-        case VMX_VMCS64_CTRL_VAPIC_PAGEADDR_FULL:
+        case VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL:
         case VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL:
         case VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL:
@@ -5670,7 +5671,7 @@
         }
 
-        if (uProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT)
-        {
-            uProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
+        if (uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT)
+        {
+            uProcCtls &= ~VMX_PROC_CTLS_RDTSC_EXIT;
             int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
             AssertRC(rc);
@@ -5682,7 +5683,7 @@
     {
         /* We can't use TSC-offsetting (non-fixed TSC, warp drive active etc.), VM-exit on RDTSC(P). */
-        if (!(uProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
-        {
-            uProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT;
+        if (!(uProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
+        {
+            uProcCtls |= VMX_PROC_CTLS_RDTSC_EXIT;
             int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, uProcCtls);
             AssertRC(rc);
@@ -5887,5 +5888,5 @@
             && (   enmRaise   == IEMXCPTRAISE_PREV_EVENT
                 || (fRaiseInfo & IEMXCPTRAISEINFO_NMI_PF))
-            && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
+            && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
         {
             VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
@@ -5978,5 +5979,5 @@
              && VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(pVmxTransient->uExitIntInfo)
              && uExitVector != X86_XCPT_DF
-             && (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI))
+             && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
     {
         /*
@@ -6806,5 +6807,5 @@
 #ifdef VBOX_STRICT
     if (CPUMIsHyperDebugStateActive(pVCpu))
-        Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
+        Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
 #endif
     CPUMR0DebugStateMaybeSaveGuestAndRestoreHost(pVCpu, true /* save DR6 */);
@@ -7099,9 +7100,9 @@
 DECLINLINE(void) hmR0VmxSetIntWindowExitVmcs(PVMCPU pVCpu)
 {
-    if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
-    {
-        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT))
-        {
-            pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
+    if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_INT_WINDOW_EXIT))
+    {
+        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT))
+        {
+            pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_INT_WINDOW_EXIT;
             int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
             AssertRC(rc);
@@ -7119,6 +7120,6 @@
 DECLINLINE(void) hmR0VmxClearIntWindowExitVmcs(PVMCPU pVCpu)
 {
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
-    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT;
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
+    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_INT_WINDOW_EXIT;
     int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
     AssertRC(rc);
@@ -7135,9 +7136,9 @@
 DECLINLINE(void) hmR0VmxSetNmiWindowExitVmcs(PVMCPU pVCpu)
 {
-    if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
-    {
-        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT))
-        {
-            pVCpu->hm.s.vmx.u32ProcCtls |= VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
+    if (RT_LIKELY(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
+    {
+        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT))
+        {
+            pVCpu->hm.s.vmx.u32ProcCtls |= VMX_PROC_CTLS_NMI_WINDOW_EXIT;
             int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
             AssertRC(rc);
@@ -7155,6 +7156,6 @@
 DECLINLINE(void) hmR0VmxClearNmiWindowExitVmcs(PVMCPU pVCpu)
 {
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
-    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT;
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
+    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_NMI_WINDOW_EXIT;
     int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
     AssertRC(rc);
@@ -7239,5 +7240,5 @@
             else if (rc == VERR_APIC_INTR_MASKED_BY_TPR)
             {
-                if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+                if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
                     hmR0VmxApicSetTprThreshold(pVCpu, u8Interrupt >> 4);
                 STAM_COUNTER_INC(&pVCpu->hm.s.StatSwitchTprMaskedIrq);
@@ -7370,5 +7371,5 @@
              * BS bit would mean delivering a #DB to the guest upon VM-entry when it shouldn't be.
              */
-            Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG));
+            Assert(!(pVCpu->CTX_SUFF(pVM)->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MONITOR_TRAP_FLAG));
             fIntrState = 0;
         }
@@ -7752,5 +7753,5 @@
 static void hmR0VmxClearIntNmiWindowsVmcs(PVMCPU pVCpu)
 {
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT)
     {
         hmR0VmxClearIntWindowExitVmcs(pVCpu);
@@ -7758,5 +7759,5 @@
     }
 
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)
     {
         hmR0VmxClearNmiWindowExitVmcs(pVCpu);
@@ -8212,5 +8213,5 @@
     PVM pVM = pVCpu->CTX_SUFF(pVM);
     if (   !pVCpu->hm.s.vmx.u64MsrApicBase
-        && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
+        && (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
         && PDMHasApic(pVM))
     {
@@ -8429,5 +8430,5 @@
      * Cache the TPR-shadow for checking on every VM-exit if it might have changed.
      */
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
         pVmxTransient->u8GuestTpr = pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR];
 
@@ -8454,7 +8455,7 @@
      * Load the TSC_AUX MSR when we are not intercepting RDTSCP.
      */
-    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
-    {
-        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
+    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDTSCP)
+    {
+        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
         {
             bool fMsrUpdated;
@@ -8492,5 +8493,5 @@
 #endif
 #ifdef HMVMX_ALWAYS_CHECK_GUEST_STATE
-    if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
+    if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
     {
         uint32_t uInvalidReason = hmR0VmxCheckGuestState(pVCpu);
@@ -8527,5 +8528,5 @@
     pVmxTransient->fVectoringDoublePF  = false;                 /* Vectoring double page-fault needs to be determined later. */
 
-    if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
+    if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_RDTSC_EXIT))
         TMCpuTickSetLastSeen(pVCpu, uHostTsc + pVCpu->hm.s.vmx.u64TscOffset);
 
@@ -8606,5 +8607,5 @@
              * Sync the TPR shadow with our APIC state.
              */
-            if (   (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+            if (   (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
                 && pVmxTransient->u8GuestTpr != pVCpu->hm.s.vmx.pbVirtApic[XAPIC_OFF_TPR])
             {
@@ -8872,6 +8873,6 @@
     if (pDbgState->fModifiedProcCtls)
     {
-        if (!(pDbgState->fProcCtlsInitial & VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
-            pDbgState->fProcCtlsInitial |= VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
+        if (!(pDbgState->fProcCtlsInitial & VMX_PROC_CTLS_MOV_DR_EXIT) && CPUMIsHyperDebugStateActive(pVCpu))
+            pDbgState->fProcCtlsInitial |= VMX_PROC_CTLS_MOV_DR_EXIT; /* Avoid assertion in hmR0VmxLeave */
         int rc2 = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pDbgState->fProcCtlsInitial);
         AssertRCReturn(rc2, rc2);
@@ -9022,13 +9023,13 @@
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_GETSEC,             VMX_EXIT_GETSEC);           /* unconditional */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_GETSEC,             VMX_EXIT_GETSEC);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT,               VMX_EXIT_HLT,      VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT); /* paranoia */
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_HALT,               VMX_EXIT_HLT,      VMX_PROC_CTLS_HLT_EXIT); /* paranoia */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_HALT,               VMX_EXIT_HLT);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_INVD,               VMX_EXIT_INVD);             /* unconditional */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVD,               VMX_EXIT_INVD);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG,             VMX_EXIT_INVLPG,   VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_INVLPG,             VMX_EXIT_INVLPG,   VMX_PROC_CTLS_INVLPG_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_INVLPG,             VMX_EXIT_INVLPG);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC,              VMX_EXIT_RDPMC,    VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDPMC,              VMX_EXIT_RDPMC,    VMX_PROC_CTLS_RDPMC_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDPMC,              VMX_EXIT_RDPMC);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC,              VMX_EXIT_RDTSC,    VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSC,              VMX_EXIT_RDTSC,    VMX_PROC_CTLS_RDTSC_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSC,              VMX_EXIT_RDTSC);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_RSM,                VMX_EXIT_RSM);              /* unconditional */
@@ -9066,8 +9067,8 @@
 #endif
         if (IS_EITHER_ENABLED(pVM, INSTR_CRX_READ))
-            pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT;
+            pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_STORE_EXIT | VMX_PROC_CTLS_CR8_STORE_EXIT;
         if (IS_EITHER_ENABLED(pVM, INSTR_CRX_WRITE))
-            pDbgState->fCpe1Extra |= VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT | VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT;
-        pDbgState->fCpe1Unwanted |= VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW; /* risky? */
+            pDbgState->fCpe1Extra |= VMX_PROC_CTLS_CR3_LOAD_EXIT | VMX_PROC_CTLS_CR8_LOAD_EXIT;
+        pDbgState->fCpe1Unwanted |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* risky? */
         /* Note! We currently don't use VMX_VMCS32_CTRL_CR3_TARGET_COUNT.  It would
                  require clearing here and in the loop if we start using it. */
@@ -9099,16 +9100,16 @@
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_DRX_WRITE,          VMX_EXIT_MOV_DRX);
 
-    SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR,               VMX_EXIT_RDMSR,     VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS); /* risky clearing this? */
-    SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR,               VMX_EXIT_RDMSR);
-    SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR,               VMX_EXIT_WRMSR,     VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
-    SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR,               VMX_EXIT_WRMSR);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT,               VMX_EXIT_MWAIT,     VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);   /* paranoia */
-    SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT,               VMX_EXIT_MWAIT);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR,             VMX_EXIT_MONITOR,   VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT); /* paranoia */
-    SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR,             VMX_EXIT_MONITOR);
+    SET_CPEU_XBM_IF_EITHER_EN(INSTR_RDMSR,              VMX_EXIT_RDMSR,    VMX_PROC_CTLS_USE_MSR_BITMAPS); /* risky clearing this? */
+    SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDMSR,              VMX_EXIT_RDMSR);
+    SET_CPEU_XBM_IF_EITHER_EN(INSTR_WRMSR,              VMX_EXIT_WRMSR,    VMX_PROC_CTLS_USE_MSR_BITMAPS);
+    SET_ONLY_XBM_IF_EITHER_EN( EXIT_WRMSR,              VMX_EXIT_WRMSR);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_MWAIT,              VMX_EXIT_MWAIT,    VMX_PROC_CTLS_MWAIT_EXIT);   /* paranoia */
+    SET_ONLY_XBM_IF_EITHER_EN( EXIT_MWAIT,              VMX_EXIT_MWAIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_MONITOR,            VMX_EXIT_MONITOR,  VMX_PROC_CTLS_MONITOR_EXIT); /* paranoia */
+    SET_ONLY_XBM_IF_EITHER_EN( EXIT_MONITOR,            VMX_EXIT_MONITOR);
 #if 0 /** @todo too slow, fix handler. */
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE,               VMX_EXIT_PAUSE,     VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_PAUSE,              VMX_EXIT_PAUSE,    VMX_PROC_CTLS_PAUSE_EXIT);
 #endif
-    SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE,               VMX_EXIT_PAUSE);
+    SET_ONLY_XBM_IF_EITHER_EN( EXIT_PAUSE,              VMX_EXIT_PAUSE);
 
     if (   IS_EITHER_ENABLED(pVM, INSTR_SGDT)
@@ -9117,5 +9118,5 @@
         || IS_EITHER_ENABLED(pVM, INSTR_LIDT))
     {
-        pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
+        pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
         ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_XDTR_ACCESS);
     }
@@ -9130,5 +9131,5 @@
         || IS_EITHER_ENABLED(pVM, INSTR_LTR))
     {
-        pDbgState->fCpe2Extra |= VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT;
+        pDbgState->fCpe2Extra |= VMX_PROC_CTLS2_DESC_TABLE_EXIT;
         ASMBitSet(pDbgState->bmExitsToCheck, VMX_EXIT_TR_ACCESS);
     }
@@ -9140,19 +9141,19 @@
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVEPT,         VMX_EXIT_INVEPT);           /* unconditional */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVEPT,         VMX_EXIT_INVEPT);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP,             VMX_EXIT_RDTSCP,    VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_RDTSCP,             VMX_EXIT_RDTSCP,   VMX_PROC_CTLS_RDTSC_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDTSCP,             VMX_EXIT_RDTSCP);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_INVVPID,        VMX_EXIT_INVVPID);          /* unconditional */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVVPID,        VMX_EXIT_INVVPID);
-    SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD,             VMX_EXIT_WBINVD,    VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
+    SET_CPE2_XBM_IF_EITHER_EN(INSTR_WBINVD,             VMX_EXIT_WBINVD,   VMX_PROC_CTLS2_WBINVD_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_WBINVD,             VMX_EXIT_WBINVD);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSETBV,             VMX_EXIT_XSETBV);           /* unconditional */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_XSETBV,             VMX_EXIT_XSETBV);
-    SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND,             VMX_EXIT_RDRAND,    VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
+    SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDRAND,             VMX_EXIT_RDRAND,   VMX_PROC_CTLS2_RDRAND_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDRAND,             VMX_EXIT_RDRAND);
-    SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID,        VMX_EXIT_INVPCID,   VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
+    SET_CPE1_XBM_IF_EITHER_EN(INSTR_VMX_INVPCID,        VMX_EXIT_INVPCID,  VMX_PROC_CTLS_INVLPG_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_INVPCID,        VMX_EXIT_INVPCID);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_VMX_VMFUNC,         VMX_EXIT_VMFUNC);           /* unconditional for the current setup */
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_VMX_VMFUNC,         VMX_EXIT_VMFUNC);
-    SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED,             VMX_EXIT_RDSEED,    VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
+    SET_CPE2_XBM_IF_EITHER_EN(INSTR_RDSEED,             VMX_EXIT_RDSEED,   VMX_PROC_CTLS2_RDSEED_EXIT);
     SET_ONLY_XBM_IF_EITHER_EN( EXIT_RDSEED,             VMX_EXIT_RDSEED);
     SET_ONLY_XBM_IF_EITHER_EN(INSTR_XSAVES,             VMX_EXIT_XSAVES);           /* unconditional (enabled by host, guest cfg) */
@@ -9172,8 +9173,8 @@
     pDbgState->fCpe2Extra       &= pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1;
     if (pDbgState->fCpe2Extra)
-        pDbgState->fCpe1Extra   |= VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL;
+        pDbgState->fCpe1Extra   |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
     pDbgState->fCpe1Extra       &= pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1;
     pDbgState->fCpe1Unwanted    &= ~pVM->hm.s.vmx.Msrs.ProcCtls.n.disallowed0;
-    if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT))
+    if (pVCpu->hm.s.fDebugWantRdTscExit != RT_BOOL(pDbgState->fCpe1Extra & VMX_PROC_CTLS_RDTSC_EXIT))
     {
         pVCpu->hm.s.fDebugWantRdTscExit ^= true;
@@ -10306,5 +10307,5 @@
         rc = VMXReadVmcs64(VMX_VMCS64_GUEST_DEBUGCTL_FULL, &u64Val);
         AssertRCBreak(rc);
-        if (   (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
+        if (   (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
             && (u64Val & 0xfffffe3c))                           /* Bits 31:9, bits 5:2 MBZ. */
         {
@@ -10318,5 +10319,5 @@
         Assert(u32Val == pVCpu->hm.s.vmx.u32EntryCtls);
 #endif
-        bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
+        bool const fLongModeGuest = RT_BOOL(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
 
         /*
@@ -10387,5 +10388,5 @@
          *        51:32 beyond the processor's physical-address width are 0. */
 
-        if (   (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG)
+        if (   (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG)
             && (pCtx->dr[7] & X86_DR7_MBZ_MASK))
         {
@@ -10405,5 +10406,5 @@
          * PERF_GLOBAL MSR.
          */
-        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR)
+        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PERF_MSR)
         {
             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL, &u64Val);
@@ -10416,5 +10417,5 @@
          * PAT MSR.
          */
-        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR)
+        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_PAT_MSR)
         {
             rc = VMXReadVmcs64(VMX_VMCS64_GUEST_PAT_FULL, &u64Val);
@@ -10440,5 +10441,5 @@
          * EFER MSR.
          */
-        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR)
+        if (pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
         {
             Assert(pVM->hm.s.vmx.fSupportsVmcsEfer);
@@ -10448,5 +10449,5 @@
                               VMX_IGS_EFER_MSR_RESERVED);               /* Bits 63:12, bit 9, bits 7:1 MBZ. */
             HMVMX_CHECK_BREAK(RT_BOOL(u64Val & MSR_K6_EFER_LMA) == RT_BOOL(  pVCpu->hm.s.vmx.u32EntryCtls
-                                                                           & VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST),
+                                                                           & VMX_ENTRY_CTLS_IA32E_MODE_GUEST),
                               VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH);
             HMVMX_CHECK_BREAK(   fUnrestrictedGuest
@@ -10698,5 +10699,5 @@
         AssertRCBreak(rc);
         HMVMX_CHECK_BREAK(   !u32ActivityState
-                          || (u32ActivityState & MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.Msrs.u64Misc)),
+                          || (u32ActivityState & RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Misc, VMX_BF_MISC_ACTIVITY_STATES)),
                              VMX_IGS_ACTIVITY_STATE_INVALID);
         HMVMX_CHECK_BREAK(   !(pCtx->ss.Attr.n.u2Dpl)
@@ -10714,5 +10715,5 @@
          *        currently don't use activity states but ACTIVE. */
 
-        HMVMX_CHECK_BREAK(   !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
+        HMVMX_CHECK_BREAK(   !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
                           || u32ActivityState != VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT, VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID);
 
@@ -10744,8 +10745,8 @@
         HMVMX_CHECK_BREAK(!(u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
                           VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID);
-        HMVMX_CHECK_BREAK(   !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_VMCS_CTRL_ENTRY_ENTRY_SMM)
+        HMVMX_CHECK_BREAK(   !(pVCpu->hm.s.vmx.u32EntryCtls & VMX_ENTRY_CTLS_ENTRY_TO_SMM)
                           || (u32IntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI),
                              VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID);
-        if (   (pVCpu->hm.s.vmx.u32PinCtls & VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI)
+        if (   (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI)
             && VMX_ENTRY_INT_INFO_IS_VALID(u32EntryInfo)
             && VMX_ENTRY_INT_INFO_TYPE(u32EntryInfo) == VMX_EXIT_INT_INFO_TYPE_NMI)
@@ -10868,5 +10869,5 @@
 
     uint32_t uIntType = VMX_EXIT_INT_INFO_TYPE(pVmxTransient->uExitIntInfo);
-    Assert(   !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT)
+    Assert(   !(pVCpu->hm.s.vmx.u32ExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT)
            && uIntType != VMX_EXIT_INT_INFO_TYPE_EXT_INT);
     Assert(VMX_EXIT_INT_INFO_IS_VALID(pVmxTransient->uExitIntInfo));
@@ -11013,5 +11014,5 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
-    if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT)))
+    if (RT_UNLIKELY(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT)))
     {
         AssertMsgFailed(("Unexpected NMI-window exit.\n"));
@@ -11151,5 +11152,5 @@
         /* If we get a spurious VM-exit when offsetting is enabled,
            we must reset offsetting on VM-reentry. See @bugref{6634}. */
-        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
             pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
         ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
@@ -11180,5 +11181,5 @@
         /* If we get a spurious VM-exit when offsetting is enabled,
            we must reset offsetting on VM-reentry. See @bugref{6634}. */
-        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING)
+        if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING)
             pVmxTransient->fUpdateTscOffsettingAndPreemptTimer = true;
         ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
@@ -11453,5 +11454,5 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_HLT_EXIT);
 
     int rc = hmR0VmxAdvanceGuestRip(pVCpu, pVmxTransient);
@@ -11632,7 +11633,7 @@
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
-    /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT. */
+    /* By default, we don't enable VMX_PROC_CTLS2_DESCRIPTOR_TABLE_EXIT. */
     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitXdtrAccess);
-    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT)
+    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT)
         return VERR_EM_INTERPRETER;
     AssertMsgFailed(("Unexpected XDTR access\n"));
@@ -11648,6 +11649,6 @@
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
 
-    /* By default, we don't enable VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT. */
-    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT)
+    /* By default, we don't enable VMX_PROC_CTLS2_RDRAND_EXIT. */
+    if (pVCpu->hm.s.vmx.u32ProcCtls2 & VMX_PROC_CTLS2_RDRAND_EXIT)
         return VERR_EM_INTERPRETER;
     AssertMsgFailed(("Unexpected RDRAND exit\n"));
@@ -11675,5 +11676,5 @@
 
 #ifdef VBOX_STRICT
-    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS)
+    if (pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS)
     {
         if (   hmR0VmxIsAutoLoadStoreGuestMsr(pVCpu, idMsr)
@@ -11765,5 +11766,5 @@
 
         /* Update MSRs that are part of the VMCS and auto-load/store area when MSR-bitmaps are not supported. */
-        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS))
+        if (!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS))
         {
             switch (idMsr)
@@ -11864,5 +11865,5 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
 
     /*
@@ -11974,5 +11975,5 @@
                 {
                     STAM_COUNTER_INC(&pVCpu->hm.s.StatExitCR8Write);
-                    Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
+                    Assert(!(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
                     ASMAtomicUoOrU64(&pVCpu->hm.s.fCtxChanged,
                                      HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS | HM_CHANGED_GUEST_APIC_TPR);
@@ -11994,5 +11995,5 @@
             /* CR8 reads only cause a VM-exit when the TPR shadow feature isn't enabled. */
             Assert(   VMX_EXIT_QUAL_CRX_REGISTER(uExitQualification) != 8
-                   || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW));
+                   || !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW));
 
             rcStrict = IEMExecDecodedMovCRxRead(pVCpu, pVmxTransient->cbInstr,
@@ -12127,5 +12128,6 @@
             Log4(("CS:RIP=%04x:%08RX64 %#06x/%u %c str\n", pCtx->cs.Sel, pCtx->rip, uIOPort, cbValue, fIOWrite ? 'w' : 'r'));
             AssertReturn(pCtx->dx == uIOPort, VERR_VMX_IPE_2);
-            if (MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64Basic))
+            bool const fInsOutsInfo = RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
+            if (fInsOutsInfo)
             {
                 int rc2  = hmR0VmxReadExitInstrInfoVmcs(pVmxTransient);
@@ -12368,6 +12370,6 @@
 {
     HMVMX_VALIDATE_EXIT_HANDLER_PARAMS(pVCpu, pVmxTransient);
-    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
-    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG;
+    Assert(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
+    pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MONITOR_TRAP_FLAG;
     int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
     AssertRCReturn(rc, rc);
@@ -12417,5 +12419,5 @@
         case VMX_APIC_ACCESS_TYPE_LINEAR_READ:
         {
-            AssertMsg(   !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW)
+            AssertMsg(   !(pVCpu->hm.s.vmx.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW)
                       || VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(pVmxTransient->uExitQualification) != XAPIC_OFF_TPR,
                       ("hmR0VmxExitApicAccess: can't access TPR offset while using TPR shadowing.\n"));
@@ -12478,5 +12480,5 @@
 
         /* Don't intercept MOV DRx any more. */
-        pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT;
+        pVCpu->hm.s.vmx.u32ProcCtls &= ~VMX_PROC_CTLS_MOV_DR_EXIT;
         int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PROC_EXEC, pVCpu->hm.s.vmx.u32ProcCtls);
         AssertRCReturn(rc, rc);
Index: /trunk/src/VBox/VMM/VMMR3/CPUM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR3/CPUM.cpp	(revision 73389)
@@ -901,4 +901,295 @@
 
 /**
+ * Displays the host and guest VMX features.
+ *
+ * @param   pVM         The cross context VM structure.
+ * @param   pHlp        The info helper functions.
+ * @param   pszArgs     "terse", "default" or "verbose".
+ */
+DECLCALLBACK(void) cpumR3InfoVmxFeatures(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
+{
+    RT_NOREF(pszArgs);
+    PCCPUMFEATURES pHostFeatures  = &pVM->cpum.s.HostFeatures;
+    PCCPUMFEATURES pGuestFeatures = &pVM->cpum.s.GuestFeatures;
+    if (   pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_INTEL
+        || pHostFeatures->enmCpuVendor == CPUMCPUVENDOR_VIA)
+    {
+#define VMXFEATDUMP(a_szDesc, a_Var) \
+        pHlp->pfnPrintf(pHlp, "  %s = %u (%u)\n", a_szDesc, pGuestFeatures->a_Var, pHostFeatures->a_Var)
+
+        pHlp->pfnPrintf(pHlp, "Nested hardware virtualization - VMX features\n");
+        pHlp->pfnPrintf(pHlp, "  Mnemonic - Description                                  = guest (host)\n");
+        VMXFEATDUMP("VMX - Virtual-Machine Extensions                       ", fVmx);
+        /* Basic. */
+        VMXFEATDUMP("InsOutInfo - INS/OUTS instruction info.                ", fVmxInsOutInfo);
+        /* Pin-based controls. */
+        VMXFEATDUMP("ExtIntExit - External interrupt VM-exit                ", fVmxExtIntExit);
+        VMXFEATDUMP("NmiExit - NMI VM-exit                                  ", fVmxNmiExit);
+        VMXFEATDUMP("VirtNmi - Virtual NMIs                                 ", fVmxVirtNmi);
+        VMXFEATDUMP("PreemptTimer - VMX preemption timer                    ", fVmxPreemptTimer);
+        /* Processor-based controls. */
+        VMXFEATDUMP("IntWindowExit - Interrupt-window exiting               ", fVmxIntWindowExit);
+        VMXFEATDUMP("TscOffsetting - TSC offsetting                         ", fVmxTscOffsetting);
+        VMXFEATDUMP("HltExit - HLT exiting                                  ", fVmxHltExit);
+        VMXFEATDUMP("InvlpgExit - INVLPG exiting                            ", fVmxInvlpgExit);
+        VMXFEATDUMP("MwaitExit - MWAIT exiting                              ", fVmxMwaitExit);
+        VMXFEATDUMP("RdpmcExit - RDPMC exiting                              ", fVmxRdpmcExit);
+        VMXFEATDUMP("RdtscExit - RDTSC exiting                              ", fVmxRdtscExit);
+        VMXFEATDUMP("Cr3LoadExit - CR3-load exiting                         ", fVmxCr3LoadExit);
+        VMXFEATDUMP("Cr3StoreExit - CR3-store exiting                       ", fVmxCr3StoreExit);
+        VMXFEATDUMP("Cr8LoadExit  - CR8-load exiting                        ", fVmxCr8LoadExit);
+        VMXFEATDUMP("Cr8StoreExit - CR8-store exiting                       ", fVmxCr8StoreExit);
+        VMXFEATDUMP("TprShadow - TPR shadow                                 ", fVmxTprShadow);
+        VMXFEATDUMP("NmiWindowExit - NMI-window exiting                     ", fVmxNmiWindowExit);
+        VMXFEATDUMP("MovDRxExit - Mov-DR exiting                            ", fVmxMovDRxExit);
+        VMXFEATDUMP("UncondIoExit - Unconditional I/O exiting               ", fVmxUncondIoExit);
+        VMXFEATDUMP("UseIoBitmaps - Use I/O bitmaps                         ", fVmxUseIoBitmaps);
+        VMXFEATDUMP("MonitorTrapFlag - Monitor trap flag                    ", fVmxMonitorTrapFlag);
+        VMXFEATDUMP("UseMsrBitmaps - MSR bitmaps                            ", fVmxUseMsrBitmaps);
+        VMXFEATDUMP("MonitorExit - MONITOR exiting                          ", fVmxMonitorExit);
+        VMXFEATDUMP("PauseExit - PAUSE exiting                              ", fVmxPauseExit);
+        VMXFEATDUMP("SecondaryExecCtl - Activate secondary controls         ", fVmxSecondaryExecCtls);
+        /* Secondary processor-based controls. */
+        VMXFEATDUMP("VirtApic - Virtualize-APIC accesses                    ", fVmxVirtApicAccess);
+        VMXFEATDUMP("Ept - Extended Page Tables                             ", fVmxEpt);
+        VMXFEATDUMP("DescTableExit - Descriptor-table exiting               ", fVmxDescTableExit);
+        VMXFEATDUMP("Rdtscp - Enable RDTSCP                                 ", fVmxRdtscp);
+        VMXFEATDUMP("VirtX2Apic - Virtualize-x2APIC accesses                ", fVmxVirtX2ApicAccess);
+        VMXFEATDUMP("Vpid - Enable VPID                                     ", fVmxVpid);
+        VMXFEATDUMP("WbinvdExit - WBINVD exiting                            ", fVmxWbinvdExit);
+        VMXFEATDUMP("UnrestrictedGuest - Unrestricted guest                 ", fVmxUnrestrictedGuest);
+        VMXFEATDUMP("PauseLoopExit - PAUSE-loop exiting                     ", fVmxPauseLoopExit);
+        VMXFEATDUMP("Invpcid - Enable INVPCID                               ", fVmxInvpcid);
+        /* VM-entry controls. */
+        VMXFEATDUMP("EntryLoadDebugCtls - Load debug controls on VM-entry   ", fVmxEntryLoadDebugCtls);
+        VMXFEATDUMP("Ia32eModeGuest - IA-32e mode guest                     ", fVmxIa32eModeGuest);
+        VMXFEATDUMP("EntryLoadEferMsr - Load IA32_EFER on VM-entry          ", fVmxEntryLoadEferMsr);
+        /* VM-exit controls. */
+        VMXFEATDUMP("ExitSaveDebugCtls - Save debug controls on VM-exit     ", fVmxExitSaveDebugCtls);
+        VMXFEATDUMP("HostAddrSpaceSize - Host address-space size            ", fVmxHostAddrSpaceSize);
+        VMXFEATDUMP("ExitAckExtInt - Acknowledge interrupt on VM-exit       ", fVmxExitAckExtInt);
+        VMXFEATDUMP("ExitSaveEferMsr - Save IA32_EFER on VM-exit            ", fVmxExitSaveEferMsr);
+        VMXFEATDUMP("ExitLoadEferMsr - Load IA32_EFER on VM-exit            ", fVmxExitLoadEferMsr);
+        VMXFEATDUMP("SavePreemptTimer - Save VMX-preemption timer           ", fVmxSavePreemptTimer);
+        VMXFEATDUMP("ExitStoreEferLma - Store EFER.LMA on VM-exit           ", fVmxExitStoreEferLma);
+        VMXFEATDUMP("VmwriteAll - VMWRITE to any VMCS field                 ", fVmxVmwriteAll);
+        VMXFEATDUMP("EntryInjectSoftInt - Inject softint. with 0-len instr. ", fVmxEntryInjectSoftInt);
+#undef VMXFEATDUMP
+    }
+    else
+        pHlp->pfnPrintf(pHlp, "No VMX features present - requires an Intel or compatible CPU.\n");
+}
+
+
+/**
+ * Initializes VMX host and guest features.
+ *
+ * @param   pVM     The cross context VM structure.
+ *
+ * @remarks This must be called only after HM has fully initialized since it calls
+ *          into HM to retrieve VMX and related MSRs.
+ */
+static void cpumR3InitVmxCpuFeatures(PVM pVM)
+{
+    /*
+     * Init. host features.
+     */
+    PCPUMFEATURES pHostFeat = &pVM->cpum.s.HostFeatures;
+    VMXMSRS VmxMsrs;
+    int rc = HMVmxGetHostMsrs(pVM, &VmxMsrs);
+    if (RT_SUCCESS(rc))
+    {
+        /* Basic information. */
+        pHostFeat->fVmxInsOutInfo            = RT_BF_GET(VmxMsrs.u64Basic, VMX_BF_BASIC_VMCS_INS_OUTS);
+
+        /* Pin-based VM-execution controls. */
+        uint32_t const fPinCtls = VmxMsrs.PinCtls.n.allowed1;
+        pHostFeat->fVmxExtIntExit            = RT_BOOL(fPinCtls & VMX_PIN_CTLS_EXT_INT_EXIT);
+        pHostFeat->fVmxNmiExit               = RT_BOOL(fPinCtls & VMX_PIN_CTLS_NMI_EXIT);
+        pHostFeat->fVmxVirtNmi               = RT_BOOL(fPinCtls & VMX_PIN_CTLS_VIRT_NMI);
+        pHostFeat->fVmxPreemptTimer          = RT_BOOL(fPinCtls & VMX_PIN_CTLS_PREEMPT_TIMER);
+
+        /* Processor-based VM-execution controls. */
+        uint32_t const fProcCtls = VmxMsrs.ProcCtls.n.allowed1;
+        pHostFeat->fVmxIntWindowExit         = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INT_WINDOW_EXIT);
+        pHostFeat->fVmxTscOffsetting         = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TSC_OFFSETTING);
+        pHostFeat->fVmxHltExit               = RT_BOOL(fProcCtls & VMX_PROC_CTLS_HLT_EXIT);
+        pHostFeat->fVmxInvlpgExit            = RT_BOOL(fProcCtls & VMX_PROC_CTLS_INVLPG_EXIT);
+        pHostFeat->fVmxMwaitExit             = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MWAIT_EXIT);
+        pHostFeat->fVmxRdpmcExit             = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDPMC_EXIT);
+        pHostFeat->fVmxRdtscExit             = RT_BOOL(fProcCtls & VMX_PROC_CTLS_RDTSC_EXIT);
+        pHostFeat->fVmxCr3LoadExit           = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_LOAD_EXIT);
+        pHostFeat->fVmxCr3StoreExit          = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR3_STORE_EXIT);
+        pHostFeat->fVmxCr8LoadExit           = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_LOAD_EXIT);
+        pHostFeat->fVmxCr8StoreExit          = RT_BOOL(fProcCtls & VMX_PROC_CTLS_CR8_STORE_EXIT);
+        pHostFeat->fVmxTprShadow             = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW);
+        pHostFeat->fVmxNmiWindowExit         = RT_BOOL(fProcCtls & VMX_PROC_CTLS_NMI_WINDOW_EXIT);
+        pHostFeat->fVmxMovDRxExit            = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MOV_DR_EXIT);
+        pHostFeat->fVmxUncondIoExit          = RT_BOOL(fProcCtls & VMX_PROC_CTLS_UNCOND_IO_EXIT);
+        pHostFeat->fVmxUseIoBitmaps          = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_IO_BITMAPS);
+        pHostFeat->fVmxMonitorTrapFlag       = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
+        pHostFeat->fVmxUseMsrBitmaps         = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_MSR_BITMAPS);
+        pHostFeat->fVmxMonitorExit           = RT_BOOL(fProcCtls & VMX_PROC_CTLS_MONITOR_EXIT);
+        pHostFeat->fVmxPauseExit             = RT_BOOL(fProcCtls & VMX_PROC_CTLS_PAUSE_EXIT);
+        pHostFeat->fVmxSecondaryExecCtls     = RT_BOOL(fProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
+
+        /* Secondary processor-based VM-execution controls. */
+        if (pHostFeat->fVmxSecondaryExecCtls)
+        {
+            uint32_t const fProcCtls2 = VmxMsrs.ProcCtls2.n.allowed1;
+            pHostFeat->fVmxVirtApicAccess    = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
+            pHostFeat->fVmxEpt               = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_EPT);
+            pHostFeat->fVmxDescTableExit     = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_DESC_TABLE_EXIT);
+            pHostFeat->fVmxRdtscp            = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_RDTSCP);
+            pHostFeat->fVmxVirtX2ApicAccess  = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
+            pHostFeat->fVmxVpid              = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_VPID);
+            pHostFeat->fVmxWbinvdExit        = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_WBINVD_EXIT);
+            pHostFeat->fVmxUnrestrictedGuest = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
+            pHostFeat->fVmxPauseLoopExit     = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
+            pHostFeat->fVmxInvpcid           = RT_BOOL(fProcCtls2 & VMX_PROC_CTLS2_INVPCID);
+        }
+
+        /* VM-entry controls. */
+        uint32_t const fEntryCtls = VmxMsrs.EntryCtls.n.allowed1;
+        pHostFeat->fVmxEntryLoadDebugCtls    = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_DEBUG);
+        pHostFeat->fVmxIa32eModeGuest        = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
+        pHostFeat->fVmxEntryLoadEferMsr      = RT_BOOL(fEntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR);
+
+        /* VM-exit controls. */
+        uint32_t const fExitCtls = VmxMsrs.ExitCtls.n.allowed1;
+        pHostFeat->fVmxExitSaveDebugCtls     = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_DEBUG);
+        pHostFeat->fVmxHostAddrSpaceSize     = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
+        pHostFeat->fVmxExitAckExtInt         = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_ACK_EXT_INT);
+        pHostFeat->fVmxExitSaveEferMsr       = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_EFER_MSR);
+        pHostFeat->fVmxExitLoadEferMsr       = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_LOAD_EFER_MSR);
+        pHostFeat->fVmxSavePreemptTimer      = RT_BOOL(fExitCtls & VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
+
+        /* Miscellaneous data. */
+        uint32_t const fMiscData = VmxMsrs.u64Misc;
+        pHostFeat->fVmxExitStoreEferLma      = RT_BOOL(fMiscData & VMX_MISC_EXIT_STORE_EFER_LMA);
+        pHostFeat->fVmxVmwriteAll            = RT_BOOL(fMiscData & VMX_MISC_VMWRITE_ALL);
+        pHostFeat->fVmxEntryInjectSoftInt    = RT_BOOL(fMiscData & VMX_MISC_ENTRY_INJECT_SOFT_INT);
+    }
+
+    /*
+     * Initialize the set of VMX features we emulate.
+     * Note! Some bits might be reported as 1 always if they fall under the default1 class bits
+     *       (e.g. fVmxEntryLoadDebugCtls), see @bugref{9180#c5}.
+     */
+    CPUMFEATURES EmuFeat;
+    RT_ZERO(EmuFeat);
+    EmuFeat.fVmx                      = 1;
+    EmuFeat.fVmxInsOutInfo            = 0;
+    EmuFeat.fVmxExtIntExit            = 1;
+    EmuFeat.fVmxNmiExit               = 1;
+    EmuFeat.fVmxVirtNmi               = 0;
+    EmuFeat.fVmxPreemptTimer          = 0;
+    EmuFeat.fVmxIntWindowExit         = 1;
+    EmuFeat.fVmxTscOffsetting         = 1;
+    EmuFeat.fVmxHltExit               = 1;
+    EmuFeat.fVmxInvlpgExit            = 1;
+    EmuFeat.fVmxMwaitExit             = 1;
+    EmuFeat.fVmxRdpmcExit             = 1;
+    EmuFeat.fVmxRdtscExit             = 1;
+    EmuFeat.fVmxCr3LoadExit           = 1;
+    EmuFeat.fVmxCr3StoreExit          = 1;
+    EmuFeat.fVmxCr8LoadExit           = 1;
+    EmuFeat.fVmxCr8StoreExit          = 1;
+    EmuFeat.fVmxTprShadow             = 0;
+    EmuFeat.fVmxNmiWindowExit         = 0;
+    EmuFeat.fVmxMovDRxExit            = 1;
+    EmuFeat.fVmxUncondIoExit          = 1;
+    EmuFeat.fVmxUseIoBitmaps          = 1;
+    EmuFeat.fVmxMonitorTrapFlag       = 0;
+    EmuFeat.fVmxUseMsrBitmaps         = 0;
+    EmuFeat.fVmxMonitorExit           = 1;
+    EmuFeat.fVmxPauseExit             = 1;
+    EmuFeat.fVmxSecondaryExecCtls     = 1;
+    EmuFeat.fVmxVirtApicAccess        = 0;
+    EmuFeat.fVmxEpt                   = 0;
+    EmuFeat.fVmxDescTableExit         = 1;
+    EmuFeat.fVmxRdtscp                = 1;
+    EmuFeat.fVmxVirtX2ApicAccess      = 0;
+    EmuFeat.fVmxVpid                  = 0;
+    EmuFeat.fVmxWbinvdExit            = 1;
+    EmuFeat.fVmxUnrestrictedGuest     = 0;
+    EmuFeat.fVmxPauseLoopExit         = 0;
+    EmuFeat.fVmxInvpcid               = 1;
+    EmuFeat.fVmxEntryLoadDebugCtls    = 1;
+    EmuFeat.fVmxIa32eModeGuest        = 1;
+    EmuFeat.fVmxEntryLoadEferMsr      = 1;
+    EmuFeat.fVmxExitSaveDebugCtls     = 1;
+    EmuFeat.fVmxHostAddrSpaceSize     = 1;
+    EmuFeat.fVmxExitAckExtInt         = 0;
+    EmuFeat.fVmxExitSaveEferMsr       = 1;
+    EmuFeat.fVmxExitLoadEferMsr       = 1;
+    EmuFeat.fVmxSavePreemptTimer      = 0;
+    EmuFeat.fVmxExitStoreEferLma      = 1;
+    EmuFeat.fVmxVmwriteAll            = 0;
+    EmuFeat.fVmxEntryInjectSoftInt    = 0;
+
+    /*
+     * Explode guest features.
+     *
+     * When hardware-assisted VMX may be used, any feature we emulate must also be supported
+     * by the hardware, hence we merge our emulated features with the host features below.
+     */
+    bool const fHostSupportsVmx = pHostFeat->fVmx;
+    AssertLogRelReturnVoid(!fHostSupportsVmx || HMIsVmxSupported(pVM));
+    PCCPUMFEATURES pBaseFeat    = fHostSupportsVmx ? pHostFeat : &EmuFeat;
+    PCPUMFEATURES  pGuestFeat   = &pVM->cpum.s.GuestFeatures;
+    pGuestFeat->fVmx                      = (pBaseFeat->fVmx                      & EmuFeat.fVmx                     );
+    pGuestFeat->fVmxInsOutInfo            = (pBaseFeat->fVmxInsOutInfo            & EmuFeat.fVmxInsOutInfo           );
+    pGuestFeat->fVmxExtIntExit            = (pBaseFeat->fVmxExtIntExit            & EmuFeat.fVmxExtIntExit           );
+    pGuestFeat->fVmxNmiExit               = (pBaseFeat->fVmxNmiExit               & EmuFeat.fVmxNmiExit              );
+    pGuestFeat->fVmxVirtNmi               = (pBaseFeat->fVmxVirtNmi               & EmuFeat.fVmxVirtNmi              );
+    pGuestFeat->fVmxPreemptTimer          = (pBaseFeat->fVmxPreemptTimer          & EmuFeat.fVmxPreemptTimer         );
+    pGuestFeat->fVmxIntWindowExit         = (pBaseFeat->fVmxIntWindowExit         & EmuFeat.fVmxIntWindowExit        );
+    pGuestFeat->fVmxTscOffsetting         = (pBaseFeat->fVmxTscOffsetting         & EmuFeat.fVmxTscOffsetting        );
+    pGuestFeat->fVmxHltExit               = (pBaseFeat->fVmxHltExit               & EmuFeat.fVmxHltExit              );
+    pGuestFeat->fVmxInvlpgExit            = (pBaseFeat->fVmxInvlpgExit            & EmuFeat.fVmxInvlpgExit           );
+    pGuestFeat->fVmxMwaitExit             = (pBaseFeat->fVmxMwaitExit             & EmuFeat.fVmxMwaitExit            );
+    pGuestFeat->fVmxRdpmcExit             = (pBaseFeat->fVmxRdpmcExit             & EmuFeat.fVmxRdpmcExit            );
+    pGuestFeat->fVmxRdtscExit             = (pBaseFeat->fVmxRdtscExit             & EmuFeat.fVmxRdtscExit            );
+    pGuestFeat->fVmxCr3LoadExit           = (pBaseFeat->fVmxCr3LoadExit           & EmuFeat.fVmxCr3LoadExit          );
+    pGuestFeat->fVmxCr3StoreExit          = (pBaseFeat->fVmxCr3StoreExit          & EmuFeat.fVmxCr3StoreExit         );
+    pGuestFeat->fVmxCr8LoadExit           = (pBaseFeat->fVmxCr8LoadExit           & EmuFeat.fVmxCr8LoadExit          );
+    pGuestFeat->fVmxCr8StoreExit          = (pBaseFeat->fVmxCr8StoreExit          & EmuFeat.fVmxCr8StoreExit         );
+    pGuestFeat->fVmxTprShadow             = (pBaseFeat->fVmxTprShadow             & EmuFeat.fVmxTprShadow            );
+    pGuestFeat->fVmxNmiWindowExit         = (pBaseFeat->fVmxNmiWindowExit         & EmuFeat.fVmxNmiWindowExit        );
+    pGuestFeat->fVmxMovDRxExit            = (pBaseFeat->fVmxMovDRxExit            & EmuFeat.fVmxMovDRxExit           );
+    pGuestFeat->fVmxUncondIoExit          = (pBaseFeat->fVmxUncondIoExit          & EmuFeat.fVmxUncondIoExit         );
+    pGuestFeat->fVmxUseIoBitmaps          = (pBaseFeat->fVmxUseIoBitmaps          & EmuFeat.fVmxUseIoBitmaps         );
+    pGuestFeat->fVmxMonitorTrapFlag       = (pBaseFeat->fVmxMonitorTrapFlag       & EmuFeat.fVmxMonitorTrapFlag      );
+    pGuestFeat->fVmxUseMsrBitmaps         = (pBaseFeat->fVmxUseMsrBitmaps         & EmuFeat.fVmxUseMsrBitmaps        );
+    pGuestFeat->fVmxMonitorExit           = (pBaseFeat->fVmxMonitorExit           & EmuFeat.fVmxMonitorExit          );
+    pGuestFeat->fVmxPauseExit             = (pBaseFeat->fVmxPauseExit             & EmuFeat.fVmxPauseExit            );
+    pGuestFeat->fVmxSecondaryExecCtls     = (pBaseFeat->fVmxSecondaryExecCtls     & EmuFeat.fVmxSecondaryExecCtls    );
+    pGuestFeat->fVmxVirtApicAccess        = (pBaseFeat->fVmxVirtApicAccess        & EmuFeat.fVmxVirtApicAccess       );
+    pGuestFeat->fVmxEpt                   = (pBaseFeat->fVmxEpt                   & EmuFeat.fVmxEpt                  );
+    pGuestFeat->fVmxDescTableExit         = (pBaseFeat->fVmxDescTableExit         & EmuFeat.fVmxDescTableExit        );
+    pGuestFeat->fVmxRdtscp                = (pBaseFeat->fVmxRdtscp                & EmuFeat.fVmxRdtscp               );
+    pGuestFeat->fVmxVirtX2ApicAccess      = (pBaseFeat->fVmxVirtX2ApicAccess      & EmuFeat.fVmxVirtX2ApicAccess     );
+    pGuestFeat->fVmxVpid                  = (pBaseFeat->fVmxVpid                  & EmuFeat.fVmxVpid                 );
+    pGuestFeat->fVmxWbinvdExit            = (pBaseFeat->fVmxWbinvdExit            & EmuFeat.fVmxWbinvdExit           );
+    pGuestFeat->fVmxUnrestrictedGuest     = (pBaseFeat->fVmxUnrestrictedGuest     & EmuFeat.fVmxUnrestrictedGuest    );
+    pGuestFeat->fVmxPauseLoopExit         = (pBaseFeat->fVmxPauseLoopExit         & EmuFeat.fVmxPauseLoopExit        );
+    pGuestFeat->fVmxInvpcid               = (pBaseFeat->fVmxInvpcid               & EmuFeat.fVmxInvpcid              );
+    pGuestFeat->fVmxEntryLoadDebugCtls    = (pBaseFeat->fVmxEntryLoadDebugCtls    & EmuFeat.fVmxEntryLoadDebugCtls   );
+    pGuestFeat->fVmxIa32eModeGuest        = (pBaseFeat->fVmxIa32eModeGuest        & EmuFeat.fVmxIa32eModeGuest       );
+    pGuestFeat->fVmxEntryLoadEferMsr      = (pBaseFeat->fVmxEntryLoadEferMsr      & EmuFeat.fVmxEntryLoadEferMsr);
+    pGuestFeat->fVmxExitSaveDebugCtls     = (pBaseFeat->fVmxExitSaveDebugCtls     & EmuFeat.fVmxExitSaveDebugCtls    );
+    pGuestFeat->fVmxHostAddrSpaceSize     = (pBaseFeat->fVmxHostAddrSpaceSize     & EmuFeat.fVmxHostAddrSpaceSize    );
+    pGuestFeat->fVmxExitAckExtInt         = (pBaseFeat->fVmxExitAckExtInt         & EmuFeat.fVmxExitAckExtInt        );
+    pGuestFeat->fVmxExitSaveEferMsr       = (pBaseFeat->fVmxExitSaveEferMsr       & EmuFeat.fVmxExitSaveEferMsr      );
+    pGuestFeat->fVmxExitLoadEferMsr       = (pBaseFeat->fVmxExitLoadEferMsr       & EmuFeat.fVmxExitLoadEferMsr      );
+    pGuestFeat->fVmxSavePreemptTimer      = (pBaseFeat->fVmxSavePreemptTimer      & EmuFeat.fVmxSavePreemptTimer     );
+    pGuestFeat->fVmxExitStoreEferLma      = (pBaseFeat->fVmxExitStoreEferLma      & EmuFeat.fVmxExitStoreEferLma     );
+    pGuestFeat->fVmxVmwriteAll            = (pBaseFeat->fVmxVmwriteAll            & EmuFeat.fVmxVmwriteAll           );
+    pGuestFeat->fVmxEntryInjectSoftInt    = (pBaseFeat->fVmxEntryInjectSoftInt    & EmuFeat.fVmxEntryInjectSoftInt   );
+}
+
+
+/**
  * Initializes the CPUM.
  *
@@ -1061,4 +1352,6 @@
                                  &cpumR3InfoGuestInstr, DBGFINFO_FLAGS_ALL_EMTS);
     DBGFR3InfoRegisterInternal(  pVM, "cpuid",            "Displays the guest cpuid leaves.",         &cpumR3CpuIdInfo);
+    DBGFR3InfoRegisterInternal(  pVM, "cpumvmxfeat",      "Displays the host and guest VMX hwvirt. features.",
+                               &cpumR3InfoVmxFeatures);
 
     rc = cpumR3DbgInit(pVM);
@@ -3002,4 +3295,26 @@
         }
 
+        case VMINITCOMPLETED_HM:
+        {
+            /*
+             * Currently, nested VMX/SVM both derives their guest VMX/SVM CPUID bit from the host
+             * CPUID bit. This could be later changed if we need to support nested-VMX on CPUs
+             * that are not capable of VMX.
+             */
+            if (pVM->cpum.s.GuestFeatures.fVmx)
+            {
+                Assert(   pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
+                       || pVM->cpum.s.GuestFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
+                cpumR3InitVmxCpuFeatures(pVM);
+                DBGFR3Info(pVM->pUVM, "cpumvmxfeat", "default", DBGFR3InfoLogRelHlp());
+            }
+
+            if (pVM->cpum.s.GuestFeatures.fVmx)
+                LogRel(("CPUM: Enabled guest VMX support\n"));
+            else if (pVM->cpum.s.GuestFeatures.fSvm)
+                LogRel(("CPUM: Enabled guest SVM support\n"));
+            break;
+        }
+
         default:
             break;
Index: /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp	(revision 73389)
@@ -1738,6 +1738,5 @@
         pFeatures->fPcid                = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_PCID);
         pFeatures->fVmx                 = RT_BOOL(pStd1Leaf->uEcx & X86_CPUID_FEATURE_ECX_VMX);
-        if (pFeatures->fVmx)
-        { /** @todo Support other VMX features */ }
+        /* VMX sub-features will be initialized in cpumR3InitVmxCpuFeatures(). */
 
         /* Structured extended features. */
Index: /trunk/src/VBox/VMM/VMMR3/GIMHv.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/GIMHv.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR3/GIMHv.cpp	(revision 73389)
@@ -555,6 +555,6 @@
     {
         /* Hypervisor capabilities; features used by the hypervisor. */
-        pHv->uHyperCaps  = HMIsNestedPagingActive(pVM)   ? GIM_HV_HOST_FEAT_NESTED_PAGING : 0;
-        pHv->uHyperCaps |= HMAreMsrBitmapsAvailable(pVM) ? GIM_HV_HOST_FEAT_MSR_BITMAP : 0;
+        pHv->uHyperCaps  = HMIsNestedPagingActive(pVM) ? GIM_HV_HOST_FEAT_NESTED_PAGING : 0;
+        pHv->uHyperCaps |= HMIsMsrBitmapActive(pVM)    ? GIM_HV_HOST_FEAT_MSR_BITMAP    : 0;
     }
 
Index: /trunk/src/VBox/VMM/VMMR3/HM.cpp
===================================================================
--- /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 73388)
+++ /trunk/src/VBox/VMM/VMMR3/HM.cpp	(revision 73389)
@@ -1334,6 +1334,6 @@
 
 /**
- * Returns the VMCS (and associated regions') memory type given the IA32_VMX_BASIC
- * MSR.
+ * Returns a description of the VMCS (and associated regions') memory type given the
+ * IA32_VMX_BASIC MSR.
  *
  * @returns The descriptive memory type.
@@ -1342,11 +1342,37 @@
 static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
 {
-    uint8_t const uMemType = MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(uMsrVmxBasic);
+    uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
     switch (uMemType)
     {
-        case VMX_VMCS_MEM_TYPE_WB: return "Write Back (WB)";
-        case VMX_VMCS_MEM_TYPE_UC: return "Uncacheable (UC)";
+        case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
+        case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
     }
     return "Unknown";
+}
+
+
+/**
+ * Returns a single-line description of all the activity-states supported by the CPU
+ * given the IA32_VMX_MISC MSR.
+ *
+ * @returns All supported activity states.
+ * @param   uMsrMisc            IA32_VMX_MISC MSR value.
+ */
+static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
+{
+    static const char * const s_apszActStates[] =
+    {
+        "",
+        " ( HLT )",
+        " ( SHUTDOWN )",
+        " ( HLT SHUTDOWN )",
+        " ( SIPI_WAIT )",
+        " ( HLT SIPI_WAIT )",
+        " ( SHUTDOWN SIPI_WAIT )",
+        " ( HLT SHUTDOWN SIPI_WAIT )"
+    };
+    uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
+    Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
+    return s_apszActStates[idxActStates];
 }
 
@@ -1387,13 +1413,13 @@
 static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
 {
-    LogRel(("HM: MSR_IA32_VMX_BASIC                = %#RX64\n", uBasicMsr));
-    LogRel(("HM:   VMCS id                           = %#x\n",      MSR_IA32_VMX_BASIC_VMCS_ID(uBasicMsr)));
-    LogRel(("HM:   VMCS size                         = %u bytes\n", MSR_IA32_VMX_BASIC_VMCS_SIZE(uBasicMsr)));
-    LogRel(("HM:   VMCS physical address limit       = %s\n",       MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(uBasicMsr) ? "< 4 GB"
-                                                                                                                : "None"));
+    LogRel(("HM: MSR_IA32_VMX_BASIC                = %#RX64\n",     uBasicMsr));
+    LogRel(("HM:   VMCS id                           = %#x\n",      RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
+    LogRel(("HM:   VMCS size                         = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
+    LogRel(("HM:   VMCS physical address limit       = %s\n",       RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
+                                                                    "< 4 GB" : "None"));
     LogRel(("HM:   VMCS memory type                  = %s\n",       hmR3VmxGetMemTypeDesc(uBasicMsr)));
-    LogRel(("HM:   Dual-monitor treatment support    = %RTbool\n",  MSR_IA32_VMX_BASIC_DUAL_MON(uBasicMsr)));
-    LogRel(("HM:   OUTS & INS instruction-info       = %RTbool\n",  MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(uBasicMsr)));
-    LogRel(("HM:   Supports true capability MSRs     = %RTbool\n",  MSR_IA32_VMX_BASIC_TRUE_CONTROLS(uBasicMsr)));
+    LogRel(("HM:   Dual-monitor treatment support    = %RTbool\n",  RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
+    LogRel(("HM:   OUTS & INS instruction-info       = %RTbool\n",  RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
+    LogRel(("HM:   Supports true capability MSRs     = %RTbool\n",  RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
 }
 
@@ -1409,9 +1435,9 @@
     uint64_t const zap = pVmxMsr->n.disallowed0;
     LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS        = %#RX64\n", pVmxMsr->u));
-    HMVMX_REPORT_FEAT(val, zap, "EXT_INT_EXIT",  VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "NMI_EXIT",      VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "VIRTUAL_NMI",   VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
-    HMVMX_REPORT_FEAT(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
-    HMVMX_REPORT_FEAT(val, zap, "POSTED_INTR",   VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
+    HMVMX_REPORT_FEAT(val, zap, "EXT_INT_EXIT",  VMX_PIN_CTLS_EXT_INT_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "NMI_EXIT",      VMX_PIN_CTLS_NMI_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "VIRTUAL_NMI",   VMX_PIN_CTLS_VIRT_NMI);
+    HMVMX_REPORT_FEAT(val, zap, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
+    HMVMX_REPORT_FEAT(val, zap, "POSTED_INT",    VMX_PIN_CTLS_POSTED_INT);
 }
 
@@ -1427,25 +1453,25 @@
     uint64_t const zap = pVmxMsr->n.disallowed0;
     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS       = %#RX64\n", pVmxMsr->u));
-    HMVMX_REPORT_FEAT(val, zap, "INT_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "USE_TSC_OFFSETTING",      VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
-    HMVMX_REPORT_FEAT(val, zap, "HLT_EXIT",                VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "INVLPG_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "MWAIT_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "RDPMC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "RDTSC_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "CR3_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "CR3_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "CR8_LOAD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "CR8_STORE_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "USE_TPR_SHADOW",          VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
-    HMVMX_REPORT_FEAT(val, zap, "NMI_WINDOW_EXIT",         VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "MOV_DR_EXIT",             VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "UNCOND_IO_EXIT",          VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "USE_IO_BITMAPS",          VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
-    HMVMX_REPORT_FEAT(val, zap, "MONITOR_TRAP_FLAG",       VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
-    HMVMX_REPORT_FEAT(val, zap, "USE_MSR_BITMAPS",         VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
-    HMVMX_REPORT_FEAT(val, zap, "MONITOR_EXIT",            VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "PAUSE_EXIT",              VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
+    HMVMX_REPORT_FEAT(val, zap, "INT_WINDOW_EXIT",         VMX_PROC_CTLS_INT_WINDOW_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "USE_TSC_OFFSETTING",      VMX_PROC_CTLS_USE_TSC_OFFSETTING);
+    HMVMX_REPORT_FEAT(val, zap, "HLT_EXIT",                VMX_PROC_CTLS_HLT_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "INVLPG_EXIT",             VMX_PROC_CTLS_INVLPG_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "MWAIT_EXIT",              VMX_PROC_CTLS_MWAIT_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "RDPMC_EXIT",              VMX_PROC_CTLS_RDPMC_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "RDTSC_EXIT",              VMX_PROC_CTLS_RDTSC_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "CR3_LOAD_EXIT",           VMX_PROC_CTLS_CR3_LOAD_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "CR3_STORE_EXIT",          VMX_PROC_CTLS_CR3_STORE_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "CR8_LOAD_EXIT",           VMX_PROC_CTLS_CR8_LOAD_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "CR8_STORE_EXIT",          VMX_PROC_CTLS_CR8_STORE_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "USE_TPR_SHADOW",          VMX_PROC_CTLS_USE_TPR_SHADOW);
+    HMVMX_REPORT_FEAT(val, zap, "NMI_WINDOW_EXIT",         VMX_PROC_CTLS_NMI_WINDOW_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "MOV_DR_EXIT",             VMX_PROC_CTLS_MOV_DR_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "UNCOND_IO_EXIT",          VMX_PROC_CTLS_UNCOND_IO_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "USE_IO_BITMAPS",          VMX_PROC_CTLS_USE_IO_BITMAPS);
+    HMVMX_REPORT_FEAT(val, zap, "MONITOR_TRAP_FLAG",       VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
+    HMVMX_REPORT_FEAT(val, zap, "USE_MSR_BITMAPS",         VMX_PROC_CTLS_USE_MSR_BITMAPS);
+    HMVMX_REPORT_FEAT(val, zap, "MONITOR_EXIT",            VMX_PROC_CTLS_MONITOR_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "PAUSE_EXIT",              VMX_PROC_CTLS_PAUSE_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "USE_SECONDARY_CTLS",      VMX_PROC_CTLS_USE_SECONDARY_CTLS);
 }
 
@@ -1461,26 +1487,26 @@
     uint64_t const zap = pVmxMsr->n.disallowed0;
     LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2      = %#RX64\n", pVmxMsr->u));
-    HMVMX_REPORT_FEAT(val, zap, "VIRT_APIC",             VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
-    HMVMX_REPORT_FEAT(val, zap, "EPT",                   VMX_VMCS_CTRL_PROC_EXEC2_EPT);
-    HMVMX_REPORT_FEAT(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "RDTSCP",                VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
-    HMVMX_REPORT_FEAT(val, zap, "VIRT_X2APIC",           VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
-    HMVMX_REPORT_FEAT(val, zap, "VPID",                  VMX_VMCS_CTRL_PROC_EXEC2_VPID);
-    HMVMX_REPORT_FEAT(val, zap, "WBINVD_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "UNRESTRICTED_GUEST",    VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
-    HMVMX_REPORT_FEAT(val, zap, "APIC_REG_VIRT",         VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
-    HMVMX_REPORT_FEAT(val, zap, "VIRT_INTR_DELIVERY",    VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
-    HMVMX_REPORT_FEAT(val, zap, "PAUSE_LOOP_EXIT",       VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "RDRAND_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "INVPCID",               VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
-    HMVMX_REPORT_FEAT(val, zap, "VMFUNC",                VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
-    HMVMX_REPORT_FEAT(val, zap, "VMCS_SHADOWING",        VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
-    HMVMX_REPORT_FEAT(val, zap, "ENCLS_EXIT",            VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "RDSEED_EXIT",           VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
-    HMVMX_REPORT_FEAT(val, zap, "PML",                   VMX_VMCS_CTRL_PROC_EXEC2_PML);
-    HMVMX_REPORT_FEAT(val, zap, "EPT_VE",                VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
-    HMVMX_REPORT_FEAT(val, zap, "CONCEAL_FROM_PT",       VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
-    HMVMX_REPORT_FEAT(val, zap, "XSAVES_XRSTORS",        VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
-    HMVMX_REPORT_FEAT(val, zap, "TSC_SCALING",           VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
+    HMVMX_REPORT_FEAT(val, zap, "VIRT_APIC_ACCESS",      VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
+    HMVMX_REPORT_FEAT(val, zap, "EPT",                   VMX_PROC_CTLS2_EPT);
+    HMVMX_REPORT_FEAT(val, zap, "DESC_TABLE_EXIT",       VMX_PROC_CTLS2_DESC_TABLE_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "RDTSCP",                VMX_PROC_CTLS2_RDTSCP);
+    HMVMX_REPORT_FEAT(val, zap, "VIRT_X2APIC_ACCESS",    VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
+    HMVMX_REPORT_FEAT(val, zap, "VPID",                  VMX_PROC_CTLS2_VPID);
+    HMVMX_REPORT_FEAT(val, zap, "WBINVD_EXIT",           VMX_PROC_CTLS2_WBINVD_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "UNRESTRICTED_GUEST",    VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
+    HMVMX_REPORT_FEAT(val, zap, "APIC_REG_VIRT",         VMX_PROC_CTLS2_APIC_REG_VIRT);
+    HMVMX_REPORT_FEAT(val, zap, "VIRT_INT_DELIVERY",     VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
+    HMVMX_REPORT_FEAT(val, zap, "PAUSE_LOOP_EXIT",       VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "RDRAND_EXIT",           VMX_PROC_CTLS2_RDRAND_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "INVPCID",               VMX_PROC_CTLS2_INVPCID);
+    HMVMX_REPORT_FEAT(val, zap, "VMFUNC",                VMX_PROC_CTLS2_VMFUNC);
+    HMVMX_REPORT_FEAT(val, zap, "VMCS_SHADOWING",        VMX_PROC_CTLS2_VMCS_SHADOWING);
+    HMVMX_REPORT_FEAT(val, zap, "ENCLS_EXIT",            VMX_PROC_CTLS2_ENCLS_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "RDSEED_EXIT",           VMX_PROC_CTLS2_RDSEED_EXIT);
+    HMVMX_REPORT_FEAT(val, zap, "PML",                   VMX_PROC_CTLS2_PML);
+    HMVMX_REPORT_FEAT(val, zap, "EPT_VE",                VMX_PROC_CTLS2_EPT_VE);
+    HMVMX_REPORT_FEAT(val, zap, "CONCEAL_FROM_PT",       VMX_PROC_CTLS2_CONCEAL_FROM_PT);
+    HMVMX_REPORT_FEAT(val, zap, "XSAVES_XRSTORS",        VMX_PROC_CTLS2_XSAVES_XRSTORS);
+    HMVMX_REPORT_FEAT(val, zap, "TSC_SCALING",           VMX_PROC_CTLS2_TSC_SCALING);
 }
 
@@ -1496,11 +1522,11 @@
     uint64_t const zap = pVmxMsr->n.disallowed0;
     LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS           = %#RX64\n", pVmxMsr->u));
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_DEBUG",          VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
-    HMVMX_REPORT_FEAT(val, zap, "IA32E_MODE_GUEST",    VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
-    HMVMX_REPORT_FEAT(val, zap, "ENTRY_SMM",           VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
-    HMVMX_REPORT_FEAT(val, zap, "DEACTIVATE_DUALMON",  VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PAT_MSR",  VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_DEBUG",          VMX_ENTRY_CTLS_LOAD_DEBUG);
+    HMVMX_REPORT_FEAT(val, zap, "IA32E_MODE_GUEST",    VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
+    HMVMX_REPORT_FEAT(val, zap, "ENTRY_TO_SMM",        VMX_ENTRY_CTLS_ENTRY_TO_SMM);
+    HMVMX_REPORT_FEAT(val, zap, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR",       VMX_ENTRY_CTLS_LOAD_PERF_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_PAT_MSR",        VMX_ENTRY_CTLS_LOAD_PAT_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_EFER_MSR",       VMX_ENTRY_CTLS_LOAD_EFER_MSR);
 }
 
@@ -1516,13 +1542,13 @@
     uint64_t const zap = pVmxMsr->n.disallowed0;
     LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS            = %#RX64\n", pVmxMsr->u));
-    HMVMX_REPORT_FEAT(val, zap, "SAVE_DEBUG",             VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
-    HMVMX_REPORT_FEAT(val, zap, "HOST_ADDR_SPACE_SIZE",   VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR",          VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "ACK_EXT_INT",            VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
-    HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_PAT_MSR",     VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_PAT_MSR",      VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_EFER_MSR",    VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_EFER_MSR",     VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
-    HMVMX_REPORT_FEAT(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
+    HMVMX_REPORT_FEAT(val, zap, "SAVE_DEBUG",             VMX_EXIT_CTLS_SAVE_DEBUG);
+    HMVMX_REPORT_FEAT(val, zap, "HOST_ADDR_SPACE_SIZE",   VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR",          VMX_EXIT_CTLS_LOAD_PERF_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "ACK_EXT_INT",            VMX_EXIT_CTLS_ACK_EXT_INT);
+    HMVMX_REPORT_FEAT(val, zap, "SAVE_PAT_MSR",           VMX_EXIT_CTLS_SAVE_PAT_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_PAT_MSR",           VMX_EXIT_CTLS_LOAD_PAT_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "SAVE_EFER_MSR",          VMX_EXIT_CTLS_SAVE_EFER_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "LOAD_EFER_MSR",          VMX_EXIT_CTLS_LOAD_EFER_MSR);
+    HMVMX_REPORT_FEAT(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
 }
 
@@ -1563,21 +1589,24 @@
 {
     LogRel(("HM: MSR_IA32_VMX_MISC                 = %#RX64\n", fMisc));
-    if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc) == pVM->hm.s.vmx.cPreemptTimerShift)
-        LogRel(("HM:   PREEMPT_TSC_BIT                   = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc)));
+    uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
+    if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
+        LogRel(("HM:   PREEMPT_TIMER_TSC                 = %#x\n",    cPreemptTimerShift));
     else
-        LogRel(("HM:   PREEMPT_TSC_BIT                   = %#x - erratum detected, using %#x instead\n",
-                MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc), pVM->hm.s.vmx.cPreemptTimerShift));
-    LogRel(("HM:   STORE_EFERLMA_VMEXIT              = %RTbool\n", MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(fMisc)));
-    uint8_t const fActivityState = MSR_IA32_VMX_MISC_ACTIVITY_STATES(fMisc);
-    LogRel(("HM:   ACTIVITY_STATES                   = %#x\n",     fActivityState));
-    HMVMX_REPORT_MSR_CAP(fActivityState, "  HLT",       VMX_VMCS_GUEST_ACTIVITY_HLT);
-    HMVMX_REPORT_MSR_CAP(fActivityState, "  SHUTDOWN",  VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN);
-    HMVMX_REPORT_MSR_CAP(fActivityState, "  SIPI_WAIT", VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT);
-    LogRel(("HM:   CR3_TARGET                        = %#x\n",     MSR_IA32_VMX_MISC_CR3_TARGET(fMisc)));
-    LogRel(("HM:   MAX_MSR                           = %u\n",      MSR_IA32_VMX_MISC_MAX_MSR(fMisc)));
-    LogRel(("HM:   RDMSR_SMBASE_MSR_SMM              = %RTbool\n", MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(fMisc)));
-    LogRel(("HM:   SMM_MONITOR_CTL_B2                = %RTbool\n", MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(fMisc)));
-    LogRel(("HM:   VMWRITE_VMEXIT_INFO               = %RTbool\n", MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(fMisc)));
-    LogRel(("HM:   MSEG_ID                           = %#x\n",     MSR_IA32_VMX_MISC_MSEG_ID(fMisc)));
+    {
+        LogRel(("HM:   PREEMPT_TIMER_TSC                 = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
+                pVM->hm.s.vmx.cPreemptTimerShift));
+    }
+    LogRel(("HM:   EXIT_STORE_EFER_LMA               = %RTbool\n",    RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_STORE_EFER_LMA)));
+    LogRel(("HM:   ACTIVITY_STATES                   = %#x%s\n",      RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
+                                                                      hmR3VmxGetActivityStateAllDesc(fMisc)));
+    LogRel(("HM:   PT                                = %RTbool\n",    RT_BF_GET(fMisc, VMX_BF_MISC_PT)));
+    LogRel(("HM:   SMM_READ_SMBASE_MSR               = %RTbool\n",    RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
+    LogRel(("HM:   CR3_TARGET                        = %#x\n",        RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
+    LogRel(("HM:   MAX_MSR                           = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
+                                                                      VMX_MISC_MAX_MSRS(fMisc)));
+    LogRel(("HM:   VMXOFF_BLOCK_SMI                  = %RTbool\n",    RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
+    LogRel(("HM:   VMWRITE_ALL                       = %RTbool\n",    RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
+    LogRel(("HM:   ENTRY_INJECT_SOFT_INT             = %#x\n",        RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
+    LogRel(("HM:   MSEG_ID                           = %#x\n",        RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
 }
 
@@ -1590,7 +1619,6 @@
 static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
 {
-    uint64_t const val = uVmcsEnum;
-    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM            = %#RX64\n", val));
-    LogRel(("HM:   HIGHEST_INDEX                     = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
+    LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM            = %#RX64\n", uVmcsEnum));
+    LogRel(("HM:   HIGHEST_IDX                       = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
 }
 
@@ -1601,8 +1629,8 @@
  * @param   uVmFunc    The VMX VMFUNC MSR value.
  */
-static void hmR3VmxReportVmfuncMsr(uint64_t uVmFunc)
+static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
 {
     LogRel(("HM: MSR_IA32_VMX_VMFUNC               = %#RX64\n", uVmFunc));
-    HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
+    HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
 }
 
@@ -1646,5 +1674,5 @@
     hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
     hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
-    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+    if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
         hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
 
@@ -1652,8 +1680,7 @@
     hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
 
-    if (MSR_IA32_VMX_BASIC_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64Basic))
-    {
-        /* We don't do extensive dumping of the true capability MSRs as we don't use them yet. */
-        /** @todo Consider using true capability MSRs and dumping them extensively. */
+    if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
+    {
+        /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
         LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS   = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
         LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS  = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
@@ -1666,6 +1693,6 @@
     if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
         hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
-    if (pVM->hm.s.vmx.Msrs.u64Vmfunc)
-        hmR3VmxReportVmfuncMsr(pVM->hm.s.vmx.Msrs.u64Vmfunc);
+    if (pVM->hm.s.vmx.Msrs.u64VmFunc)
+        hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
     hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
 
@@ -1681,8 +1708,8 @@
      */
     AssertLogRelReturn(   !pVM->hm.s.fNestedPaging
-                       || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
+                       || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
                        VERR_HM_IPE_1);
     AssertLogRelReturn(   !pVM->hm.s.vmx.fUnrestrictedGuest
-                       || (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
+                       || (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
                            && pVM->hm.s.fNestedPaging),
                        VERR_HM_IPE_1);
@@ -1691,5 +1718,5 @@
      * Enable VPID if configured and supported.
      */
-    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
+    if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
         pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
 
@@ -1698,6 +1725,6 @@
      * Enable APIC register virtualization and virtual-interrupt delivery if supported.
      */
-    if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
-        && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
+    if (   (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
+        && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
         pVM->hm.s.fVirtApicRegs = true;
 
@@ -1707,6 +1734,6 @@
     /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
      *        here. */
-    if (   (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1  & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
-        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
+    if (   (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1  & VMX_PIN_CTLS_POSTED_INT)
+        && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
         pVM->hm.s.fPostedIntrs = true;
 #endif
@@ -1717,5 +1744,5 @@
      * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
      */
-    if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
+    if (   !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
         && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
     {
@@ -3413,84 +3440,84 @@
                     {
                         uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT     );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI  );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR  );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT     );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI     );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT   );
                     }
                     LogRel(("HM: CPU[%u] ProcCtls         %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
                     {
                         uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT       );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT        );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT        );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT        );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT     );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT     );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT       );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT      );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT        );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT          );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT        );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT        );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT        );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT     );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT     );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT      );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT        );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
                     }
                     LogRel(("HM: CPU[%u] ProcCtls2        %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
                     {
                         uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC            );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT                  );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP               );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VPID                 );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT        );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT      );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID              );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC               );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING       );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT           );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PML                  );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE               );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT      );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS       );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING          );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS  );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT               );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP            );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_ACCESS);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID              );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT     );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID           );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC            );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT        );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML               );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE            );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_FROM_PT   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS    );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING       );
                     }
                     LogRel(("HM: CPU[%u] EntryCtls        %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
                     {
                         uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG         );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM          );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG         );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST   );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR      );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR       );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR      );
                     }
                     LogRel(("HM: CPU[%u] ExitCtls         %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
                     {
                         uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG            );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE  );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR         );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT           );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR     );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR   );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR    );
-                        HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG            );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE  );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR         );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT           );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR          );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR          );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR         );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR         );
+                        HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_VMX_PREEMPT_TIMER);
                     }
                     LogRel(("HM: CPU[%u] HCPhysMsrBitmap  %#RHp\n",  i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
Index: /trunk/src/VBox/VMM/include/CPUMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/CPUMInternal.h	(revision 73388)
+++ /trunk/src/VBox/VMM/include/CPUMInternal.h	(revision 73389)
@@ -441,5 +441,5 @@
 #ifndef VBOX_FOR_DTRACE_LIB
 AssertCompileMemberOffset(CPUM, HostFeatures, 64);
-AssertCompileMemberOffset(CPUM, GuestFeatures, 96);
+AssertCompileMemberOffset(CPUM, GuestFeatures, 104);
 #endif
 /** Pointer to the CPUM instance data residing in the shared VM structure. */
Index: /trunk/src/VBox/VMM/include/CPUMInternal.mac
===================================================================
--- /trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 73388)
+++ /trunk/src/VBox/VMM/include/CPUMInternal.mac	(revision 73389)
@@ -97,6 +97,6 @@
 
     alignb 64
-    .HostFeatures               resb    32
-    .GuestFeatures              resb    32
+    .HostFeatures               resb    40
+    .GuestFeatures              resb    40
     .GuestInfo                  resb    RTHCPTR_CB*4 + RTRCPTR_CB*2 + 4*12
 
Index: /trunk/src/VBox/VMM/include/HMInternal.h
===================================================================
--- /trunk/src/VBox/VMM/include/HMInternal.h	(revision 73388)
+++ /trunk/src/VBox/VMM/include/HMInternal.h	(revision 73389)
@@ -726,14 +726,14 @@
         uint32_t                    u32Alignment0;
 #endif
-        /** Current VMX_VMCS32_CTRL_PIN_EXEC. */
+        /** Current pin-based VM-execution controls. */
         uint32_t                    u32PinCtls;
-        /** Current VMX_VMCS32_CTRL_PROC_EXEC. */
+        /** Current processor-based VM-execution controls. */
         uint32_t                    u32ProcCtls;
-        /** Current VMX_VMCS32_CTRL_PROC_EXEC2. */
+        /** Current secondary processor-based VM-execution controls. */
         uint32_t                    u32ProcCtls2;
-        /** Current VMX_VMCS32_CTRL_EXIT. */
+        /** Current VM-entry controls. */
+        uint32_t                    u32EntryCtls;
+        /** Current VM-exit controls. */
         uint32_t                    u32ExitCtls;
-        /** Current VMX_VMCS32_CTRL_ENTRY. */
-        uint32_t                    u32EntryCtls;
 
         /** Current CR0 mask. */
@@ -823,5 +823,5 @@
             X86DESCATTR             AttrSS;
             X86EFLAGS               Eflags;
-            uint32_t                fRealOnV86Active;
+            bool                    fRealOnV86Active;
         } RealMode;
 
