Changeset 73431 in vbox for trunk/include/VBox

Timestamp:

Aug 1, 2018 2:56:26 PM (7 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

124055

Message:

VMM: Nested VMX: bugref:9180 Don't forget to report the VMCS size in IA32_VMX_BASIC MSR, nits.

File:

• trunk/include/VBox/vmm/hm_vmx.h (modified) (7 diffs)

trunk/include/VBox/vmm/hm_vmx.h

@@ -1113 +1113 @@
 #define VMX_BF_BASIC_VMCS_ID_SHIFT                              0
 #define VMX_BF_BASIC_VMCS_ID_MASK                               UINT64_C(0x000000007fffffff)
-/** Bit 32 is reserved as RAZ. */
+/** Bit 31 is reserved and RAZ. */
 #define VMX_BF_BASIC_RSVD_32_SHIFT                              31
 #define VMX_BF_BASIC_RSVD_32_MASK                               UINT64_C(0x0000000080000000)
@@ -1171 +1171 @@
 #define VMX_BF_MISC_ACTIVITY_STATES_SHIFT                       6
 #define VMX_BF_MISC_ACTIVITY_STATES_MASK                        UINT64_C(0x00000000000001c0)
-/** Bits 9:13 is reserved, RAZ. */
+/** Bits 9:13 is reserved and RAZ. */
 #define VMX_BF_MISC_RSVD_9_13_SHIFT                             9
 #define VMX_BF_MISC_RSVD_9_13_MASK                              UINT64_C(0x0000000000003e00)
@@ -1198 +1198 @@
 #define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT                 30
 #define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK                  UINT64_C(0x0000000040000000)
-/** Bit 31 is reserved, RAZ. */
+/** Bit 31 is reserved and RAZ. */
 #define VMX_BF_MISC_RSVD_31_SHIFT                               31
 #define VMX_BF_MISC_RSVD_31_MASK                                UINT64_C(0x0000000080000000)
@@ -1214 +1214 @@
  * @{
  */
-/** Bit 0 is reserved, RAZ.  */
+/** Bit 0 is reserved and RAZ.  */
 #define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT                           0
 #define VMX_BF_VMCS_ENUM_RSVD_0_MASK                            UINT64_C(0x0000000000000001)
@@ -1220 +1220 @@
 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT                      1
 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK                       UINT64_C(0x00000000000003fe)
-/** Bit 10:63 is reserved, RAZ.  */
+/** Bit 10:63 is reserved and RAZ.  */
 #define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT                       10
 #define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK                        UINT64_C(0xfffffffffffffc00)
@@ -1235 +1235 @@
 #define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT                      0
 #define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK                       UINT64_C(0x0000000000000001)
-/** Bits 1:63 are reserved, RAZ. */
+/** Bits 1:63 are reserved and RAZ. */
 #define VMX_BF_VMFUNC_RSVD_1_63_SHIFT                           1
 #define VMX_BF_VMFUNC_RSVD_1_63_MASK                            UINT64_C(0xfffffffffffffffe)
@@ -2353 +2353 @@
 AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
 
+/** The size of the virtual VMCS region (we use the maximum allowed size to avoid
+ *  complications when teleporation may be implemented). */
+#define VMX_V_VMCS_SIZE                                         X86_PAGE_4K_SIZE
+
 /** The highest index value used for supported virtual VMCS field encoding. */
 #define VMX_V_VMCS_MAX_INDEX                                    RT_BF_GET(VMX_VMCS32_PREEMPT_TIMER_VALUE, VMX_BF_VMCS_ENC_INDEX)
+
+/** Whether physical addresses of VMXON and VMCS related structures (I/O bitmap
+ *  etc.) are limited to 32-bits (4G). Always 0 on 64-bit CPUs. */
+#define VMX_V_VMCS_PHYSADDR_4G_LIMIT                            0
 
 /**