Changeset 7358 in vbox
- Timestamp:
- Mar 7, 2008 1:13:17 PM (17 years ago)
- svn:sync-xref-src-repo-rev:
- 28781
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r7321 r7358 71 71 #define PCNET_GC_ENABLED 72 72 73 #if 074 #define LOG_REGISTER(a) LogRel(a)75 #else76 #define LOG_REGISTER(a)77 #endif78 #if 079 #define LOG_PACKET(name, buf, count) LogPkt(name, buf, count)80 #define LOG_PACKETS81 #else82 #define LOG_PACKET(name, buf, count)83 #undef LOG_PACKETS84 #endif85 86 73 #if defined(LOG_ENABLED) 87 74 #define PCNET_DEBUG_IO … … 105 92 /* Maximum number of times we report a link down to the guest (failure to send frame) */ 106 93 #define PCNET_MAX_LINKDOWN_REPORTED 3 94 95 #define MAX_FRAME 1536 107 96 108 97 /* Frame cache */ … … 250 239 uint32_t u32LinkSpeed; 251 240 252 / * #define PCNET_QUEUE_SEND_PACKETS */241 //#define PCNET_QUEUE_SEND_PACKETS 253 242 #ifdef PCNET_QUEUE_SEND_PACKETS 254 243 #define PCNET_MAX_XMIT_SLOTS 128 … … 263 252 STAMCOUNTER StatReceiveBytes; 264 253 STAMCOUNTER StatTransmitBytes; 265 266 254 #ifdef VBOX_WITH_STATISTICS 267 255 STAMPROFILEADV StatMMIOReadGC; … … 309 297 }; 310 298 311 #define PCNETSTATE_2_DEVINS(pPCNet) ( (pPCNet)->CTXSUFF(pDevIns) ) 312 #define PCIDEV_2_PCNETSTATE(pPciDev) ( (PCNetState *)(pPciDev) ) 299 #define PCNETSTATE_2_DEVINS(pPCNet) ((pPCNet)->CTXSUFF(pDevIns)) 300 #define PCIDEV_2_PCNETSTATE(pPciDev) ((PCNetState *)(pPciDev)) 301 #define PCNET_INST_NR (PCNETSTATE_2_DEVINS(pData)->iInstance) 313 302 314 303 /* BUS CONFIGURATION REGISTERS */ … … 812 801 }; 813 802 #pragma pack() 814 815 #ifdef LOG_PACKETS816 static void LogPkt(const char *name, const void *const src, int count)817 {818 int i, j;819 const uint8_t * const p = (const uint8_t * const)src;820 LogRel(("%s: ", name));821 i = 14; // length of MAC header822 i += 4*(p[i] & 15); // length of IP header823 i += 4*(p[i+12] >> 4); // length of TCP header824 for (j=i; j<70 && j<count; j++)825 LogRel((" %02x", p[j]));826 LogRel((" ("));827 for (j=i; j<70 && j<count; j++)828 LogRel(("%c", p[j] >= 32 && p[j] < 127 ? p[j] : '.'));829 LogRel((")\n"));830 }831 #endif832 803 833 804 #define PRINT_PKTHDR(BUF) do { \ … … 961 932 #ifdef PCNET_DEBUG_MATCH 962 933 Log(("#%d packet dhost=%02x:%02x:%02x:%02x:%02x:%02x, " 963 "padr=%02x:%02x:%02x:%02x:%02x:%02x\n", 964 PCNETSTATE_2_DEVINS(pData)->iInstance, 934 "padr=%02x:%02x:%02x:%02x:%02x:%02x => %d\n", PCNET_INST_NR, 965 935 hdr->ether_dhost[0],hdr->ether_dhost[1],hdr->ether_dhost[2], 966 936 hdr->ether_dhost[3],hdr->ether_dhost[4],hdr->ether_dhost[5], 967 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5])); 968 Log(("padr_match result=%d\n", result)); 937 padr[0],padr[1],padr[2],padr[3],padr[4],padr[5], result)); 969 938 #endif 970 939 return result; … … 977 946 int result = !CSR_DRCVBC(pData) && !memcmp(hdr->ether_dhost, aBCAST, 6); 978 947 #ifdef PCNET_DEBUG_MATCH 979 Log(("#%d padr_bcast result=%d\n", PCNET STATE_2_DEVINS(pData)->iInstance, result));948 Log(("#%d padr_bcast result=%d\n", PCNET_INST_NR, result)); 980 949 #endif 981 950 return result; … … 1076 1045 PCNetState *pData = (PCNetState *)pvUser; 1077 1046 1078 Log(("#%d pcnetHandleRingWriteGC: write to %#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance, GCPhysFault));1047 Log(("#%d pcnetHandleRingWriteGC: write to %#010x\n", PCNET_INST_NR, GCPhysFault)); 1079 1048 1080 1049 uint32_t cb; … … 1137 1106 PCNetState *pData = PDMINS2DATA(pDevIns, PCNetState *); 1138 1107 1139 Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance, GCPhys));1108 Log(("#%d pcnetHandleRingWrite: write to %#010x\n", PCNET_INST_NR, GCPhys)); 1140 1109 #ifdef VBOX_WITH_STATISTICS 1141 1110 STAM_COUNTER_INC(&CTXSUFF(pData->StatRingWrite)); … … 1172 1141 static void pcnetSoftReset(PCNetState *pData) 1173 1142 { 1174 Log(("#%d pcnetSoftReset:\n", PCNET STATE_2_DEVINS(pData)->iInstance));1143 Log(("#%d pcnetSoftReset:\n", PCNET_INST_NR)); 1175 1144 1176 1145 pData->u32Lnkst = 0x40; … … 1257 1226 pData->aCSR[4] &= ~0x0080; /* clear UINTCMD */ 1258 1227 pData->aCSR[4] |= 0x0040; /* set UINT */ 1259 Log(("#%d user int\n", PCNET STATE_2_DEVINS(pData)->iInstance));1228 Log(("#%d user int\n", PCNET_INST_NR)); 1260 1229 } 1261 1230 if (pData->aCSR[4] & csr0 & 0x0040 /* CSR_INEA */) … … 1271 1240 csr0 |= 0x0080; /* set INTR */ 1272 1241 iISR = 1; 1273 Log(("#%d user int\n", PCNET STATE_2_DEVINS(pData)->iInstance));1242 Log(("#%d user int\n", PCNET_INST_NR)); 1274 1243 } 1275 1244 #endif /* !VBOX */ … … 1291 1260 pData->aCSR[0] = csr0; 1292 1261 1293 Log2(("#%d set irq iISR=%d\n", PCNET STATE_2_DEVINS(pData)->iInstance, iISR));1262 Log2(("#%d set irq iISR=%d\n", PCNET_INST_NR, iISR)); 1294 1263 1295 1264 /* normal path is to _not_ change the IRQ status */ 1296 1265 if (RT_UNLIKELY(iISR != pData->iISR)) 1297 1266 { 1298 Log(("#%d INTA=%d\n", PCNET STATE_2_DEVINS(pData)->iInstance, iISR));1267 Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR)); 1299 1268 PDMDevHlpPCISetIrqNoWait(PCNETSTATE_2_DEVINS(pData), 0, iISR); 1300 1269 pData->iISR = iISR; … … 1396 1365 { 1397 1366 PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pData); 1398 Log(("#%d pcnetInit: init_addr=%#010x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 1399 PHYSADDR(pData, CSR_IADR(pData)))); 1367 Log(("#%d pcnetInit: init_addr=%#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_IADR(pData)))); 1400 1368 1401 1369 /** @todo Documentation says that RCVRL and XMTRL are stored as two's complement! … … 1425 1393 PCNET_INIT(); 1426 1394 Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n", 1427 PCNET STATE_2_DEVINS(pData)->iInstance, initblk.rlen, initblk.tlen));1395 PCNET_INST_NR, initblk.rlen, initblk.tlen)); 1428 1396 } 1429 1397 else … … 1433 1401 PCNET_INIT(); 1434 1402 Log(("#%d initblk.rlen=%#04x, initblk.tlen=%#04x\n", 1435 PCNET STATE_2_DEVINS(pData)->iInstance, initblk.rlen, initblk.tlen));1403 PCNET_INST_NR, initblk.rlen, initblk.tlen)); 1436 1404 } 1437 1405 … … 1453 1421 1454 1422 LogRel(("PCNet#%d: Init: ss32=%d GCRDRA=%#010x[%d] GCTDRA=%#010x[%d]\n", 1455 PCNET STATE_2_DEVINS(pData)->iInstance, BCR_SSIZE32(pData),1423 PCNET_INST_NR, BCR_SSIZE32(pData), 1456 1424 pData->GCRDRA, CSR_RCVRL(pData), pData->GCTDRA, CSR_XMTRL(pData))); 1457 1425 … … 1466 1434 static void pcnetStart(PCNetState *pData) 1467 1435 { 1468 Log(("#%d pcnetStart:\n", PCNET STATE_2_DEVINS(pData)->iInstance));1436 Log(("#%d pcnetStart:\n", PCNET_INST_NR)); 1469 1437 if (!CSR_DTX(pData)) 1470 1438 pData->aCSR[0] |= 0x0010; /* set TXON */ … … 1480 1448 static void pcnetStop(PCNetState *pData) 1481 1449 { 1482 Log(("#%d pcnetStop:\n", PCNET STATE_2_DEVINS(pData)->iInstance));1450 Log(("#%d pcnetStop:\n", PCNET_INST_NR)); 1483 1451 pData->aCSR[0] &= ~0x7feb; 1484 1452 pData->aCSR[0] |= 0x0014; … … 1553 1521 /* This is not problematic since we don't own the descriptor */ 1554 1522 LogRel(("PCNet#%d: BAD RMD ENTRIES AT %#010x (i=%d)\n", 1555 PCNET STATE_2_DEVINS(pData)->iInstance, addr, i));1523 PCNET_INST_NR, addr, i)); 1556 1524 return; 1557 1525 } … … 1583 1551 /* This is not problematic since we don't own the descriptor */ 1584 1552 LogRel(("PCNet#%d: BAD RMD ENTRIES + AT %#010x (i=%d)\n", 1585 PCNET STATE_2_DEVINS(pData)->iInstance, addr, i));1553 PCNET_INST_NR, addr, i)); 1586 1554 return; 1587 1555 } … … 1620 1588 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatTdtePoll), a); 1621 1589 LogRel(("PCNet#%d: BAD TMD XDA=%#010x\n", 1622 PCNET STATE_2_DEVINS(pData)->iInstance, PHYSADDR(pData, cxda)));1590 PCNET_INST_NR, PHYSADDR(pData, cxda))); 1623 1591 return 0; 1624 1592 } … … 1668 1636 1669 1637 /* byte count stored in two's complement 12 bits wide */ 1670 Log(("#%d pcnetCanReceiveNoSync %d bytes\n", PCNET STATE_2_DEVINS(pData)->iInstance,1638 Log(("#%d pcnetCanReceiveNoSync %d bytes\n", PCNET_INST_NR, 1671 1639 4096 - CSR_CRBC(pData))); 1672 1640 return 4096 - CSR_CRBC(pData); … … 1686 1654 return; 1687 1655 1688 Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNETSTATE_2_DEVINS(pData)->iInstance, size)); 1689 1690 LOG_PACKET("rraw", buf, size); 1656 Log(("#%d pcnetReceiveNoSync: size=%d\n", PCNET_INST_NR, size)); 1691 1657 1692 1658 /* … … 1705 1671 * we already called pcnetCanReceive(). */ 1706 1672 LogRel(("PCNet#%d: no buffer: RCVRC=%d\n", 1707 PCNET STATE_2_DEVINS(pData)->iInstance, CSR_RCVRC(pData)));1673 PCNET_INST_NR, CSR_RCVRC(pData))); 1708 1674 /* Dump the status of all RX descriptors */ 1709 1675 const unsigned cb = 1 << pData->iLog2DescSize; … … 1803 1769 { 1804 1770 LogRel(("PCNet#%d: Overflow by %ubytes\n", 1805 PCNET STATE_2_DEVINS(pData)->iInstance, size));1771 PCNET_INST_NR, size)); 1806 1772 rmd.rmd1.oflo = 1; 1807 1773 rmd.rmd1.buff = 1; … … 1814 1780 pData->aCSR[0] |= 0x0400; 1815 1781 1816 Log(("#%d RCVRC=%d CRDA=%#010x BLKS=%d\n", PCNET STATE_2_DEVINS(pData)->iInstance,1782 Log(("#%d RCVRC=%d CRDA=%#010x BLKS=%d\n", PCNET_INST_NR, 1817 1783 CSR_RCVRC(pData), PHYSADDR(pData, CSR_CRDA(pData)), pktcount)); 1818 1784 #ifdef PCNET_DEBUG_RMD … … 1952 1918 STAM_PROFILE_ADV_STOP(&pData->StatTransmitSend, a); 1953 1919 1954 return PDMCritSectEnter(&pData->CritSect, VERR_ PERMISSION_DENIED);1920 return PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY); 1955 1921 #endif 1956 1922 } … … 1968 1934 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1; 1969 1935 Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n", 1970 PCNET STATE_2_DEVINS(pData)->iInstance, pData->aBCR[BCR_SWS]));1936 PCNET_INST_NR, pData->aBCR[BCR_SWS])); 1971 1937 } 1972 1938 … … 1981 1947 pData->Led.Asserted.s.fError = pData->Led.Actual.s.fError = 1; 1982 1948 Log(("#%d pcnetTransmit: Signaling send error. swstyle=%#x\n", 1983 PCNET STATE_2_DEVINS(pData)->iInstance, pData->aBCR[BCR_SWS]));1949 PCNET_INST_NR, pData->aBCR[BCR_SWS])); 1984 1950 } 1985 1951 … … 2081 2047 STAM_PROFILE_ADV_STOP(&pData->StatTransmitSend, a); 2082 2048 2083 PDMCritSectEnter(&pData->CritSect, VERR_ PERMISSION_DENIED);2049 PDMCritSectEnter(&pData->CritSect, VERR_SEM_BUSY); 2084 2050 2085 2051 pData->cbXmitRingBuffer[pData->ulXmitRingBufCons] = 0; … … 2124 2090 2125 2091 #ifdef PCNET_DEBUG_TMD 2126 Log2(("#%d TMDLOAD %#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance, PHYSADDR(pData, CSR_CXDA(pData))));2092 Log2(("#%d TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_CXDA(pData)))); 2127 2093 PRINT_TMD(&tmd); 2128 2094 #endif … … 2135 2101 { 2136 2102 const unsigned cb = 4096 - tmd.tmd1.bcnt; 2137 Log(("#%d pcnetTransmit: stp&enp: cb=%d xmtrc=%#x\n", PCNET STATE_2_DEVINS(pData)->iInstance, cb, CSR_XMTRC(pData)));2103 Log(("#%d pcnetTransmit: stp&enp: cb=%d xmtrc=%#x\n", PCNET_INST_NR, cb, CSR_XMTRC(pData))); 2138 2104 2139 2105 if (RT_LIKELY(pcnetIsLinkUp(pData) || CSR_LOOP(pData))) … … 2143 2109 * ENP = 1).'' That means that the first buffer might have a 2144 2110 * zero length if it is not the last one in the chain. */ 2145 if (RT_LIKELY(cb <= 1536))2111 if (RT_LIKELY(cb <= MAX_FRAME)) 2146 2112 { 2147 2113 pcnetXmitRead1st(pData, PHYSADDR(pData, tmd.tmd0.tbadr), cb); … … 2167 2133 * the buffer length of 0 is interpreted as a 4096-byte 2168 2134 * buffer.'' */ 2169 LogRel(("PCN ET: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n"));2135 LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> ignoring\n", PCNET_INST_NR)); 2170 2136 pcnetTmdStorePassHost(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData))); 2171 2137 break; … … 2175 2141 /* Signal error, as this violates the Ethernet specs. */ 2176 2142 /** @todo check if the correct error is generated. */ 2177 LogRel(("PCN ET: pcnetAsyncTransmit: illegal 4kb frame -> signalling error\n"));2143 LogRel(("PCNet#%d: pcnetAsyncTransmit: illegal 4kb frame -> signalling error\n", PCNET_INST_NR)); 2178 2144 2179 2145 pcnetXmitFailTMDGeneric(pData, &tmd); … … 2197 2163 * Read TMDs until end-of-packet or tdte poll fails (underflow). 2198 2164 */ 2199 const unsigned cbMaxFrame = 1536;2200 2165 bool fDropFrame = false; 2201 2166 unsigned cb = 4096 - tmd.tmd1.bcnt; … … 2241 2206 pcnetTmdLoad(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)), false); 2242 2207 cb = 4096 - tmd.tmd1.bcnt; 2243 if ( pData->SendFrame.cb + cb < cbMaxFrame2208 if ( pData->SendFrame.cb + cb < MAX_FRAME 2244 2209 && !fDropFrame) 2245 2210 pcnetXmitReadMore(pData, PHYSADDR(pData, tmd.tmd0.tbadr), cb); … … 2252 2217 if (tmd.tmd1.enp) 2253 2218 { 2254 Log(("#%d pcnetTransmit: stp: cb=%d xmtrc=%#x-%#x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2219 Log(("#%d pcnetTransmit: stp: cb=%d xmtrc=%#x-%#x\n", PCNET_INST_NR, 2255 2220 pData->SendFrame.cb, iStart, CSR_XMTRC(pData))); 2256 2221 if (pcnetIsLinkUp(pData) && !fDropFrame) … … 2287 2252 */ 2288 2253 /** @todo according to the specs we're supposed to clear the own bit and move on to the next one. */ 2289 Log(("#%d pcnetTransmit: guest is giving us shit!\n", PCNET STATE_2_DEVINS(pData)->iInstance));2254 Log(("#%d pcnetTransmit: guest is giving us shit!\n", PCNET_INST_NR)); 2290 2255 break; 2291 2256 } … … 2363 2328 * suspended while waiting for the critical section. 2364 2329 */ 2365 rc = PDMCritSectEnter(&pThis->CritSect, VERR_ PERMISSION_DENIED);2330 rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY); 2366 2331 AssertReleaseRCReturn(rc, rc); 2367 2332 … … 2421 2386 if (CSR_STOP(pData) || CSR_SPND(pData)) 2422 2387 Log2(("#%d pcnetPollTimer time=%#010llx CSR_STOP=%d CSR_SPND=%d\n", 2423 PCNET STATE_2_DEVINS(pData)->iInstance, RTTimeMilliTS(), CSR_STOP(pData), CSR_SPND(pData)));2388 PCNET_INST_NR, RTTimeMilliTS(), CSR_STOP(pData), CSR_SPND(pData))); 2424 2389 else 2425 2390 Log2(("#%d pcnetPollTimer time=%#010llx TDMD=%d TXON=%d POLL=%d TDTE=%d TDRA=%#x\n", 2426 PCNET STATE_2_DEVINS(pData)->iInstance, RTTimeMilliTS(), CSR_TDMD(pData), CSR_TXON(pData),2391 PCNET_INST_NR, RTTimeMilliTS(), CSR_TDMD(pData), CSR_TXON(pData), 2427 2392 !CSR_DPOLL(pData), pcnetTdtePoll(pData, &dummy), pData->GCTDRA)); 2428 2393 Log2(("#%d pcnetPollTimer: CSR_CXDA=%#x CSR_XMTRL=%d CSR_XMTRC=%d\n", 2429 PCNET STATE_2_DEVINS(pData)->iInstance, CSR_CXDA(pData), CSR_XMTRL(pData), CSR_XMTRC(pData)));2394 PCNET_INST_NR, CSR_CXDA(pData), CSR_XMTRL(pData), CSR_XMTRC(pData))); 2430 2395 #endif 2431 2396 #ifdef PCNET_DEBUG_TMD … … 2434 2399 TMD tmd; 2435 2400 pcnetTmdLoad(pData, &tmd, PHYSADDR(pData, CSR_CXDA(pData)), false); 2436 Log2(("#%d pcnetPollTimer: TMDLOAD %#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance, PHYSADDR(pData, CSR_CXDA(pData))));2401 Log2(("#%d pcnetPollTimer: TMDLOAD %#010x\n", PCNET_INST_NR, PHYSADDR(pData, CSR_CXDA(pData)))); 2437 2402 PRINT_TMD(&tmd); 2438 2403 } … … 2476 2441 int rc = VINF_SUCCESS; 2477 2442 #ifdef PCNET_DEBUG_CSR 2478 Log(("#%d pcnetCSRWriteU16: rap=%d val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance, u32RAP, val));2443 Log(("#%d pcnetCSRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val)); 2479 2444 #endif 2480 2445 switch (u32RAP) … … 2493 2458 val &= ~3; 2494 2459 2495 Log(("#%d pcnetWriteCSR0: %#06x => %#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance, pData->aCSR[0], csr0));2460 Log(("#%d pcnetWriteCSR0: %#06x => %#06x\n", PCNET_INST_NR, pData->aCSR[0], csr0)); 2496 2461 2497 2462 #ifndef IN_RING3 2498 2463 if (!(csr0 & 0x0001/*init*/) && (val & 1)) 2499 2464 { 2500 Log(("#%d pcnetCSRWriteU16: pcnetInit requested => HC\n", PCNET STATE_2_DEVINS(pData)->iInstance));2465 Log(("#%d pcnetCSRWriteU16: pcnetInit requested => HC\n", PCNET_INST_NR)); 2501 2466 return VINF_IOM_HC_IOPORT_WRITE; 2502 2467 } 2503 2468 #endif 2504 LOG_REGISTER(("PCNet#%d: WRITE CSR%d, %#06x => %#06x (%#06x)\n",2505 PCNETSTATE_2_DEVINS(pData)->iInstance,2506 u32RAP, new_value, csr0, pData->aCSR[0]));2507 2469 pData->aCSR[0] = csr0; 2508 2470 … … 2563 2525 if (CSR_STOP(pData) || CSR_SPND(pData)) 2564 2526 break; 2565 LOG_REGISTER(("PCNet#%d: WRITE CSR%d, %#06x\n",2566 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2567 return rc;2568 2527 case 3: /* Interrupt Mask and Deferral Control */ 2569 LOG_REGISTER(("PCNet#%d: WRITE CSR%d, %#06x\n",2570 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2571 2528 break; 2572 2529 case 4: /* Test and Features Control */ 2573 LOG_REGISTER(("PCNet#%d: WRITE CSR%d, %#06x\n",2574 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2575 2530 pData->aCSR[4] &= ~(val & 0x026a); 2576 2531 val &= ~0x026a; … … 2578 2533 break; 2579 2534 case 5: /* Extended Control and Interrupt 1 */ 2580 LOG_REGISTER(("PCNet#%d: WRITE CSR%d, %#06x\n",2581 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2582 2535 pData->aCSR[5] &= ~(val & 0x0a90); 2583 2536 val &= ~0x0a90; … … 2596 2549 if ((pData->aCSR[15] & 0x8000) != (val & 0x8000) && pData->pDrv) 2597 2550 { 2598 Log(("PCNet#%d: promiscuous mode changed to %d\n", 2599 PCNETSTATE_2_DEVINS(pData)->iInstance, !!(val & 0x8000))); 2551 Log(("#%d: promiscuous mode changed to %d\n", PCNET_INST_NR, !!(val & 0x8000))); 2600 2552 #ifndef IN_RING3 2601 2553 return VINF_IOM_HC_IOPORT_WRITE; … … 2620 2572 if (!CSR_STOP(pData) && !CSR_SPND(pData)) 2621 2573 { 2622 Log((" PCNet#%d: WRITE CSR%d, %#06x !!\n", PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2574 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val)); 2623 2575 return rc; 2624 2576 } … … 2627 2579 else 2628 2580 pData->GCRDRA = (pData->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); 2629 Log((" PCNet#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2581 Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, 2630 2582 u32RAP, val, pData->GCRDRA)); 2631 2583 break; … … 2639 2591 if (!CSR_STOP(pData) && !CSR_SPND(pData)) 2640 2592 { 2641 Log((" PCNet#%d: WRITE CSR%d, %#06x !!\n", PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2593 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val)); 2642 2594 return rc; 2643 2595 } … … 2646 2598 else 2647 2599 pData->GCTDRA = (pData->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); 2648 Log((" PCNet#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2600 Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, 2649 2601 u32RAP, val, pData->GCTDRA)); 2650 2602 break; 2651 2603 2652 2604 case 58: /* Software Style */ 2653 LOG_REGISTER(("PCNet#%d: WRITE SW_STYLE, %#06x\n",2654 PCNETSTATE_2_DEVINS(pData)->iInstance, val));2655 2605 rc = pcnetBCRWriteU16(pData, BCR_SWS, val); 2656 2606 break; … … 2666 2616 if (!CSR_STOP(pData) && !CSR_SPND(pData)) 2667 2617 { 2668 Log((" PCNet#%d: WRITE CSR%d, %#06x !!\n", PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2618 Log(("#%d: WRITE CSR%d, %#06x !!\n", PCNET_INST_NR, u32RAP, val)); 2669 2619 return rc; 2670 2620 } 2671 Log((" PCNet#%d: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", PCNETSTATE_2_DEVINS(pData)->iInstance,2621 Log(("#%d: WRITE CSR%d, %#06x (hacked %#06x) (alt init)\n", PCNET_INST_NR, 2672 2622 u32RAP, val, 1 + ~(uint16_t)val)); 2673 2623 val = 1 + ~(uint16_t)val; … … 2727 2677 default: 2728 2678 val = pData->aCSR[u32RAP]; 2729 LOG_REGISTER(("PCNet#%d: read CSR%d => %#06x\n",2730 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2731 2679 } 2732 2680 #ifdef PCNET_DEBUG_CSR 2733 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2681 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, 2734 2682 u32RAP, val)); 2735 2683 #endif … … 2742 2690 u32RAP &= 0x7f; 2743 2691 #ifdef PCNET_DEBUG_BCR 2744 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2692 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, 2745 2693 u32RAP, val)); 2746 2694 #endif … … 2754 2702 { 2755 2703 default: 2756 Log((" Bad SWSTYLE=%#04x\n", val & 0xff));2704 Log(("#%d Bad SWSTYLE=%#04x\n", PCNET_INST_NR, val & 0xff)); 2757 2705 // fall through 2758 2706 case 0: … … 2773 2721 break; 2774 2722 } 2775 LOG_REGISTER(("PCNet#%d: WRITE SW_STYLE, %#06x\n", 2776 PCNETSTATE_2_DEVINS(pData)->iInstance, val)); 2777 Log(("BCR_SWS=%#06x\n", val)); 2723 Log(("#%d BCR_SWS=%#06x\n", PCNET_INST_NR, val)); 2778 2724 pData->aCSR[58] = val; 2779 2725 /* fall through */ … … 2789 2735 case BCR_MIICAS: 2790 2736 case BCR_MIIADDR: 2791 LOG_REGISTER(("PCNet#%d: WRITE BCR%d, %#06x\n",2792 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2793 2737 pData->aBCR[u32RAP] = val; 2794 2738 break; … … 2802 2746 2803 2747 case BCR_MIIMDR: 2804 LOG_REGISTER(("PCNet#%d: WRITE MII%d, %#06x\n",2805 PCNETSTATE_2_DEVINS(pData)->iInstance, u32RAP, val));2806 2748 pData->aMII[pData->aBCR[BCR_MIIADDR] & 0x1f] = val; 2807 2749 #ifdef PCNET_DEBUG_MII 2808 Log(("#%d pcnet: mii write %d <- %#x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2750 Log(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, 2809 2751 pData->aBCR[BCR_MIIADDR] & 0x1f, val)); 2810 2752 #endif … … 2926 2868 2927 2869 #ifdef PCNET_DEBUG_MII 2928 Log(("#%d pcnet: mii read %d -> %#x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2870 Log(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, 2929 2871 miiaddr, val)); 2930 2872 #endif … … 2968 2910 } 2969 2911 #ifdef PCNET_DEBUG_BCR 2970 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2912 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, 2971 2913 u32RAP, val)); 2972 2914 #endif … … 3020 2962 addr &= 0x0f; 3021 2963 val &= 0xff; 3022 Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2964 Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3023 2965 addr, val)); 3024 2966 /* Check APROMWE bit to enable write access */ … … 3030 2972 { 3031 2973 uint32_t val = pData->aPROM[addr &= 0x0f]; 3032 Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2974 Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3033 2975 addr, val)); 3034 2976 return val; … … 3040 2982 3041 2983 #ifdef PCNET_DEBUG_IO 3042 Log2(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,2984 Log2(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, 3043 2985 addr, val)); 3044 2986 #endif … … 3061 3003 } 3062 3004 else 3063 Log(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET STATE_2_DEVINS(pData)->iInstance, addr, val));3005 Log(("#%d pcnetIoportWriteU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val)); 3064 3006 3065 3007 return rc; … … 3099 3041 } 3100 3042 else 3101 Log(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET STATE_2_DEVINS(pData)->iInstance, addr, val & 0xffff));3043 Log(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x BCR_DWIO !!\n", PCNET_INST_NR, addr, val & 0xffff)); 3102 3044 3103 3045 pcnetUpdateIrq(pData); … … 3105 3047 skip_update_irq: 3106 3048 #ifdef PCNET_DEBUG_IO 3107 Log2(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x\n", PCNETSTATE_2_DEVINS(pData)->iInstance, 3108 addr, val & 0xffff)); 3049 Log2(("#%d pcnetIoportReadU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val & 0xffff)); 3109 3050 #endif 3110 3051 return val; … … 3116 3057 3117 3058 #ifdef PCNET_DEBUG_IO 3118 Log2(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3059 Log2(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3119 3060 addr, val)); 3120 3061 #endif … … 3145 3086 } 3146 3087 else 3147 Log(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET STATE_2_DEVINS(pData)->iInstance, addr, val));3088 Log(("#%d pcnetIoportWriteU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val)); 3148 3089 3149 3090 return rc; … … 3183 3124 } 3184 3125 else 3185 Log(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET STATE_2_DEVINS(pData)->iInstance, addr, val));3126 Log(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x !BCR_DWIO !!\n", PCNET_INST_NR, addr, val)); 3186 3127 pcnetUpdateIrq(pData); 3187 3128 3188 3129 skip_update_irq: 3189 3130 #ifdef PCNET_DEBUG_IO 3190 Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3131 Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3191 3132 addr, val)); 3192 3133 #endif … … 3197 3138 { 3198 3139 #ifdef PCNET_DEBUG_IO 3199 Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3140 Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3200 3141 addr, val)); 3201 3142 #endif … … 3210 3151 val = pcnetAPROMReadU8(pData, addr); 3211 3152 #ifdef PCNET_DEBUG_IO 3212 Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3153 Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3213 3154 addr, val & 0xff)); 3214 3155 #endif … … 3219 3160 { 3220 3161 #ifdef PCNET_DEBUG_IO 3221 Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3162 Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, 3222 3163 addr, val)); 3223 3164 #endif … … 3245 3186 } 3246 3187 #ifdef PCNET_DEBUG_IO 3247 Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3188 Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, 3248 3189 addr, val & 0xffff)); 3249 3190 #endif … … 3254 3195 { 3255 3196 #ifdef PCNET_DEBUG_IO 3256 Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3197 Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3257 3198 addr, val)); 3258 3199 #endif … … 3286 3227 } 3287 3228 #ifdef PCNET_DEBUG_IO 3288 Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET STATE_2_DEVINS(pData)->iInstance,3229 Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3289 3230 addr, val)); 3290 3231 #endif … … 3328 3269 else 3329 3270 { 3330 Log(("#%d pcnetIOPortAPromRead: Port=%RTiop cb=%d BCR_DWIO !!\n", PCNET STATE_2_DEVINS(pData)->iInstance, Port, cb));3271 Log(("#%d pcnetIOPortAPromRead: Port=%RTiop cb=%d BCR_DWIO !!\n", PCNET_INST_NR, Port, cb)); 3331 3272 rc = VERR_IOM_IOPORT_UNUSED; 3332 3273 } … … 3335 3276 STAM_PROFILE_ADV_STOP(&pData->StatAPROMRead, a); 3336 3277 LogFlow(("#%d pcnetIOPortAPromRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", 3337 PCNET STATE_2_DEVINS(pData)->iInstance, Port, *pu32, cb, rc));3278 PCNET_INST_NR, Port, *pu32, cb, rc)); 3338 3279 return rc; 3339 3280 } … … 3361 3302 STAM_PROFILE_ADV_START(&pData->StatAPROMWrite, a); 3362 3303 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE); 3363 if ( rc == VINF_SUCCESS)3304 if (RT_LIKELY(rc == VINF_SUCCESS)) 3364 3305 { 3365 3306 pcnetAPROMWriteU8(pData, Port, u32); … … 3374 3315 } 3375 3316 LogFlow(("#%d pcnetIOPortAPromWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", 3376 PCNETSTATE_2_DEVINS(pData)->iInstance, Port, u32, cb, rc)); 3317 PCNET_INST_NR, Port, u32, cb, rc)); 3318 #ifdef LOG_ENABLED 3319 if (rc == VINF_IOM_HC_IOPORT_WRITE) 3320 LogFlow(("#%d => HC\n", PCNET_INST_NR)); 3321 #endif 3377 3322 return rc; 3378 3323 } … … 3398 3343 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatIORead), a); 3399 3344 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_READ); 3400 if ( rc == VINF_SUCCESS)3345 if (RT_LIKELY(rc == VINF_SUCCESS)) 3401 3346 { 3402 3347 switch (cb) … … 3412 3357 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIORead), a); 3413 3358 LogFlow(("#%d pcnetIOPortRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", 3414 PCNETSTATE_2_DEVINS(pData)->iInstance, Port, *pu32, cb, rc)); 3359 PCNET_INST_NR, Port, *pu32, cb, rc)); 3360 #ifdef LOG_ENABLED 3361 if (rc == VINF_IOM_HC_IOPORT_READ) 3362 LogFlow(("#%d => HC\n", PCNET_INST_NR)); 3363 #endif 3415 3364 return rc; 3416 3365 } … … 3436 3385 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatIOWrite), a); 3437 3386 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_IOPORT_WRITE); 3438 if ( rc == VINF_SUCCESS)3387 if (RT_LIKELY(rc == VINF_SUCCESS)) 3439 3388 { 3440 3389 switch (cb) … … 3451 3400 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIOWrite), a); 3452 3401 LogFlow(("#%d pcnetIOPortWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", 3453 PCNETSTATE_2_DEVINS(pData)->iInstance, Port, u32, cb, rc)); 3402 PCNET_INST_NR, Port, u32, cb, rc)); 3403 #ifdef LOG_ENABLED 3404 if (rc == VINF_IOM_HC_IOPORT_WRITE) 3405 LogFlow(("#%d => HC\n", PCNET_INST_NR)); 3406 #endif 3454 3407 return rc; 3455 3408 } … … 3480 3433 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatMMIORead), a); 3481 3434 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_MMIO_READ); 3482 if ( rc == VINF_SUCCESS)3435 if (RT_LIKELY(rc == VINF_SUCCESS)) 3483 3436 { 3484 3437 switch (cb) … … 3500 3453 3501 3454 LogFlow(("#%d pcnetMMIORead: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Vrc\n", 3502 PCNETSTATE_2_DEVINS(pData)->iInstance, pv, cb, pv, cb, GCPhysAddr, rc)); 3455 PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc)); 3456 #ifdef LOG_ENABLED 3457 if (rc == VINF_IOM_HC_MMIO_READ) 3458 LogFlow(("#%d => HC\n", PCNET_INST_NR)); 3459 #endif 3503 3460 return rc; 3504 3461 } … … 3529 3486 STAM_PROFILE_ADV_START(&pData->CTXSUFF(StatMMIOWrite), a); 3530 3487 rc = PDMCritSectEnter(&pData->CritSect, VINF_IOM_HC_MMIO_WRITE); 3531 if ( rc == VINF_SUCCESS)3488 if (RT_LIKELY(rc == VINF_SUCCESS)) 3532 3489 { 3533 3490 switch (cb) … … 3548 3505 } 3549 3506 LogFlow(("#%d pcnetMMIOWrite: pvUser=%p:{%.*Rhxs} cb=%d GCPhysAddr=%RGp rc=%Vrc\n", 3550 PCNETSTATE_2_DEVINS(pData)->iInstance, pv, cb, pv, cb, GCPhysAddr, rc)); 3507 PCNET_INST_NR, pv, cb, pv, cb, GCPhysAddr, rc)); 3508 #ifdef LOG_ENABLED 3509 if (rc == VINF_IOM_HC_MMIO_WRITE) 3510 LogFlow(("#%d => HC\n", PCNET_INST_NR)); 3511 #endif 3551 3512 return rc; 3552 3513 } … … 4424 4385 rc = CFGMR3QueryU32(pCfgHandle, "LineSpeed", &pData->u32LinkSpeed); 4425 4386 if (rc == VERR_CFGM_VALUE_NOT_FOUND) 4426 pData->u32LinkSpeed = 100000 ; /* 100 Mbps (in kbps units)*/4387 pData->u32LinkSpeed = 1000000; /* 1GBit/s (in kbps units)*/ 4427 4388 else if (VBOX_FAILURE(rc)) 4428 4389 return PDMDEV_SET_ERROR(pDevIns, rc, … … 4659 4620 pData->ulXmitRingBufProd = 0; 4660 4621 pData->ulXmitRingBufCons = 0; 4661 pData->pXmitRingBuffer[0] = (char *)RTMemAlloc(PCNET_MAX_XMIT_SLOTS * 1536);4622 pData->pXmitRingBuffer[0] = (char *)RTMemAlloc(PCNET_MAX_XMIT_SLOTS * MAX_FRAME); 4662 4623 pData->cbXmitRingBuffer[0] = 0; 4663 4624 for (i = 1; i < PCNET_MAX_XMIT_SLOTS; i++) 4664 4625 { 4665 pData->pXmitRingBuffer[i] = pData->pXmitRingBuffer[i-1] + 1536;4626 pData->pXmitRingBuffer[i] = pData->pXmitRingBuffer[i-1] + MAX_FRAME; 4666 4627 pData->cbXmitRingBuffer[i] = 0; 4667 4628 } … … 4698 4659 4699 4660 for (i = 0; i < ELEMENTS(pData->aStatXmitFlush) - 1; i++) 4700 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "","/Devices/PCNet%d/XmitFlushIrq/%d", iInstance, i + 1);4701 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "","/Devices/PCNet%d/XmitFlushIrq/%d+", iInstance, i + 1);4661 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d", iInstance, i + 1); 4662 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitFlush[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitFlushIrq/%d+", iInstance, i + 1); 4702 4663 4703 4664 for (i = 0; i < ELEMENTS(pData->aStatXmitChainCounts) - 1; i++) 4704 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "","/Devices/PCNet%d/XmitChainCounts/%d", iInstance, i + 1);4705 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d+", iInstance, i + 1);4706 4707 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitSkipCurrent, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "","/Devices/PCNet%d/Xmit/Skipped", iInstance, i + 1);4665 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d", iInstance, i + 1); 4666 PDMDevHlpSTAMRegisterF(pDevIns, &pData->aStatXmitChainCounts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/XmitChainCounts/%d+", iInstance, i + 1); 4667 4668 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatXmitSkipCurrent, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "", "/Devices/PCNet%d/Xmit/Skipped", iInstance, i + 1); 4708 4669 4709 4670 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatInterrupt, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, "Profiling PCNet interrupt checks", "/Devices/PCNet%d/UpdateIRQ", iInstance); … … 4716 4677 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/R0/Writes", iInstance); 4717 4678 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored ring page writes", "/Devices/PCNet%d/Ring/GC/Writes", iInstance); 4718 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/HC/Failed", iInstance);4719 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/R0/Failed", iInstance);4720 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/GC/Failed", iInstance);4721 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range","/Devices/PCNet%d/Ring/HC/Outside", iInstance);4722 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range","/Devices/PCNet%d/Ring/R0/Outside", iInstance);4723 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range","/Devices/PCNet%d/Ring/GC/Outside", iInstance);4679 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/HC/Failed", iInstance); 4680 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/R0/Failed", iInstance); 4681 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteFailedGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of failed ring page writes", "/Devices/PCNet%d/Ring/GC/Failed", iInstance); 4682 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeHC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range", "/Devices/PCNet%d/Ring/HC/Outside", iInstance); 4683 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeR0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range", "/Devices/PCNet%d/Ring/R0/Outside", iInstance); 4684 PDMDevHlpSTAMRegisterF(pDevIns, &pData->StatRingWriteOutsideRangeGC, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Nr of monitored writes outside ring range", "/Devices/PCNet%d/Ring/GC/Outside", iInstance); 4724 4685 # endif /* PCNET_NO_POLLING */ 4725 4686 #endif
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