VirtualBox

Changeset 73606 in vbox for trunk/include/VBox


Ignore:
Timestamp:
Aug 10, 2018 7:38:56 AM (6 years ago)
Author:
vboxsync
Message:

VMM: Nested VMX: bugref:9180 Various bits:

  • IEM: Started VMXON, VMXOFF implementation, use IEM_OPCODE_GET_NEXT_RM.
  • IEM: Fixed INVPCID C impl, removed unused IEMExecDecodedInvpcid.
  • IEM: Updated iemCImpl_load_CrX to check for CR0/CR4 fixed bits in VMX.
  • IEM: Update offModRm to reset/re-initialize where needed.
  • CPUM: Added VMX root, non-root mode and other bits and updated a few places where they're used.
  • HM: Started adding fine-grained VMX instruction failure diagnostics.
  • HM: Made VM instruction error an enum.
  • HM: Added HMVMXAll.cpp for all context VMX code.
  • Ensure building with VBOX_WITH_NESTED_HWVIRT_[SVM|VMX] does the right thing based on host CPU.
  • CPUM: Added dumping of nested-VMX CPUMCTX state.
  • HMVMXR0: Added memory operand decoding.
  • HMVMXR0: VMX instr. privilege checks (CR0/CR4 read shadows are not consulted, so we need to do them)
  • HM: Added some more bit-field representaions.
  • Recompiler: Refuse to run when in nested-VMX guest code.
Location:
trunk/include/VBox/vmm
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum.h

    r73443 r73606  
    13021302VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32MtrrCap(PVMCPU pVCpu);
    13031303VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32FeatureControl(PVMCPU pVCpu);
     1304VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32VmxBasic(PVMCPU pVCpu);
     1305VMM_INT_DECL(uint64_t)  CPUMGetGuestIa32SmmMonitorCtl(PVMCPU pVCpu);
    13041306VMMDECL(VBOXSTRICTRC)   CPUMQueryGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *puValue);
    13051307VMMDECL(VBOXSTRICTRC)   CPUMSetGuestMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t uValue);
    … …  
    17881790
    17891791/**
    1790  * Checks if we are executing inside a VMX nested hardware-virtualized guest.
    1791  *
    1792  * @returns @c true if in VMX nested-guest mode, @c false otherwise.
    1793  * @param   pCtx        Pointer to the context.
    1794  */
    1795 DECLINLINE(bool) CPUMIsGuestInVmxNestedHwVirtMode(PCCPUMCTX pCtx)
    1796 {
    1797     /** @todo Intel. */
     1792 * Checks if the guest is in VMX non-root operation.
     1793 *
     1794 * @returns @c true if in VMX non-root operation, @c false otherwise.
     1795 * @param   pCtx    Current CPU context.
     1796 */
     1797DECLINLINE(bool) CPUMIsGuestInVmxNonRootMode(PCCPUMCTX pCtx)
     1798{
     1799#ifndef IN_RC
     1800    Assert(!pCtx->hwvirt.vmx.fInVmxNonRootMode || pCtx->hwvirt.vmx.fInVmxRootMode);
     1801    return pCtx->hwvirt.vmx.fInVmxNonRootMode;
     1802#else
    17981803    NOREF(pCtx);
    17991804    return false;
    1800 }
    1801 
    1802 /**
    1803  * Checks if we are executing inside a nested hardware-virtualized guest.
    1804  *
    1805  * @returns @c true if in SVM/VMX nested-guest mode, @c false otherwise.
    1806  * @param   pCtx        Pointer to the context.
    1807  */
    1808 DECLINLINE(bool) CPUMIsGuestInNestedHwVirtMode(PCCPUMCTX pCtx)
    1809 {
    1810     return CPUMIsGuestInSvmNestedHwVirtMode(pCtx) || CPUMIsGuestInVmxNestedHwVirtMode(pCtx);
    1811 }
     1805#endif
     1806}
     1807
     1808/**
     1809 * Checks if the guest is in VMX root operation.
     1810 *
     1811 * @returns @c true if in VMX root operation, @c false otherwise.
     1812 * @param   pCtx    Current CPU context.
     1813 */
     1814DECLINLINE(bool) CPUMIsGuestInVmxRootMode(PCCPUMCTX pCtx)
     1815{
     1816#ifndef IN_RC
     1817    return pCtx->hwvirt.vmx.fInVmxRootMode;
     1818#else
     1819    NOREF(pCtx);
     1820    return false;
     1821#endif
     1822}
     1823
    18121824#endif /* IPRT_WITHOUT_NAMED_UNIONS_AND_STRUCTS */
    18131825

  • trunk/include/VBox/vmm/cpumctx.h

    r73436 r73606  
    3131# include <VBox/types.h>
    3232# include <VBox/vmm/hm_svm.h>
     33# include <VBox/vmm/hm_vmx.h>
    3334#else
    3435# pragma D depends_on library x86.d
    … …  
    488489            {
    489490                /** 0x2e0 - MSR holding physical address of the Guest's Host-state. */
    490                 uint64_t            uMsrHSavePa;
     491                uint64_t                uMsrHSavePa;
    491492                /** 0x2e8 - Guest physical address of the nested-guest VMCB. */
    492                 RTGCPHYS            GCPhysVmcb;
     493                RTGCPHYS                GCPhysVmcb;
    493494                /** 0x2f0 - Cache of the nested-guest VMCB - R0 ptr. */
    494                 R0PTRTYPE(PSVMVMCB) pVmcbR0;
     495                R0PTRTYPE(PSVMVMCB)     pVmcbR0;
    495496#if HC_ARCH_BITS == 32
    496                 uint32_t            uVmcbR0Padding;
     497                uint32_t                uVmcbR0Padding;
    497498#endif
    498499                /** 0x2f8 - Cache of the nested-guest VMCB - R3 ptr. */
    499                 R3PTRTYPE(PSVMVMCB) pVmcbR3;
     500                R3PTRTYPE(PSVMVMCB)     pVmcbR3;
    500501#if HC_ARCH_BITS == 32
    501                 uint32_t            uVmcbR3Padding;
     502                uint32_t                uVmcbR3Padding;
    502503#endif
    503504                /** 0x300 - Guest's host-state save area. */
    504                 SVMHOSTSTATE        HostState;
     505                SVMHOSTSTATE            HostState;
    505506                /** 0x3b8 - Guest TSC time-stamp of when the previous PAUSE instr. was executed. */
    506                 uint64_t            uPrevPauseTick;
     507                uint64_t                uPrevPauseTick;
    507508                /** 0x3c0 - Pause filter count. */
    508                 uint16_t            cPauseFilter;
     509                uint16_t                cPauseFilter;
    509510                /** 0x3c2 - Pause filter threshold. */
    510                 uint16_t            cPauseFilterThreshold;
     511                uint16_t                cPauseFilterThreshold;
    511512                /** 0x3c4 - Whether the injected event is subject to event intercepts. */
    512                 bool                fInterceptEvents;
     513                bool                    fInterceptEvents;
    513514                /** 0x3c5 - Padding. */
    514                 bool                afPadding[3];
     515                bool                    afPadding[3];
    515516                /** 0x3c8 - MSR permission bitmap - R0 ptr. */
    516                 R0PTRTYPE(void *)   pvMsrBitmapR0;
     517                R0PTRTYPE(void *)       pvMsrBitmapR0;
    517518#if HC_ARCH_BITS == 32
    518                 uint32_t            uvMsrBitmapR0Padding;
     519                uint32_t                uvMsrBitmapR0Padding;
    519520#endif
    520521                /** 0x3d0 - MSR permission bitmap - R3 ptr. */
    521                 R3PTRTYPE(void *)   pvMsrBitmapR3;
     522                R3PTRTYPE(void *)       pvMsrBitmapR3;
    522523#if HC_ARCH_BITS == 32
    523                 uint32_t            uvMsrBitmapR3Padding;
     524                uint32_t                uvMsrBitmapR3Padding;
    524525#endif
    525526                /** 0x3d8 - IO permission bitmap - R0 ptr. */
    526                 R0PTRTYPE(void *)   pvIoBitmapR0;
     527                R0PTRTYPE(void *)       pvIoBitmapR0;
    527528#if HC_ARCH_BITS == 32
    528                 uint32_t            uIoBitmapR0Padding;
     529                uint32_t                uIoBitmapR0Padding;
    529530#endif
    530531                /** 0x3e0 - IO permission bitmap - R3 ptr. */
    531                 R3PTRTYPE(void *)   pvIoBitmapR3;
     532                R3PTRTYPE(void *)       pvIoBitmapR3;
    532533#if HC_ARCH_BITS == 32
    533                 uint32_t            uIoBitmapR3Padding;
     534                uint32_t                uIoBitmapR3Padding;
    534535#endif
    535536                /** 0x3e8 - Host physical address of the nested-guest VMCB.  */
    536                 RTHCPHYS            HCPhysVmcb;
     537                RTHCPHYS                HCPhysVmcb;
    537538            } svm;
    538539
    539540            struct
    540541            {
    541                 /** 0x2e0 - Whether the guest is in VMX root mode. */
    542                 uint32_t            fInVmxRootMode : 1;
    543                 uint32_t            afPadding  : 31;
    544542                /** 0x2e4 - Guest physical address of the VMXON region. */
    545                 RTGCPHYS            GCPhysVmxon;
    546                 /** 0x2ec - Padding. */
    547                 uint8_t             abPadding[0x3f0 - 0x2ec];
     543                RTGCPHYS                GCPhysVmxon;
     544                /** 0x2e8 - Guest physical address of the current VMCS pointer. */
     545                RTGCPHYS                GCPhysVmcs;
     546                /** 0x2f0 - Last emulated VMX instruction diagnostic. */
     547                VMXVINSTRDIAG           enmInstrDiag;
     548                /** 0x2f4 - Whether the guest is in VMX root mode. */
     549                bool                    fInVmxRootMode;
     550                /** 0x2f5 - Whether the guest is in VMX non-root mode. */
     551                bool                    fInVmxNonRootMode;
     552                /** 0x2f6 - Padding.  */
     553                bool                    afPadding[2];
     554                /** 0x2f8 - Cache of the nested-guest current VMCS - R0 ptr. */
     555                R0PTRTYPE(PVMXVVMCS)    pVmcsR0;
     556#if HC_ARCH_BITS == 32
     557                uint32_t                uVmcsR0Padding;
     558#endif
     559                /** 0x300 - Cache of the nested-guest curent VMCS - R3 ptr. */
     560                R3PTRTYPE(PVMXVVMCS)    pVmcsR3;
     561#if HC_ARCH_BITS == 32
     562                uint32_t                uVmcsR3Padding;
     563#endif
     564                /** 0x308 - Padding. */
     565                uint8_t             abPadding[0x3f0 - 0x308];
    548566            } vmx;
    549567        } CPUM_UNION_NM(s);

  • trunk/include/VBox/vmm/hm.h

    r73395 r73606  
    130130VMM_INT_DECL(bool)              HMHasPendingIrq(PVM pVM);
    131131VMM_INT_DECL(PX86PDPE)          HMGetPaePdpes(PVMCPU pVCpu);
    132 VMM_INT_DECL(int)               HMAmdIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
    133132VMM_INT_DECL(bool)              HMSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable);
    134133VMM_INT_DECL(bool)              HMIsSvmActive(PVM pVM);
    … …  
    136135VMM_INT_DECL(bool)              HMIsVmxSupported(PVM pVM);
    137136VMM_INT_DECL(void)              HMHCPagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode);
     137/** @} */
     138
     139/** @name All-context VMX helpers.
     140 * These are VMX functions (based on VMX specs.) that may be used by IEM/REM and
     141 * not VirtualBox functions that are used for hardware-assisted VMX. Those are
     142 * declared below under the !IN_RC section.
     143 * @{ */
    138144VMM_INT_DECL(int)               HMVmxGetHostMsrs(PVM pVM, PVMXMSRS pVmxMsrs);
    139145VMM_INT_DECL(int)               HMVmxGetHostMsr(PVM pVM, uint32_t idMsr, uint64_t *puValue);
     146VMM_INT_DECL(const char *)      HMVmxGetInstrDiagDesc(VMXVINSTRDIAG enmInstrDiag);
    140147/** @} */
    141148
    … …  
    151158                                                         uint8_t cAddrSizeBits, uint8_t iEffSeg, bool fRep, bool fStrIo,
    152159                                                         PSVMIOIOEXITINFO pIoExitInfo);
    153 VMM_INT_DECL(int)               HMHCSvmMaybeMovTprHypercall(PVMCPU pVCpu);
    154160/** @} */
    155161
    … …  
    168174VMM_INT_DECL(void)              HMSvmNstGstVmExitNotify(PVMCPU pVCpu, PCPUMCTX pCtx);
    169175# endif
     176VMM_INT_DECL(int)               HMSvmIsSubjectToErratum170(uint32_t *pu32Family, uint32_t *pu32Model, uint32_t *pu32Stepping);
     177VMM_INT_DECL(int)               HMHCSvmMaybeMovTprHypercall(PVMCPU pVCpu);
    170178#else /* Nops in RC: */
    171 # define HMFlushTLB(pVCpu)                              do { } while (0)
    172 # define HMFlushTLBOnAllVCpus(pVM)                      do { } while (0)
    173 # define HMInvalidatePageOnAllVCpus(pVM, GCVirt)        do { } while (0)
    174 # define HMInvalidatePhysPage(pVM,  GCVirt)             do { } while (0)
    175 # define HMAreNestedPagingAndFullGuestExecEnabled(pVM)  false
    176 # define HMIsLongModeAllowed(pVM)                       false
    177 # define HMIsNestedPagingActive(pVM)                    false
    178 # define HMIsMsrBitmapsActive(pVM)                      false
    179 # define HMSvmIsVGifActive(pVM)                         false
    180 # define HMSvmNstGstApplyTscOffset(pVCpu, uTicks)       (uTicks)
    181 # define HMSvmNstGstVmExitNotify(pVCpu, pCtx)           do { } while (0)
     179# define HMFlushTLB(pVCpu)                                            do { } while (0)
     180# define HMFlushTLBOnAllVCpus(pVM)                                    do { } while (0)
     181# define HMInvalidatePageOnAllVCpus(pVM, GCVirt)                      do { } while (0)
     182# define HMInvalidatePhysPage(pVM,  GCVirt)                           do { } while (0)
     183# define HMAreNestedPagingAndFullGuestExecEnabled(pVM)                false
     184# define HMIsLongModeAllowed(pVM)                                     false
     185# define HMIsNestedPagingActive(pVM)                                  false
     186# define HMIsMsrBitmapsActive(pVM)                                    false
     187# define HMSvmIsVGifActive(pVM)                                       false
     188# define HMSvmNstGstApplyTscOffset(pVCpu, uTicks)                     (uTicks)
     189# define HMSvmNstGstVmExitNotify(pVCpu, pCtx)                         do { } while (0)
     190# define HMSvmIsSubjectToErratum170(puFamily, puModel, puStepping)    false
     191# define HMHCSvmMaybeMovTprHypercall(pVCpu)                           do { } while (0)
    182192#endif
    183193

  • trunk/include/VBox/vmm/hm_vmx.h

    r73431 r73606  
    812812
    813813/**
     814 * VMX VMCS revision identifier.
     815 */
     816typedef union
     817{
     818    struct
     819    {
     820        /** Revision identifier. */
     821        uint32_t    u31RevisionId : 31;
     822        /** Whether this is a shadow VMCS. */
     823        uint32_t    fIsShadowVmcs : 1;
     824    } n;
     825    /* The unsigned integer view. */
     826    uint32_t        u;
     827} VMXVMCSREVID;
     828AssertCompileSize(VMXVMCSREVID, 4);
     829/** Pointer to the VMXVMCSREVID union. */
     830typedef VMXVMCSREVID *PVMXVMCSREVID;
     831/** Pointer to a const VMXVVMCSREVID union. */
     832typedef const VMXVMCSREVID *PCVMXVMCSREVID;
     833
     834/**
     835 * VMX VM-exit instruction information.
     836 */
     837typedef union
     838{
     839    /** Plain unsigned int representation. */
     840    uint32_t    u;
     841    /** INS and OUTS information. */
     842    struct
     843    {
     844        uint32_t    u7Reserved0 : 7;
     845        /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
     846        uint32_t    u3AddrSize  : 3;
     847        uint32_t    u5Reserved1 : 5;
     848        /** The segment register (X86_SREG_XXX). */
     849        uint32_t    iSegReg     : 3;
     850        uint32_t    uReserved2  : 14;
     851    } StrIo;
     852    /** INVEPT, INVVPID, INVPCID, VMCLEAR, VMPTRLD, VMPTRST, VMXON, VMXOFF, XSAVES,
     853     *  XRSTORS information. */
     854    struct
     855    {
     856        /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
     857        uint32_t    u2Scaling       : 2;
     858        uint32_t    u5Reserved0     : 5;
     859        /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
     860        uint32_t    u3AddrSize      : 3;
     861        /** Memory/Register - Always cleared to 0 to indicate memory operand. */
     862        uint32_t    fIsRegOperand   : 1;
     863        uint32_t    u4Reserved0     : 4;
     864        /** The segment register (X86_SREG_XXX). */
     865        uint32_t    iSegReg         : 3;
     866        /** The index register (X86_GREG_XXX). */
     867        uint32_t    iIdxReg         : 4;
     868        /** Set if index register is invalid. */
     869        uint32_t    fIdxRegInvalid  : 1;
     870        /** The base register (X86_GREG_XXX). */
     871        uint32_t    iBaseReg        : 4;
     872        /** Set if base register is invalid. */
     873        uint32_t    fBaseRegInvalid : 1;
     874        /** Register 2 (X86_GREG_XXX). */
     875        uint32_t    iReg2           : 4;
     876    } InvVmxXsaves;
     877} VMXEXITINSTRINFO;
     878AssertCompileSize(VMXEXITINSTRINFO, 4);
     879/** Pointer to a VMX VM-exit instruction info. struct. */
     880typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
     881/** Pointer to a const VMX VM-exit instruction info. struct. */
     882typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
     883
     884/**
    814885 * VMX MSR autoload/store element.
    815886 * In accordance to the VT-x spec.
    … …  
    10461117
    10471118/** @name VM Instruction Errors.
    1048  * @{
    1049  */
    1050 /** VMCALL executed in VMX root operation. */
    1051 #define VMX_ERROR_VMCALL                                        1
    1052 /** VMCLEAR with invalid physical address. */
    1053 #define VMX_ERROR_VMCLEAR_INVALID_PHYS_ADDR                     2
    1054 /** VMCLEAR with VMXON pointer. */
    1055 #define VMX_ERROR_VMCLEAR_INVALID_VMXON_PTR                     3
    1056 /** VMLAUNCH with non-clear VMCS. */
    1057 #define VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS                        4
    1058 /** VMRESUME with non-launched VMCS. */
    1059 #define VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS                    5
    1060 /** VMRESUME with a corrupted VMCS (indicates corruption of the current VMCS). */
    1061 #define VMX_ERROR_VMRESUME_CORRUPTED_VMCS                       6
    1062 /** VM-entry with invalid control field(s). */
    1063 #define VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS                7
    1064 /** VM-entry with invalid host-state field(s). */
    1065 #define VMX_ERROR_VMENTRY_INVALID_HOST_STATE                    8
    1066 /** VMPTRLD with invalid physical address. */
    1067 #define VMX_ERROR_VMPTRLD_INVALID_PHYS_ADDR                     9
    1068 /** VMPTRLD with VMXON pointer. */
    1069 #define VMX_ERROR_VMPTRLD_VMXON_PTR                             10
    1070 /** VMPTRLD with incorrect VMCS revision identifier. */
    1071 #define VMX_ERROR_VMPTRLD_WRONG_VMCS_REVISION                   11
    1072 /** VMREAD/VMWRITE from/to unsupported VMCS component. */
    1073 #define VMX_ERROR_VMREAD_INVALID_COMPONENT                      12
    1074 #define VMX_ERROR_VMWRITE_INVALID_COMPONENT                     VMX_ERROR_VMREAD_INVALID_COMPONENT
    1075 /** VMWRITE to read-only VMCS component. */
    1076 #define VMX_ERROR_VMWRITE_READONLY_COMPONENT                    13
    1077 /** VMXON executed in VMX root operation. */
    1078 #define VMX_ERROR_VMXON_IN_VMX_ROOT_OP                          15
    1079 /** VM-entry with invalid executive-VMCS pointer. */
    1080 #define VMX_ERROR_VMENTRY_INVALID_VMCS_EXEC_PTR                 16
    1081 /** VM-entry with non-launched executive VMCS. */
    1082 #define VMX_ERROR_VMENTRY_NON_LAUNCHED_EXEC_VMCS                17
    1083 /** VM-entry with executive-VMCS pointer not VMXON pointer. */
    1084 #define VMX_ERROR_VMENTRY_EXEC_VMCS_PTR                         18
    1085 /** VMCALL with non-clear VMCS. */
    1086 #define VMX_ERROR_VMCALL_NON_CLEAR_VMCS                         19
    1087 /** VMCALL with invalid VM-exit control fields. */
    1088 #define VMX_ERROR_VMCALL_INVALID_VMEXIT_FIELDS                  20
    1089 /** VMCALL with incorrect MSEG revision identifier. */
    1090 #define VMX_ERROR_VMCALL_INVALID_MSEG_REVISION                  22
    1091 /** VMXOFF under dual-monitor treatment of SMIs and SMM. */
    1092 #define VMX_ERROR_VMXOFF_DUAL_MONITOR                           23
    1093 /** VMCALL with invalid SMM-monitor features. */
    1094 #define VMX_ERROR_VMCALL_INVALID_SMM_MONITOR                    24
    1095 /** VM-entry with invalid VM-execution control fields in executive VMCS. */
    1096 #define VMX_ERROR_VMENTRY_INVALID_VM_EXEC_CTRL                  25
    1097 /** VM-entry with events blocked by MOV SS. */
    1098 #define VMX_ERROR_VMENTRY_MOV_SS                                26
    1099 /** Invalid operand to INVEPT/INVVPID. */
    1100 #define VMX_ERROR_INVEPTVPID_INVALID_OPERAND                    28
     1119 * See Intel spec. "30.4 VM Instruction Error Numbers"
     1120 * @{
     1121 */
     1122typedef enum
     1123{
     1124    /** VMCALL executed in VMX root operation. */
     1125    VMXINSTRERR_VMCALL_VMXROOTMODE             = 1,
     1126    /** VMCLEAR with invalid physical address. */
     1127    VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR       = 2,
     1128    /** VMCLEAR with VMXON pointer. */
     1129    VMXINSTRERR_VMCLEAR_VMXON_PTR              = 3,
     1130    /** VMLAUNCH with non-clear VMCS. */
     1131    VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS        = 4,
     1132    /** VMRESUME with non-launched VMCS. */
     1133    VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS     = 5,
     1134    /** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
     1135    VMXINSTRERR_VMRESUME_AFTER_VMXOFF          = 6,
     1136    /** VM-entry with invalid control field(s). */
     1137    VMXINSTRERR_VMENTRY_INVALID_CTL            = 7,
     1138    /** VM-entry with invalid host-state field(s). */
     1139    VMXINSTRERR_VMENTRY_INVALID_HOST_STATE     = 8,
     1140    /** VMPTRLD with invalid physical address. */
     1141    VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR       = 9,
     1142    /** VMPTRLD with VMXON pointer. */
     1143    VMXINSTRERR_VMPTRLD_VMXON_PTR              = 10,
     1144    /** VMPTRLD with incorrect VMCS revision identifier. */
     1145    VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV     = 11,
     1146    /** VMREAD from unsupported VMCS component. */
     1147    VMXINSTRERR_VMREAD_INVALID_COMPONENT       = 12,
     1148    /** VMWRITE to unsupported VMCS component. */
     1149    VMXINSTRERR_VMWRITE_INVALID_COMPONENT      = 12,
     1150    /** VMWRITE to read-only VMCS component. */
     1151    VMXINSTRERR_VMWRITE_RO_COMPONENT           = 13,
     1152    /** VMXON executed in VMX root operation. */
     1153    VMXINSTRERR_VMXON_IN_VMXROOTMODE           = 15,
     1154    /** VM-entry with invalid executive-VMCS pointer. */
     1155    VMXINSTRERR_VMENTRY_INVALID_VMCS_PTR       = 16,
     1156    /** VM-entry with non-launched executive VMCS. */
     1157    VMXINSTRERR_VMENTRY_NON_LAUNCHED_VMCS      = 17,
     1158    /** VM-entry with executive-VMCS pointer not VMXON pointer. */
     1159    VMXINSTRERR_VMENTRY_VMCS_PTR               = 18,
     1160    /** VMCALL with non-clear VMCS. */
     1161    VMXINSTRERR_VMCALL_NON_CLEAR_VMCS          = 19,
     1162    /** VMCALL with invalid VM-exit control fields. */
     1163    VMXINSTRERR_VMCALL_INVALID_EXITCTLS        = 20,
     1164    /** VMCALL with incorrect MSEG revision identifier. */
     1165    VMXINSTRERR_VMCALL_INVALID_MSEG_ID         = 22,
     1166    /** VMXOFF under dual-monitor treatment of SMIs and SMM. */
     1167    VMXINSTRERR_VMXOFF_DUAL_MON                = 23,
     1168    /** VMCALL with invalid SMM-monitor features. */
     1169    VMXINSTRERR_VMCALL_INVALID_SMMCTLS         = 24,
     1170    /** VM-entry with invalid VM-execution control fields in executive VMCS. */
     1171    VMXINSTRERR_VMENTRY_INVALID_EXECTLS        = 25,
     1172    /** VM-entry with events blocked by MOV SS. */
     1173    VMXINSTRERR_VMENTRY_BLOCK_MOVSS            = 26,
     1174    /** Invalid operand to INVEPT/INVVPID. */
     1175    VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
     1176} VMXINSTRERR;
    11011177/** @} */
    11021178
    … …  
    11061182 */
    11071183/** VMCS (and related regions) memory type - Uncacheable. */
    1108 #define VMX_BASIC_MEM_TYPE_UC                                    0
     1184#define VMX_BASIC_MEM_TYPE_UC                                   0
    11091185/** VMCS (and related regions) memory type - Write back. */
    1110 #define VMX_BASIC_MEM_TYPE_WB                                    6
     1186#define VMX_BASIC_MEM_TYPE_WB                                   6
     1187
    11111188/** Bit fields for MSR_IA32_VMX_BASIC.  */
    11121189/** VMCS revision identifier used by the processor. */
    … …  
    15741651/** Default1 class when true capability MSRs are not supported. */
    15751652#define VMX_PIN_CTLS_DEFAULT1                                   UINT32_C(0x00000016)
     1653
    15761654/** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
    15771655 *  controls field in the VMCS. */
    … …  
    16461724/** Default1 class when true-capability MSRs are not supported. */
    16471725#define VMX_PROC_CTLS_DEFAULT1                                  UINT32_C(0x0401e172)
     1726
    16481727/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
    16491728 *  controls field in the VMCS. */
    … …  
    17581837/** Use TSC scaling. */
    17591838#define VMX_PROC_CTLS2_TSC_SCALING                              RT_BIT(25)
     1839
    17601840/** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
    17611841 *  VM-execution controls field in the VMCS. */
    … …  
    18361916/** Default1 class when true-capability MSRs are not supported. */
    18371917#define VMX_ENTRY_CTLS_DEFAULT1                                 UINT32_C(0x000011ff)
     1918
    18381919/** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
    18391920 *  VMCS. */
    … …  
    18901971/** Default1 class when true-capability MSRs are not supported.  */
    18911972#define VMX_EXIT_CTLS_DEFAULT1                                  UINT32_C(0x00036dff)
     1973
    18921974/** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
    18931975 *  VMCS. */
    … …  
    19452027
    19462028
     2029/** @name VM-entry interruption information.
     2030 * @{ */
     2031#define VMX_ENTRY_INT_INFO_VECTOR(a)                             ((a) & 0xff)
     2032#define VMX_ENTRY_INT_INFO_TYPE_SHIFT                            8
     2033#define VMX_ENTRY_INT_INFO_TYPE(a)                               (((a) >> 8) & 7)
     2034#define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID                      RT_BIT(11)
     2035#define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a)                (((a) >> 11) & 1)
     2036#define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET                      12
     2037#define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a)                (((a) >> 12) & 1)
     2038#define VMX_ENTRY_INT_INFO_VALID                                 RT_BIT(31)
     2039#define VMX_ENTRY_INT_INFO_IS_VALID(a)                           (((a) >> 31) & 1)
     2040/** Construct an VM-entry interruption information field from a VM-exit interruption
     2041 *  info value (same except that bit 12 is reserved). */
     2042#define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a)                 ((a) & ~RT_BIT(12))
     2043/** Construct a VM-entry interruption information field from an IDT-vectoring
     2044 *  information field (same except that bit 12 is reserved). */
     2045#define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a)                 ((a) & ~RT_BIT(12))
     2046
     2047/** Bit fields for VM-entry interruption information. */
     2048#define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT                       0
     2049#define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK                        UINT32_C(0x000000ff)
     2050#define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT                         8
     2051#define VMX_BF_ENTRY_INT_INFO_TYPE_MASK                          UINT32_C(0x00000700)
     2052#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT               11
     2053#define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK                UINT32_C(0x00000800)
     2054#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT                   12
     2055#define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK                    UINT32_C(0x7ffff000)
     2056#define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT                        31
     2057#define VMX_BF_ENTRY_INT_INFO_VALID_MASK                         UINT32_C(0x80000000)
     2058RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
     2059                            (VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
     2060/** @} */
     2061
     2062
     2063/** @name VM-entry interruption information types.
     2064 * @{
     2065 */
     2066#define VMX_ENTRY_INT_INFO_TYPE_EXT_INT                          0
     2067#define VMX_ENTRY_INT_INFO_TYPE_NMI                              2
     2068#define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT                          3
     2069#define VMX_ENTRY_INT_INFO_TYPE_SW_INT                           4
     2070#define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT                     5
     2071#define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT                          6
     2072#define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT                      7
     2073/** @} */
     2074
     2075
    19472076/** @name VM-exit interruption information.
    19482077 * @{
    … …  
    19572086#define VMX_EXIT_INT_INFO_VALID                                 RT_BIT(31)
    19582087#define VMX_EXIT_INT_INFO_IS_VALID(a)                           (((a) >> 31) & 1)
    1959 /** Construct an irq event injection value from the exit interruption info value
    1960  *  (same except that bit 12 is reserved). */
    1961 #define VMX_VMCS_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(a)           ((a) & ~RT_BIT(12))
     2088
     2089/** Bit fields for VM-exit interruption infomration. */
     2090#define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT                       0
     2091#define VMX_BF_EXIT_INT_INFO_VECTOR_MASK                        UINT32_C(0x000000ff)
     2092#define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT                         8
     2093#define VMX_BF_EXIT_INT_INFO_TYPE_MASK                          UINT32_C(0x00000700)
     2094#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT               11
     2095#define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK                UINT32_C(0x00000800)
     2096#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT             12
     2097#define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK              UINT32_C(0x00001000)
     2098#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT                   13
     2099#define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK                    UINT32_C(0x7fffe000)
     2100#define VMX_BF_EXIT_INT_INFO_VALID_SHIFT                        31
     2101#define VMX_BF_EXIT_INT_INFO_VALID_MASK                         UINT32_C(0x80000000)
     2102RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
     2103                            (VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
    19622104/** @} */
    19632105
    … …  
    19722114#define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT                     5
    19732115#define VMX_EXIT_INT_INFO_TYPE_SW_XCPT                          6
     2116#define VMX_EXIT_INT_INFO_TYPE_UNUSED                           7
    19742117/** @} */
    19752118
    … …  
    19792122 */
    19802123#define VMX_IDT_VECTORING_INFO_VECTOR(a)                        ((a) & 0xff)
    1981 #define VMX_IDT_VECTORING_INFO_TYPE_SHIFT                       8
    19822124#define VMX_IDT_VECTORING_INFO_TYPE(a)                          (((a) >> 8) & 7)
    1983 #define VMX_IDT_VECTORING_INFO_ERROR_CODE_VALID                 RT_BIT(11)
    19842125#define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a)           (((a) >> 11) & 1)
    1985 #define VMX_IDT_VECTORING_INFO_VALID(a)                         ((a) & RT_BIT(31))
    1986 #define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a)                ((a) & ~RT_BIT(12))
     2126#define VMX_IDT_VECTORING_INFO_IS_VALID(a)                      (((a) >> 31) & 1)
     2127
     2128/** Bit fields for IDT-vectoring information. */
     2129#define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT                  0
     2130#define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK                   UINT32_C(0x000000ff)
     2131#define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT                    8
     2132#define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK                     UINT32_C(0x00000700)
     2133#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT          11
     2134#define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK           UINT32_C(0x00000800)
     2135#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT                12
     2136#define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK                 UINT32_C(0x00001000)
     2137#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT              13
     2138#define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK               UINT32_C(0x7fffe000)
     2139#define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT                   31
     2140#define VMX_BF_IDT_VECTORING_INFO_VALID_MASK                    UINT32_C(0x80000000)
     2141RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
     2142                            (VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
    19872143/** @} */
    19882144
    … …  
    19972153#define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT                5
    19982154#define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT                     6
     2155#define VMX_IDT_VECTORING_INFO_TYPE_SW_UNUSED                   7
    19992156/** @} */
    20002157
    … …  
    23452502/** CR0 bits set here must always be set when in VMX operation. */
    23462503#define VMX_V_CR0_FIXED0                                        (X86_CR0_PE | X86_CR0_NE | X86_CR0_PG)
     2504/** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
     2505#define VMX_V_CR0_FIXED0_UX                                     (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE | X86_CR0_PG))
    23472506/** CR4 bits set here must always be set when in VMX operation. */
    23482507#define VMX_V_CR4_FIXED0                                        (X86_CR4_VMXE)
    … …  
    23632522 *  etc.) are limited to 32-bits (4G). Always 0 on 64-bit CPUs. */
    23642523#define VMX_V_VMCS_PHYSADDR_4G_LIMIT                            0
     2524
     2525/**
     2526 * Virtual VMX-instruction diagnostics.
     2527 *
     2528 * These are not the same as VM instruction errors that are enumerated in the Intel
     2529 * spec. These are purely internal, fine-grained definitions used for diagnostic
     2530 * purposes and are not reported to guest software under the VM-instruction error
     2531 * field in its VMCS.
     2532 *
     2533 * @note Members of this enum are used as array indices, so no gaps are allowed.
     2534 *       Please update g_apszVmxInstrDiagDesc when you add new fields to this
     2535 *       enum.
     2536 */
     2537typedef enum
     2538{
     2539    /* Internal processing errors. */
     2540    kVmxVInstrDiag_Ipe_1 = 0,
     2541    kVmxVInstrDiag_Ipe_2,
     2542    kVmxVInstrDiag_Ipe_3,
     2543    kVmxVInstrDiag_Ipe_4,
     2544    kVmxVInstrDiag_Ipe_5,
     2545    kVmxVInstrDiag_Ipe_6,
     2546    kVmxVInstrDiag_Ipe_7,
     2547    kVmxVInstrDiag_Ipe_8,
     2548    kVmxVInstrDiag_Ipe_9,
     2549    /* VMXON. */
     2550    kVmxVInstrDiag_Vmxon_A20M,
     2551    kVmxVInstrDiag_Vmxon_Cpl,
     2552    kVmxVInstrDiag_Vmxon_Cr0Fixed0,
     2553    kVmxVInstrDiag_Vmxon_Cr4Fixed0,
     2554    kVmxVInstrDiag_Vmxon_Intercept,
     2555    kVmxVInstrDiag_Vmxon_LongModeCS,
     2556    kVmxVInstrDiag_Vmxon_MsrFeatCtl,
     2557    kVmxVInstrDiag_Vmxon_PtrAlign,
     2558    kVmxVInstrDiag_Vmxon_PtrAbnormal,
     2559    kVmxVInstrDiag_Vmxon_PtrMap,
     2560    kVmxVInstrDiag_Vmxon_PtrReadPhys,
     2561    kVmxVInstrDiag_Vmxon_PtrWidth,
     2562    kVmxVInstrDiag_Vmxon_RealOrV86Mode,
     2563    kVmxVInstrDiag_Vmxon_ShadowVmcs,
     2564    kVmxVInstrDiag_Vmxon_Success,
     2565    kVmxVInstrDiag_Vmxon_Vmxe,
     2566    kVmxVInstrDiag_Vmxon_VmcsRevId,
     2567    kVmxVInstrDiag_Vmxon_VmxRoot,
     2568    kVmxVInstrDiag_Vmxon_VmxRootCpl,
     2569    /* VMXOFF. */
     2570    kVmxVInstrDiag_Vmxoff_Cpl,
     2571    kVmxVInstrDiag_Vmxoff_Intercept,
     2572    kVmxVInstrDiag_Vmxoff_LongModeCS,
     2573    kVmxVInstrDiag_Vmxoff_RealOrV86Mode,
     2574    kVmxVInstrDiag_Vmxoff_Success,
     2575    kVmxVInstrDiag_Vmxoff_Vmxe,
     2576    kVmxVInstrDiag_Vmxoff_VmxRoot,
     2577    /* Last member for determining array index limit. */
     2578    kVmxVInstrDiag_Last
     2579} VMXVINSTRDIAG;
     2580AssertCompileSize(VMXVINSTRDIAG, 4);
    23652581
    23662582/**
    … …  
    23742590typedef struct
    23752591{
    2376     /** Revision identifier. */
    2377     uint32_t            u31RevisionId : 31;
    2378     /** Whether this is a shadow VMCS. */
    2379     uint32_t            fIsShadowVmcs : 1;
    2380 
     2592    /** VMX VMCS revision identifier.   */
     2593    VMXVMCSREVID        u32VmcsRevId;
    23812594    /** VMX-abort indicator. */
    23822595    uint32_t            u32VmxAbortId;

  • trunk/include/VBox/vmm/iem.h

    r73024 r73606  
    299299VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedInvd(PVMCPU pVCpu, uint8_t cbInstr);
    300300VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedInvlpg(PVMCPU pVCpu,  uint8_t cbInstr, RTGCPTR GCPtrPage);
    301 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedInvpcid(PVMCPU pVCpu, uint8_t cbInstr, uint8_t uType, RTGCPTR GCPtrInvpcidDesc);
    302301VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedCpuid(PVMCPU pVCpu, uint8_t cbInstr);
    303302VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedRdpmc(PVMCPU pVCpu, uint8_t cbInstr);
    … …  
    319318VMM_INT_DECL(VBOXSTRICTRC)  IEMExecSvmVmexit(PVMCPU pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);
    320319#endif
     320
     321#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
     322VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedVmxoff(PVMCPU pVCpu, uint8_t cbInstr);
     323VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedVmxon(PVMCPU pVCpu, uint8_t cbInstr, RTGCPTR GCPtrVmxon, uint32_t uExitInstrInfo,
     324                                                RTGCPTR GCPtrDisp);
     325#endif
    321326/** @}  */
    322327
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette