Changeset 73606 in vbox for trunk/src/VBox/VMM/VMMR3

Timestamp:

Aug 10, 2018 7:38:56 AM (6 years ago)

Author:

vboxsync

Message:

VMM: Nested VMX: bugref:9180 Various bits:

• IEM: Started VMXON, VMXOFF implementation, use IEM_OPCODE_GET_NEXT_RM.
• IEM: Fixed INVPCID C impl, removed unused IEMExecDecodedInvpcid.
• IEM: Updated iemCImpl_load_CrX to check for CR0/CR4 fixed bits in VMX.
• IEM: Update offModRm to reset/re-initialize where needed.
• CPUM: Added VMX root, non-root mode and other bits and updated a few places where they're used.
• HM: Started adding fine-grained VMX instruction failure diagnostics.
• HM: Made VM instruction error an enum.
• HM: Added HMVMXAll.cpp for all context VMX code.
• Ensure building with VBOX_WITH_NESTED_HWVIRT_[SVM|VMX] does the right thing based on host CPU.
• CPUM: Added dumping of nested-VMX CPUMCTX state.
• HMVMXR0: Added memory operand decoding.
• HMVMXR0: VMX instr. privilege checks (CR0/CR4 read shadows are not consulted, so we need to do them)
• HM: Added some more bit-field representaions.
• Recompiler: Refuse to run when in nested-VMX guest code.

Location:

trunk/src/VBox/VMM/VMMR3

Files:

• CPUM.cpp (modified) (3 diffs)
• CPUMR3CpuId.cpp (modified) (1 diff)
• EM.cpp (modified) (2 diffs)
• HM.cpp (modified) (11 diffs)
• PGMPhys.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMR3/CPUM.cpp

@@ -2775 +2775 @@
     PCPUMCTX pCtx = &pVCpu->cpum.s.Guest;
     static const char *const s_aHwvirtModes[] = { "No/inactive", "SVM", "VMX", "Common" };
-    uint8_t const idxHwvirtState = CPUMIsGuestInSvmNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_SVM
-                                 : CPUMIsGuestInVmxNestedHwVirtMode(pCtx) ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE;
+    bool const fSvm = pVM->cpum.ro.GuestFeatures.fSvm;
+    bool const fVmx = pVM->cpum.ro.GuestFeatures.fVmx;
+    uint8_t const idxHwvirtState = fSvm ? CPUMHWVIRTDUMP_SVM : (fVmx ? CPUMHWVIRTDUMP_VMX : CPUMHWVIRTDUMP_NONE);
     AssertCompile(CPUMHWVIRTDUMP_LAST <= RT_ELEMENTS(s_aHwvirtModes));
     Assert(idxHwvirtState < RT_ELEMENTS(s_aHwvirtModes));
@@ -2788 +2789 @@
 
     if (fDumpState & CPUMHWVIRTDUMP_COMMON)
-    {
-        pHlp->pfnPrintf(pHlp, "fGif                           = %RTbool\n", pCtx->hwvirt.fGif);
-        pHlp->pfnPrintf(pHlp, "fLocalForcedActions            = %#RX32\n",  pCtx->hwvirt.fLocalForcedActions);
-    }
+        pHlp->pfnPrintf(pHlp, "fLocalForcedActions          = %#RX32\n",  pCtx->hwvirt.fLocalForcedActions);
+
     pHlp->pfnPrintf(pHlp, "%s hwvirt state%s\n", pcszHwvirtMode, (fDumpState & (CPUMHWVIRTDUMP_SVM | CPUMHWVIRTDUMP_VMX)) ?
                                                                  ":" : "");
     if (fDumpState & CPUMHWVIRTDUMP_SVM)
     {
+        pHlp->pfnPrintf(pHlp, "  fGif                       = %RTbool\n", pCtx->hwvirt.fGif);
+
         char szEFlags[80];
         cpumR3InfoFormatFlags(&szEFlags[0], pCtx->hwvirt.svm.HostState.rflags.u);
-
         pHlp->pfnPrintf(pHlp, "  uMsrHSavePa                = %#RX64\n",    pCtx->hwvirt.svm.uMsrHSavePa);
         pHlp->pfnPrintf(pHlp, "  GCPhysVmcb                 = %#RGp\n",     pCtx->hwvirt.svm.GCPhysVmcb);
@@ -2839 +2839 @@
     }
 
-    /** @todo Intel.  */
-#if 0
     if (fDumpState & CPUMHWVIRTDUMP_VMX)
     {
+        pHlp->pfnPrintf(pHlp, "  fInVmxRootMode             = %RTbool\n",   pCtx->hwvirt.vmx.fInVmxRootMode);
+        pHlp->pfnPrintf(pHlp, "  fInVmxNonRootMode          = %RTbool\n",   pCtx->hwvirt.vmx.fInVmxNonRootMode);
+        pHlp->pfnPrintf(pHlp, "  GCPhysVmxon                = %#RGp\n",     pCtx->hwvirt.vmx.GCPhysVmxon);
+        pHlp->pfnPrintf(pHlp, "  GCPhysVmcs                 = %#RGp\n",     pCtx->hwvirt.vmx.GCPhysVmcs);
+        pHlp->pfnPrintf(pHlp, "  enmInstrDiag               = %u (%s)\n",   pCtx->hwvirt.vmx.enmInstrDiag,
+                        HMVmxGetInstrDiagDesc(pCtx->hwvirt.vmx.enmInstrDiag));
+        /** @todo NSTVMX: Dump remaining/new fields. */
     }
-#endif
 
 #undef CPUMHWVIRTDUMP_NONE

trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

@@ -3937 +3937 @@
     AssertLogRelRCReturn(rc, rc);
 
-#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
-    /** @cfgm{/CPUM/NestedHWVirt, bool, false}
-     * Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
-     * The default is false, and when enabled requires nested paging and AMD-V or
-     * unrestricted guest mode.
-     */
-    rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
-    AssertLogRelRCReturn(rc, rc);
-    if (   pConfig->fNestedHWVirt
-        && !fNestedPagingAndFullGuestExec)
-        return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
-                          "Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
-
-    /** @todo Think about enabling this later with NEM/KVM. */
-    if (   pConfig->fNestedHWVirt
-        && VM_IS_NEM_ENABLED(pVM))
-    {
-        LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
-        pConfig->fNestedHWVirt = false;
-    }
+    bool fQueryNestedHwvirt = false;
+#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
+    fQueryNestedHwvirt |= RT_BOOL(pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_AMD);
 #endif
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+    fQueryNestedHwvirt |= RT_BOOL(   pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_INTEL
+                                  || pVM->cpum.s.HostFeatures.enmCpuVendor == CPUMCPUVENDOR_VIA);
+#endif
+    if (fQueryNestedHwvirt)
+    {
+        /** @cfgm{/CPUM/NestedHWVirt, bool, false}
+         * Whether to expose the hardware virtualization (VMX/SVM) feature to the guest.
+         * The default is false, and when enabled requires nested paging and AMD-V or
+         * unrestricted guest mode.
+         */
+        rc = CFGMR3QueryBoolDef(pCpumCfg, "NestedHWVirt", &pConfig->fNestedHWVirt, false);
+        AssertLogRelRCReturn(rc, rc);
+        if (   pConfig->fNestedHWVirt
+            && !fNestedPagingAndFullGuestExec)
+            return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
+                              "Cannot enable nested VT-x/AMD-V without nested-paging and unresricted guest execution!\n");
+
+        /** @todo Think about enabling this later with NEM/KVM. */
+        if (   pConfig->fNestedHWVirt
+            && VM_IS_NEM_ENABLED(pVM))
+        {
+            LogRel(("CPUM: WARNING! Can't turn on nested VT-x/AMD-V when NEM is used!\n"));
+            pConfig->fNestedHWVirt = false;
+        }
+    }
 
     /*

trunk/src/VBox/VMM/VMMR3/EM.cpp

@@ -1815 +1815 @@
     }
 
-    if (CPUMIsGuestInVmxNestedHwVirtMode(&pVCpu->cpum.GstCtx))
+    if (CPUMIsGuestInVmxNonRootMode(&pVCpu->cpum.GstCtx))
     { /** @todo Nested VMX. */ }
 
@@ -2147 +2147 @@
                 Assert(!HMR3IsEventPending(pVCpu));
 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM
-                if (CPUMIsGuestInNestedHwVirtMode(&pVCpu->cpum.GstCtx))
+                if (CPUMIsGuestInSvmNestedHwVirtMode(&pVCpu->cpum.GstCtx))
                 {
                     bool fResched, fInject;

trunk/src/VBox/VMM/VMMR3/HM.cpp

@@ -42 +42 @@
 #include <VBox/vmm/stam.h>
 #include <VBox/vmm/mm.h>
+#include <VBox/vmm/em.h>
 #include <VBox/vmm/pdmapi.h>
 #include <VBox/vmm/pgm.h>
@@ -77 +78 @@
 #define EXIT_REASON(def, val, str) #def " - " #val " - " str
 #define EXIT_REASON_NIL() NULL
-/** Exit reason descriptions for VT-x, used to describe statistics. */
-static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
+/** Exit reason descriptions for VT-x, used to describe statistics and exit
+ *  history. */
+static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
 {
     EXIT_REASON(VMX_EXIT_XCPT_OR_NMI            ,   0, "Exception or non-maskable interrupt (NMI)."),
@@ -149 +151 @@
 #define MAX_EXITREASON_VTX                         64
 
-/** A partial list of Exit reason descriptions for AMD-V, used to describe
- *  statistics.
+/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
+ *  statistics and exit history.
  *
  *  @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
  *        this array doesn't contain the entire set of exit reasons, we
  *        handle them via hmSvmGetSpecialExitReasonDesc(). */
-static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
+static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
 {
     EXIT_REASON(SVM_EXIT_READ_CR0     ,    0, "Read CR0."),
@@ -310 +312 @@
 /**
  * Gets the SVM exit reason if it's one of the reasons not present in the @c
- * g_apszAmdVExitReasons array.
+ * g_apszSvmExitReasons array.
  *
  * @returns The exit reason or NULL if unknown.
@@ -1061 +1063 @@
 #undef HM_REG_COUNTER
 
-        const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
-                                                                               : &g_apszAmdVExitReasons[0];
+        const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVmxExitReasons[0]
+                                                                               : &g_apszSvmExitReasons[0];
 
         /*
@@ -1938 +1940 @@
     uint32_t u32Model;
     uint32_t u32Stepping;
-    if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
+    if (HMSvmIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
         LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
     LogRel(("HM: Max resume loops                  = %u\n",     pVM->hm.s.cMaxResumeLoops));
@@ -2948 +2950 @@
 
 #ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
-    if (CPUMIsGuestInNestedHwVirtMode(pCtx))
+    if (   CPUMIsGuestInSvmNestedHwVirtMode(pCtx)
+        || CPUMIsGuestVmxEnabled(pCtx))
     {
         Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
@@ -3151 +3154 @@
         &&  CPUMIsGuestInRealModeEx(pCtx)
         && !PDMVmmDevHeapIsEnabled(pVM))
-    {
         return true;
-    }
 
     return false;
@@ -3429 +3430 @@
                 LogRel(("HM: CPU[%u] Exit reason          %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
 
-                if (   pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
-                    || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
+                if (   pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
+                    || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
                 {
                     LogRel(("HM: CPU[%u] Entered Host Cpu     %u\n",  i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
                     LogRel(("HM: CPU[%u] Current Host Cpu     %u\n",  i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
                 }
-                else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
+                else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTL)
                 {
                     LogRel(("HM: CPU[%u] PinCtls          %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
@@ -3756 +3757 @@
 VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
 {
-    if (uExit < RT_ELEMENTS(g_apszVTxExitReasons))
-        return g_apszVTxExitReasons[uExit];
+    if (uExit < RT_ELEMENTS(g_apszVmxExitReasons))
+        return g_apszVmxExitReasons[uExit];
     return NULL;
 }
@@ -3770 +3771 @@
 VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
 {
-    if (uExit < RT_ELEMENTS(g_apszAmdVExitReasons))
-        return g_apszAmdVExitReasons[uExit];
+    if (uExit < RT_ELEMENTS(g_apszSvmExitReasons))
+        return g_apszSvmExitReasons[uExit];
     return hmSvmGetSpecialExitReasonDesc(uExit);
 }

trunk/src/VBox/VMM/VMMR3/PGMPhys.cpp

@@ -4549 +4549 @@
     if (pVCpu->pgm.s.fA20Enabled != fEnable)
     {
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+        PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
+        if (   CPUMIsGuestInVmxRootMode(pCtx)
+            && !fEnable)
+        {
+            Log(("Cannot enter A20M mode while in VMX root mode\n"));
+            return;
+        }
+#endif
         pVCpu->pgm.s.fA20Enabled = fEnable;
         pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!fEnable << 20);