Changeset 73636 in vbox for trunk/src/VBox
- Timestamp:
- Aug 13, 2018 1:07:26 PM (6 years ago)
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Serial/UartCore.cpp
r73528 r73636 69 69 /** Sets the interrupt identification to the given value. */ 70 70 # define UART_REG_IIR_ID_SET(a_Val) (((a_Val) << 1) & UART_REG_IIR_ID_MASK) 71 /** Gets the interrupt identification from the given IIR register value. */ 72 # define UART_REG_IIR_ID_GET(a_Val) (((a_Val) >> 1) & UART_REG_IIR_ID_MASK) 71 73 /** Receiver Line Status interrupt. */ 72 74 # define UART_REG_IIR_ID_RCL 0x3 … … 303 305 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA); 304 306 else if ( (pThis->uRegLsr & UART_REG_LSR_THRE) 305 && (pThis->uRegIer & UART_REG_IER_ETBEI))307 && pThis->fThreEmptyPending) 306 308 uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE); 307 309 else if ( (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS) … … 689 691 { 690 692 pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT; 693 pThis->fThreEmptyPending = false; 691 694 692 695 uartFifoClear(&pThis->FifoXmit); … … 749 752 uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, uVal); 750 753 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT); 754 pThis->fThreEmptyPending = false; 751 755 uartIrqUpdate(pThis); 752 756 if (pThis->pDrvSerial) … … 768 772 pThis->uRegThr = uVal; 769 773 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT); 774 pThis->fThreEmptyPending = false; 770 775 uartIrqUpdate(pThis); 771 776 if (pThis->pDrvSerial) … … 1116 1121 { 1117 1122 *puVal = pThis->uRegIir; 1123 /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */ 1124 if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE) 1125 { 1126 pThis->fThreEmptyPending = false; 1127 uartIrqUpdate(pThis); 1128 } 1118 1129 return VINF_SUCCESS; 1119 1130 } … … 1406 1417 *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead); 1407 1418 if (!pThis->FifoXmit.cbUsed) 1419 { 1408 1420 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE); 1421 pThis->fThreEmptyPending = true; 1422 } 1409 1423 if (*pcbRead) 1410 1424 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT); … … 1417 1431 UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE); 1418 1432 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT); 1433 pThis->fThreEmptyPending = true; 1419 1434 uartIrqUpdate(pThis); 1420 1435 } … … 1493 1508 SSMR3PutU8(pSSM, pThis->uRegScr); 1494 1509 SSMR3PutBool(pSSM, pThis->fIrqCtiPending); 1510 SSMR3PutBool(pSSM, pThis->fThreEmptyPending); 1495 1511 SSMR3PutU8(pSSM, pThis->FifoXmit.cbMax); 1496 1512 SSMR3PutU8(pSSM, pThis->FifoXmit.cbItl); … … 1522 1538 SSMR3GetU8(pSSM, &pThis->uRegScr); 1523 1539 SSMR3GetBool(pSSM, &pThis->fIrqCtiPending); 1540 SSMR3GetBool(pSSM, &pThis->fThreEmptyPending); 1524 1541 SSMR3GetU8(pSSM, &pThis->FifoXmit.cbMax); 1525 1542 SSMR3GetU8(pSSM, &pThis->FifoXmit.cbItl); … … 1538 1555 1539 1556 int uIrq; 1557 int32_t iTmp; 1540 1558 uint32_t PortBase; 1541 1559 … … 1550 1568 if (uVersion > UART_SAVED_STATE_VERSION_16450) 1551 1569 SSMR3GetU8(pSSM, &pThis->uRegFcr); 1552 SSMR3Skip(pSSM, sizeof(int32_t)); 1570 SSMR3GetS32(pSSM, &iTmp); 1571 pThis->fThreEmptyPending = RT_BOOL(iTmp); 1553 1572 SSMR3GetS32(pSSM, &uIrq); 1554 1573 SSMR3Skip(pSSM, sizeof(int32_t)); … … 1638 1657 pThis->uRegScr = 0; 1639 1658 pThis->fIrqCtiPending = false; 1659 pThis->fThreEmptyPending = false; 1640 1660 1641 1661 /* Standard FIFO size for 15550A. */ -
trunk/src/VBox/Devices/Serial/UartCore.h
r73259 r73636 181 181 * is not empty). */ 182 182 bool fIrqCtiPending; 183 /** Flag whether the transmitter holding register went empty since last time the 184 * IIR register was read. This gets reset when IIR is read so the guest will get this 185 * interrupt ID only once. */ 186 bool fThreEmptyPending; 183 187 /** Alignment. */ 184 bool afAlignment[ 3];188 bool afAlignment[2]; 185 189 /** The transmit FIFO. */ 186 190 UARTFIFO FifoXmit; -
trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
r73243 r73636 1350 1350 GEN_CHECK_OFF(UARTCORE, uRegScr); 1351 1351 GEN_CHECK_OFF(UARTCORE, fIrqCtiPending); 1352 GEN_CHECK_OFF(UARTCORE, fThreEmptyPending); 1352 1353 GEN_CHECK_OFF(UARTCORE, FifoXmit); 1353 1354 GEN_CHECK_OFF(UARTCORE, FifoRecv);
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