Index: /trunk/src/VBox/Devices/Serial/UartCore.cpp
===================================================================
--- /trunk/src/VBox/Devices/Serial/UartCore.cpp	(revision 73635)
+++ /trunk/src/VBox/Devices/Serial/UartCore.cpp	(revision 73636)
@@ -69,4 +69,6 @@
 /** Sets the interrupt identification to the given value. */
 # define UART_REG_IIR_ID_SET(a_Val)          (((a_Val) << 1) & UART_REG_IIR_ID_MASK)
+/** Gets the interrupt identification from the given IIR register value. */
+# define UART_REG_IIR_ID_GET(a_Val)          (((a_Val) >> 1) & UART_REG_IIR_ID_MASK)
 /** Receiver Line Status interrupt. */
 #  define UART_REG_IIR_ID_RCL                0x3
@@ -303,5 +305,5 @@
         uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_RDA);
     else if (   (pThis->uRegLsr & UART_REG_LSR_THRE)
-             && (pThis->uRegIer & UART_REG_IER_ETBEI))
+             && pThis->fThreEmptyPending)
         uRegIirNew = UART_REG_IIR_ID_SET(UART_REG_IIR_ID_THRE);
     else if (   (pThis->uRegMsr & UART_REG_MSR_BITS_IIR_MS)
@@ -689,4 +691,5 @@
 {
     pThis->uRegLsr = UART_REG_LSR_THRE | UART_REG_LSR_TEMT;
+    pThis->fThreEmptyPending = false;
 
     uartFifoClear(&pThis->FifoXmit);
@@ -749,4 +752,5 @@
             uartFifoPut(&pThis->FifoXmit, true /*fOvrWr*/, uVal);
             UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
+            pThis->fThreEmptyPending = false;
             uartIrqUpdate(pThis);
             if (pThis->pDrvSerial)
@@ -768,4 +772,5 @@
                 pThis->uRegThr = uVal;
                 UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_THRE | UART_REG_LSR_TEMT);
+                pThis->fThreEmptyPending = false;
                 uartIrqUpdate(pThis);
                 if (pThis->pDrvSerial)
@@ -1116,4 +1121,10 @@
 {
     *puVal = pThis->uRegIir;
+    /* Reset the THRE empty interrupt id when this gets returned to the guest (see table 3 UART Reset configuration). */
+    if (UART_REG_IIR_ID_GET(pThis->uRegIir) == UART_REG_IIR_ID_THRE)
+    {
+        pThis->fThreEmptyPending = false;
+        uartIrqUpdate(pThis);
+    }
     return VINF_SUCCESS;
 }
@@ -1406,5 +1417,8 @@
         *pcbRead = uartFifoCopyTo(&pThis->FifoXmit, pvBuf, cbRead);
         if (!pThis->FifoXmit.cbUsed)
+        {
             UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
+            pThis->fThreEmptyPending = true;
+        }
         if (*pcbRead)
             UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
@@ -1417,4 +1431,5 @@
         UART_REG_SET(pThis->uRegLsr, UART_REG_LSR_THRE);
         UART_REG_CLR(pThis->uRegLsr, UART_REG_LSR_TEMT);
+        pThis->fThreEmptyPending = true;
         uartIrqUpdate(pThis);
     }
@@ -1493,4 +1508,5 @@
     SSMR3PutU8(pSSM,   pThis->uRegScr);
     SSMR3PutBool(pSSM, pThis->fIrqCtiPending);
+    SSMR3PutBool(pSSM, pThis->fThreEmptyPending);
     SSMR3PutU8(pSSM,   pThis->FifoXmit.cbMax);
     SSMR3PutU8(pSSM,   pThis->FifoXmit.cbItl);
@@ -1522,4 +1538,5 @@
         SSMR3GetU8(pSSM,   &pThis->uRegScr);
         SSMR3GetBool(pSSM, &pThis->fIrqCtiPending);
+        SSMR3GetBool(pSSM, &pThis->fThreEmptyPending);
         SSMR3GetU8(pSSM,   &pThis->FifoXmit.cbMax);
         SSMR3GetU8(pSSM,   &pThis->FifoXmit.cbItl);
@@ -1538,4 +1555,5 @@
 
         int      uIrq;
+        int32_t  iTmp;
         uint32_t PortBase;
 
@@ -1550,5 +1568,6 @@
         if (uVersion > UART_SAVED_STATE_VERSION_16450)
             SSMR3GetU8(pSSM, &pThis->uRegFcr);
-        SSMR3Skip(pSSM, sizeof(int32_t));
+        SSMR3GetS32(pSSM, &iTmp);
+        pThis->fThreEmptyPending = RT_BOOL(iTmp);
         SSMR3GetS32(pSSM, &uIrq);
         SSMR3Skip(pSSM, sizeof(int32_t));
@@ -1638,4 +1657,5 @@
     pThis->uRegScr        = 0;
     pThis->fIrqCtiPending = false;
+    pThis->fThreEmptyPending = false;
 
     /* Standard FIFO size for 15550A. */
Index: /trunk/src/VBox/Devices/Serial/UartCore.h
===================================================================
--- /trunk/src/VBox/Devices/Serial/UartCore.h	(revision 73635)
+++ /trunk/src/VBox/Devices/Serial/UartCore.h	(revision 73636)
@@ -181,6 +181,10 @@
      * is not empty). */
     bool                            fIrqCtiPending;
+    /** Flag whether the transmitter holding register went empty since last time the
+     * IIR register was read. This gets reset when IIR is read so the guest will get this
+     * interrupt ID only once. */
+    bool                            fThreEmptyPending;
     /** Alignment. */
-    bool                            afAlignment[3];
+    bool                            afAlignment[2];
         /** The transmit FIFO. */
     UARTFIFO                        FifoXmit;
Index: /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp
===================================================================
--- /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 73635)
+++ /trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp	(revision 73636)
@@ -1350,4 +1350,5 @@
     GEN_CHECK_OFF(UARTCORE, uRegScr);
     GEN_CHECK_OFF(UARTCORE, fIrqCtiPending);
+    GEN_CHECK_OFF(UARTCORE, fThreEmptyPending);
     GEN_CHECK_OFF(UARTCORE, FifoXmit);
     GEN_CHECK_OFF(UARTCORE, FifoRecv);
