Changeset 74171 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Sep 10, 2018 7:48:40 AM (6 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp
r74147 r74171 1519 1519 int rc = HMVmxGetHostMsr(pVCpu->CTX_SUFF(pVM), MSR_IA32_VMX_MISC, &uHostMsr); 1520 1520 AssertMsgRC(rc, ("HMVmxGetHostMsr failed. rc=%Rrc\n", rc)); RT_NOREF_PV(rc); 1521 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_MAX_MSRS); 1521 uint8_t const cMaxMsrs = RT_MIN(RT_BF_GET(uHostMsr, VMX_BF_MISC_MAX_MSRS), VMX_V_MAX_MSRS); 1522 uint8_t const fActivityState = RT_BF_GET(uHostMsr, VMX_BF_MISC_ACTIVITY_STATES) & VMX_V_GUEST_ACTIVITY_STATE_MASK; 1522 1523 uVmxMsr = RT_BF_MAKE(VMX_BF_MISC_PREEMPT_TIMER_TSC, VMX_V_PREEMPT_TIMER_SHIFT ) 1523 1524 | RT_BF_MAKE(VMX_BF_MISC_EXIT_STORE_EFER_LMA, pGuestFeatures->fVmxExitStoreEferLma ) 1524 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, VMX_V_GUEST_ACTIVITY_STATE_MASK)1525 | RT_BF_MAKE(VMX_BF_MISC_ACTIVITY_STATES, fActivityState ) 1525 1526 | RT_BF_MAKE(VMX_BF_MISC_PT, 0 ) 1526 1527 | RT_BF_MAKE(VMX_BF_MISC_SMM_READ_SMBASE_MSR, 0 ) … … 1603 1604 1604 1605 /** 1605 * Gets IA32_VMX_CR4_FIXED0 for IEM and cpumMsrRd_Ia32Vmx Misc.1606 * Gets IA32_VMX_CR4_FIXED0 for IEM and cpumMsrRd_Ia32VmxCr4Fixed0. 1606 1607 * 1607 1608 * @returns IA32_VMX_CR4_FIXED0 value. … … 1626 1627 1627 1628 /** 1628 * Gets IA32_VMX_CR4_FIXED1 for IEM and cpumMsrRd_Ia32Vmx Misc.1629 * Gets IA32_VMX_CR4_FIXED1 for IEM and cpumMsrRd_Ia32VmxCr4Fixed1. 1629 1630 * 1630 1631 * @returns IA32_VMX_CR4_FIXED1 MSR. … … 1658 1659 1659 1660 /** 1660 * Gets IA32_VMX_VMCS_ENUM for IEM and cpumMsrRd_Ia32Vmx Misc.1661 * Gets IA32_VMX_VMCS_ENUM for IEM and cpumMsrRd_Ia32VmxVmcsEnum. 1661 1662 * 1662 1663 * @returns IA32_VMX_VMCS_ENUM value. … … 1685 1686 1686 1687 /** 1687 * Gets MSR_IA32_VMX_PROCBASED_CTLS2 for IEM and cpumMsrRd_Ia32Vmx Misc.1688 * Gets MSR_IA32_VMX_PROCBASED_CTLS2 for IEM and cpumMsrRd_Ia32VmxProcBasedCtls2. 1688 1689 * 1689 1690 * @returns MSR_IA32_VMX_PROCBASED_CTLS2 value. -
trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp
r74166 r74171 169 169 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrBase , "GuestIdtrBase" ), 170 170 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIdtrLimit , "GuestIdtrLimit" ), 171 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateEnclave , "GuestIntStateEnclave" ), 172 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateExtInt , "GuestIntStateExtInt" ), 173 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateNmi , "GuestIntStateNmi" ), 174 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRFlagsSti , "GuestIntStateRFlagsSti" ), 175 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateRsvd , "GuestIntStateRsvd" ), 176 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateSmi , "GuestIntStateSmi" ), 177 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateStiMovSs , "GuestIntStateStiMovSs" ), 178 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestIntStateVirtNmi , "GuestIntStateVirtNmi" ), 171 179 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPae , "GuestPae" ), 172 180 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_GuestPatMsr , "GuestPatMsr" ), … … 296 304 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_SavePreemptTimer , "SavePreemptTimer" ), 297 305 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_Success , "Success" ), 298 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThreshold , "TprThreshold"),306 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdRsvd , "TprThresholdRsvd" ), 299 307 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_TprThresholdVTpr , "TprThresholdVTpr" ), 300 308 VMXV_DIAG_DESC(kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys , "VirtApicPageReadPhys" ), … … 358 366 AssertPtrReturn(puValue, VERR_INVALID_PARAMETER); 359 367 360 if (!pVM->hm.s.vmx.fSupported) 361 return VERR_VMX_NOT_SUPPORTED; 362 363 PCVMXMSRS pVmxMsrs = &pVM->hm.s.vmx.Msrs; 364 switch (idMsr) 368 if (pVM->hm.s.vmx.fSupported) 365 369 { 366 case MSR_IA32_FEATURE_CONTROL: *puValue = pVmxMsrs->u64FeatCtrl; break; 367 case MSR_IA32_VMX_BASIC: *puValue = pVmxMsrs->u64Basic; break; 368 case MSR_IA32_VMX_PINBASED_CTLS: *puValue = pVmxMsrs->PinCtls.u; break; 369 case MSR_IA32_VMX_PROCBASED_CTLS: *puValue = pVmxMsrs->ProcCtls.u; break; 370 case MSR_IA32_VMX_PROCBASED_CTLS2: *puValue = pVmxMsrs->ProcCtls2.u; break; 371 case MSR_IA32_VMX_EXIT_CTLS: *puValue = pVmxMsrs->ExitCtls.u; break; 372 case MSR_IA32_VMX_ENTRY_CTLS: *puValue = pVmxMsrs->EntryCtls.u; break; 373 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: *puValue = pVmxMsrs->TruePinCtls.u; break; 374 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: *puValue = pVmxMsrs->TrueProcCtls.u; break; 375 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: *puValue = pVmxMsrs->TrueEntryCtls.u; break; 376 case MSR_IA32_VMX_TRUE_EXIT_CTLS: *puValue = pVmxMsrs->TrueExitCtls.u; break; 377 case MSR_IA32_VMX_MISC: *puValue = pVmxMsrs->u64Misc; break; 378 case MSR_IA32_VMX_CR0_FIXED0: *puValue = pVmxMsrs->u64Cr0Fixed0; break; 379 case MSR_IA32_VMX_CR0_FIXED1: *puValue = pVmxMsrs->u64Cr0Fixed1; break; 380 case MSR_IA32_VMX_CR4_FIXED0: *puValue = pVmxMsrs->u64Cr4Fixed0; break; 381 case MSR_IA32_VMX_CR4_FIXED1: *puValue = pVmxMsrs->u64Cr4Fixed1; break; 382 case MSR_IA32_VMX_VMCS_ENUM: *puValue = pVmxMsrs->u64VmcsEnum; break; 383 case MSR_IA32_VMX_VMFUNC: *puValue = pVmxMsrs->u64VmFunc; break; 384 case MSR_IA32_VMX_EPT_VPID_CAP: *puValue = pVmxMsrs->u64EptVpidCaps; break; 385 default: 370 PCVMXMSRS pVmxMsrs = &pVM->hm.s.vmx.Msrs; 371 switch (idMsr) 386 372 { 387 AssertMsgFailed(("Invalid MSR %#x\n", idMsr)); 388 return VERR_NOT_FOUND; 373 case MSR_IA32_FEATURE_CONTROL: *puValue = pVmxMsrs->u64FeatCtrl; break; 374 case MSR_IA32_VMX_BASIC: *puValue = pVmxMsrs->u64Basic; break; 375 case MSR_IA32_VMX_PINBASED_CTLS: *puValue = pVmxMsrs->PinCtls.u; break; 376 case MSR_IA32_VMX_PROCBASED_CTLS: *puValue = pVmxMsrs->ProcCtls.u; break; 377 case MSR_IA32_VMX_PROCBASED_CTLS2: *puValue = pVmxMsrs->ProcCtls2.u; break; 378 case MSR_IA32_VMX_EXIT_CTLS: *puValue = pVmxMsrs->ExitCtls.u; break; 379 case MSR_IA32_VMX_ENTRY_CTLS: *puValue = pVmxMsrs->EntryCtls.u; break; 380 case MSR_IA32_VMX_TRUE_PINBASED_CTLS: *puValue = pVmxMsrs->TruePinCtls.u; break; 381 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS: *puValue = pVmxMsrs->TrueProcCtls.u; break; 382 case MSR_IA32_VMX_TRUE_ENTRY_CTLS: *puValue = pVmxMsrs->TrueEntryCtls.u; break; 383 case MSR_IA32_VMX_TRUE_EXIT_CTLS: *puValue = pVmxMsrs->TrueExitCtls.u; break; 384 case MSR_IA32_VMX_MISC: *puValue = pVmxMsrs->u64Misc; break; 385 case MSR_IA32_VMX_CR0_FIXED0: *puValue = pVmxMsrs->u64Cr0Fixed0; break; 386 case MSR_IA32_VMX_CR0_FIXED1: *puValue = pVmxMsrs->u64Cr0Fixed1; break; 387 case MSR_IA32_VMX_CR4_FIXED0: *puValue = pVmxMsrs->u64Cr4Fixed0; break; 388 case MSR_IA32_VMX_CR4_FIXED1: *puValue = pVmxMsrs->u64Cr4Fixed1; break; 389 case MSR_IA32_VMX_VMCS_ENUM: *puValue = pVmxMsrs->u64VmcsEnum; break; 390 case MSR_IA32_VMX_VMFUNC: *puValue = pVmxMsrs->u64VmFunc; break; 391 case MSR_IA32_VMX_EPT_VPID_CAP: *puValue = pVmxMsrs->u64EptVpidCaps; break; 392 default: 393 { 394 AssertMsgFailed(("Invalid MSR %#x\n", idMsr)); 395 return VERR_NOT_FOUND; 396 } 389 397 } 398 return VINF_SUCCESS; 390 399 } 391 return V INF_SUCCESS;400 return VERR_VMX_NOT_SUPPORTED; 392 401 } 393 402 -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
r74167 r74171 2917 2917 * Activity state. 2918 2918 */ 2919 if (!(pVmcs->u32GuestActivityState & VMX_V_GUEST_ACTIVITY_STATE_MASK)) 2919 uint64_t const u64GuestVmxMiscMsr = CPUMGetGuestIa32VmxMisc(pVCpu); 2920 uint32_t const fActivityStateMask = RT_BF_GET(u64GuestVmxMiscMsr, VMX_BF_MISC_ACTIVITY_STATES); 2921 if (!(pVmcs->u32GuestActivityState & fActivityStateMask)) 2920 2922 { /* likely */ } 2921 2923 else … … 2923 2925 2924 2926 X86DESCATTR SsAttr; SsAttr.u = pVmcs->u32GuestSsAttr; 2925 if (SsAttr.n.u2Dpl != 0) 2926 { 2927 if (pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT) 2928 { /* likely */ } 2929 else 2930 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl); 2931 } 2927 2928 if ( !SsAttr.n.u2Dpl 2929 || pVmcs->u32GuestActivityState != VMX_VMCS_GUEST_ACTIVITY_HLT) 2930 { /* likely */ } 2931 else 2932 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestActStateSsDpl); 2932 2933 2933 2934 if ( pVmcs->u32GuestIntrState == VMX_VMCS_GUEST_INT_STATE_BLOCK_STI … … 2944 2945 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo); 2945 2946 uint8_t const uVector = VMX_ENTRY_INT_INFO_VECTOR(pVmcs->u32EntryIntInfo); 2947 AssertCompile(VMX_V_GUEST_ACTIVITY_STATE_MASK == (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)); 2946 2948 switch (pVmcs->u32GuestActivityState) 2947 2949 { … … 2981 2983 * Interruptibility state. 2982 2984 */ 2983 /** @todo NSTVMX: interruptibility-state. */ 2985 if (!(pVmcs->u32GuestIntrState & ~VMX_VMCS_GUEST_INT_STATE_MASK)) 2986 { /* likely */ } 2987 else 2988 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRsvd); 2989 2990 if ((pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)) 2991 != (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)) 2992 { /* likely */ } 2993 else 2994 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateStiMovSs); 2995 2996 if ( (pVmcs->u64GuestRFlags.u & X86_EFL_IF) 2997 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI)) 2998 { /* likely */ } 2999 else 3000 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateRFlagsSti); 3001 3002 if (VMX_ENTRY_INT_INFO_IS_VALID(pVmcs->u32EntryIntInfo)) 3003 { 3004 uint8_t const uIntType = VMX_ENTRY_INT_INFO_TYPE(pVmcs->u32EntryIntInfo); 3005 if (uIntType == VMX_ENTRY_INT_INFO_TYPE_EXT_INT) 3006 { 3007 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))) 3008 { /* likely */ } 3009 else 3010 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateExtInt); 3011 } 3012 else if (uIntType == VMX_ENTRY_INT_INFO_TYPE_NMI) 3013 { 3014 if (!(pVmcs->u32GuestIntrState & (VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS | VMX_VMCS_GUEST_INT_STATE_BLOCK_STI))) 3015 { /* likely */ } 3016 else 3017 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateNmi); 3018 3019 if ( !(pVmcs->u32PinCtls & VMX_PIN_CTLS_VIRT_NMI) 3020 || !(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)) 3021 { /* likely */ } 3022 else 3023 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateVirtNmi); 3024 } 3025 } 3026 3027 /* We don't support SMM yet. So blocking-by-SMIs must not be set. */ 3028 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI)) 3029 { /* likely */ } 3030 else 3031 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateSmi); 3032 3033 /* We don't support SGX yet. So enclave-interruption must not be set. */ 3034 if (!(pVmcs->u32GuestIntrState & VMX_VMCS_GUEST_INT_STATE_ENCLAVE)) 3035 { /* likely */ } 3036 else 3037 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_GuestIntStateEnclave); 3038 3039 /** @todo NSTVMX: Pending debug exceptions, VMCS link pointer. */ 2984 3040 2985 3041 NOREF(pszInstr); … … 3480 3536 /* TPR threshold without virtual-interrupt delivery. */ 3481 3537 if ( !(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_INT_DELIVERY) 3482 && (pVmcs->u32TprThreshold & VMX_TPR_THRESHOLD_MASK))3483 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThreshold );3538 && (pVmcs->u32TprThreshold & ~VMX_TPR_THRESHOLD_MASK)) 3539 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_TprThresholdRsvd); 3484 3540 3485 3541 /* TPR threshold and VTPR. */
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