- Timestamp:
- Oct 4, 2018 10:56:05 AM (6 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h
r74607 r74608 5208 5208 IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */ 5209 5209 } 5210 5211 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 5212 if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu)) 5213 { 5214 if (iCrReg == 0) 5215 crX = iemVmxGetMaskedCr0(pVCpu, crX); 5216 } 5217 #endif 5210 5218 5211 5219 /* store it */ -
trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h
r74607 r74608 901 901 902 902 /** 903 * Gets the nested-guest CR0 mask subjected to the CR0 guest/host mask and the CR0 904 * read-shadow. 905 * 906 * @returns The masked CR0. 907 * @param pVCpu The cross context virtual CPU structure. 908 * @param uGuestCr0 The guest CR0. 909 */ 910 IEM_STATIC uint64_t iemVmxGetMaskedCr0(PVMCPU pVCpu, uint64_t uGuestCr0) 911 { 912 PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs); 913 Assert(pVmcs); 914 Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu)); 915 916 /* 917 * For each CR0 bit owned by the host, the corresponding bit is loaded from the 918 * CR0-read shadow. For each CR0 bit that is not owned by the host, the corresponding 919 * bit from the guest CR0 is loaded. 920 * 921 * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation". 922 */ 923 uint64_t const fGstHostMask = pVmcs->u64Cr0Mask.u; 924 uint64_t const fReadShadow = pVmcs->u64Cr0ReadShadow.u; 925 uint64_t const fMaskedCr0 = (fReadShadow & fGstHostMask) | (uGuestCr0 & ~fGstHostMask); 926 927 return fMaskedCr0; 928 } 929 930 931 /** 903 932 * Gets VM-exit instruction information along with any displacement for an 904 933 * instruction VM-exit.
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