Changeset 74618 in vbox for trunk/src

Timestamp:

Oct 5, 2018 3:36:30 AM (6 years ago)

Author:

vboxsync

Message:

VMM/IEM: Nested VMX: bugref:9180 Adjust iemGetMaskedCr0 for both CR0 and CR4.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAllCImpl.cpp.h (modified) (3 diffs)
• IEMAllCImplVmxInstr.cpp.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp.h

@@ -5210 +5210 @@
 
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-    /* CRx bits are subject to masking when in VMX non-root mode. */
+    /* CR0/CR4 reads are subject to masking when in VMX non-root mode. */
     if (IEM_VMX_IS_NON_ROOT_MODE(pVCpu))
     {
-        if (iCrReg == 0)
-            crX = iemVmxGetMaskedCr0(pVCpu, crX);
+        if (   iCrReg == 0
+            || iCrReg == 4)
+            crX = iemVmxGetMaskedCrX(pVCpu, iCrReg, crX);
     }
 #endif
@@ -5502 +5503 @@
             IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR3);
 
-            /* clear bit 63 from the source operand and indicate no invalidations are required. */
+            /* Bit 63 being clear in the source operand with PCIDE indicates no invalidations are required. */
             if (   (pVCpu->cpum.GstCtx.cr4 & X86_CR4_PCIDE)
                 && (uNewCrX & RT_BIT_64(63)))
@@ -5513 +5514 @@
             }
 
-            /* check / mask the value. */
+            /* Check / mask the value. */
             if (uNewCrX & UINT64_C(0xfff0000000000000))
             {

trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

@@ -901 +901 @@
 
 /**
- * Gets the nested-guest CR0 mask subjected to the CR0 guest/host mask and the CR0
+ * Gets the nested-guest CR0/CR4 mask subjected to the corresponding guest/host mask
+ * and the read-shadow.
+ *
+ * @returns The masked CR0/CR4.
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   iCrReg      The control register (either CR0 or CR4).
+ * @param   uGuestCrX   The current guest CR0 or guest CR4.
+ */
+IEM_STATIC uint64_t iemVmxGetMaskedCrX(PVMCPU pVCpu, uint8_t iCrReg, uint64_t uGuestCrX)
+{
+    Assert(IEM_VMX_IS_NON_ROOT_MODE(pVCpu));
+    Assert(iCrReg == 0 || iCrReg == 4);
+
+    PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
+    Assert(pVmcs);
+
+    /*
+     * For each CR0 or CR4 bit owned by the host, the corresponding bit is loaded from the
+     * CR0 read shadow or CR4 read shadow. For each CR0 or CR4 bit that is not owned by the
+     * host, the corresponding bit from the guest CR0 or guest CR4 is loaded.
+     *
+     * See Intel Spec. 25.3 "Changes To Instruction Behavior In VMX Non-root Operation".
+     */
+    uint64_t fGstHostMask;
+    uint64_t fReadShadow;
+    if (iCrReg == 0)
+    {
+        fGstHostMask = pVmcs->u64Cr0Mask.u;
+        fReadShadow  = pVmcs->u64Cr0ReadShadow.u;
+    }
+    else
+    {
+        fGstHostMask = pVmcs->u64Cr4Mask.u;
+        fReadShadow  = pVmcs->u64Cr4ReadShadow.u;
+    }
+
+    uint64_t const fMaskedCrX = (fReadShadow & fGstHostMask) | (uGuestCrX & ~fGstHostMask);
+    return fMaskedCrX;
+}
+
+
+
+/**
+ * Gets the nested-guest CR4 mask subjected to the CR0 guest/host mask and the CR4
  * read-shadow.
  *