Changeset 74648 in vbox for trunk/include/VBox

Timestamp:

Oct 7, 2018 6:20:55 AM (6 years ago)

Author:

vboxsync

Message:

VMM/IEM, CPUM: Nested VMX: bugref:9180 VM-exit bits; Add TPR virtualization for WRMSR.

Location:

trunk/include/VBox/vmm

Files:

• cpum.h (modified) (2 diffs)
• hm_vmx.h (modified) (4 diffs)

trunk/include/VBox/vmm/cpum.h

@@ -1268 +1268 @@
     /** @name VMX Miscellaneous data.
      * @{ */
-    /** VMX: Supports storing EFER.LMA on VM-exits into IA32e-mode guest field. */
-    uint32_t        fVmxExitStoreEferLma : 1;
+    /** VMX: Supports storing EFER.LMA into IA32e-mode guest field on VM-exit. */
+    uint32_t        fVmxExitSaveEferLma : 1;
+    /** VMX: Whether Intel PT (Processor Trace) is supported in VMX mode or not. */
+    uint32_t        fVmxIntelPt : 1;
     /** VMX: Supports VMWRITE to any valid VMCS field incl. read-only fields, otherwise
      *  VMWRITE cannot modify read-only VM-exit information fields. */
@@ -1279 +1281 @@
 
     /** VMX: Padding / reserved for future features. */
-    uint32_t        fVmxPadding1 : 2;
+    uint32_t        fVmxPadding1 : 1;
     uint32_t        fVmxPadding2;
 } CPUMFEATURES;

trunk/include/VBox/vmm/hm_vmx.h

@@ -1457 +1457 @@
  */
 /** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
-#define VMX_MISC_EXIT_STORE_EFER_LMA                            RT_BIT(5)
+#define VMX_MISC_EXIT_SAVE_EFER_LMA                             RT_BIT(5)
+/** Whether Intel PT is supported in VMX operation. */
+#define VMX_MISC_INTEL_PT                                       RT_BIT(14)
 /** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
  * VMWRITE cannot modify read-only VM-exit information fields. */
@@ -1472 +1474 @@
 #define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK                      UINT64_C(0x000000000000001f)
 /** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
-#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_SHIFT                   5
-#define VMX_BF_MISC_EXIT_STORE_EFER_LMA_MASK                    UINT64_C(0x0000000000000020)
+#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT                    5
+#define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK                     UINT64_C(0x0000000000000020)
 /** Activity states supported by the implementation. */
 #define VMX_BF_MISC_ACTIVITY_STATES_SHIFT                       6
@@ -1481 +1483 @@
 #define VMX_BF_MISC_RSVD_9_13_MASK                              UINT64_C(0x0000000000003e00)
 /** Whether Intel PT (Processor Trace) can be used in VMX operation.  */
-#define VMX_BF_MISC_PT_SHIFT                                    14
-#define VMX_BF_MISC_PT_MASK                                     UINT64_C(0x0000000000004000)
+#define VMX_BF_MISC_INTEL_PT_SHIFT                              14
+#define VMX_BF_MISC_INTEL_PT_MASK                               UINT64_C(0x0000000000004000)
 /** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
 #define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT                   15
@@ -1511 +1513 @@
 #define VMX_BF_MISC_MSEG_ID_MASK                                UINT64_C(0xffffffff00000000)
 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
-                            (PREEMPT_TIMER_TSC, EXIT_STORE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, PT, SMM_READ_SMBASE_MSR,
+                            (PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
                              CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
 /** @} */