VirtualBox

Changeset 74785 in vbox for trunk/src/VBox/VMM/VMMR0


Ignore:
Timestamp:
Oct 12, 2018 10:14:19 AM (6 years ago)
Author:
vboxsync
Message:

vm.h,VMM: Use VMCPU_FF_IS_SET instead of VMCPU_FF_IS_PENDING when checking a single flag. Added compile time assertion on single flag. bugref:9180

Location:
trunk/src/VBox/VMM/VMMR0
Files:
4 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

    r73606 r74785  
    11581158    Assert(pVCpu->CTX_SUFF(pVM)->hm.s.svm.fSupported);
    11591159
    1160     bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
     1160    bool const fFlushPending = pVCpu->CTX_SUFF(pVM)->hm.s.svm.fAlwaysFlushTLB || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
    11611161
    11621162    /* Skip it if a TLB flush is already pending. */
    … …  
    28062806        {
    28072807            if (  !pVmcbCtrl->IntCtrl.n.u1VIrqPending
    2808                 && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
     2808                && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST))
    28092809                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
    28102810        }
    … …  
    28152815            if (pVmcbCtrl->IntShadow.n.u1IntShadow)
    28162816                EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
    2817             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     2817            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    28182818                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    28192819        }
    … …  
    30223022     */
    30233023    if (   VMMRZCallRing3IsEnabled(pVCpu)
    3024         && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
     3024        && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
    30253025    {
    30263026        Assert(pCtx->cr3 == pVmcbGuest->u64CR3);
    … …  
    36693669     *        delivery/window over a physical interrupt (from the outer guest)
    36703670     *        might be pending? */
    3671     bool const fEnableIntWindow = !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
     3671    bool const fEnableIntWindow = !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NESTED_GUEST);
    36723672    if (!fEnableIntWindow)
    36733673    {
    … …  
    37353735    bool const fVirtualGif = CPUMGetSvmNstGstVGif(pCtx);
    37363736    bool const fIntShadow  = hmR0SvmIsIntrShadowActive(pVCpu);
    3737     bool const fBlockNmi   = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
     3737    bool const fBlockNmi   = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
    37383738
    37393739    Log4Func(("fVirtualGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
    37403740              fVirtualGif, fBlockNmi, fIntShadow, VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC),
    3741               VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
     3741              VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
    37423742
    37433743    /** @todo SMI. SMIs take priority over NMIs. */
    … …  
    37483748     * NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
    37493749     */
    3750     if (    VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)
     3750    if (    VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
    37513751        && !fBlockNmi)
    37523752    {
    … …  
    38603860    bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
    38613861    bool const fBlockInt  = !(pCtx->eflags.u32 & X86_EFL_IF);
    3862     bool const fBlockNmi  = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS);
     3862    bool const fBlockNmi  = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
    38633863
    38643864    Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fBlockInt=%RTbool fIntShadow=%RTbool fIntPending=%RTbool NMI pending=%RTbool\n",
    38653865              fGif, fBlockNmi, fBlockInt, fIntShadow,
    38663866              VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC),
    3867               VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
     3867              VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)));
    38683868
    38693869    /** @todo SMI. SMIs take priority over NMIs. */
    … …  
    38743874     * NMIs take priority over maskable interrupts, see AMD spec. 8.5 "Priorities".
    38753875     */
    3876     if (    VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI)
     3876    if (    VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI)
    38773877        && !fBlockNmi)
    38783878    {
    … …  
    40024002        if (    Event.n.u3Type   == SVM_EVENT_NMI
    40034003            &&  Event.n.u8Vector == X86_XCPT_NMI
    4004             && !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     4004            && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    40054005        {
    40064006            VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
    … …  
    40274027     * but we still need to intercept IRET in order to eventually clear NMI inhibition.
    40284028     */
    4029     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     4029    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    40304030        hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
    40314031
    … …  
    42094209{
    42104210    Assert(VMMRZCallRing3IsEnabled(pVCpu));
    4211     Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
     4211    Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    42124212
    42134213    /* Could happen as a result of longjump. */
    4214     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
     4214    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
    42154215        PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
    42164216
    … …  
    42294229        {
    42304230            int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4,
    4231                                 VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
     4231                                VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
    42324232            if (rc != VINF_SUCCESS)
    42334233            {
    … …  
    42494249
    42504250        /* Pending VM request packets, such as hardware interrupts. */
    4251         if (   VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
    4252             || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
     4251        if (   VM_FF_IS_SET(pVM, VM_FF_REQUEST)
     4252            || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
    42534253        {
    42544254            Log4Func(("Pending VM request forcing us back to ring-3\n"));
    … …  
    60436043
    60446044    /* Update interrupt shadow. */
    6045     if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     6045    if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
    60466046        && pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
    60476047        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    … …  
    74567456
    74577457    /* Clear NMI blocking. */
    7458     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     7458    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    74597459        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
    74607460

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r74604 r74785  
    18481848    LogFlowFunc(("pVCpu=%p GCVirt=%RGv\n", pVCpu, GCVirt));
    18491849
    1850     bool fFlushPending = VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TLB_FLUSH);
     1850    bool fFlushPending = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TLB_FLUSH);
    18511851    if (!fFlushPending)
    18521852    {
    … …  
    34523452     */
    34533453    uint32_t fIntrState = 0;
    3454     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     3454    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    34553455    {
    34563456        /* If inhibition is active, RIP & RFLAGS should've been accessed
    … …  
    34683468                fIntrState = VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS;
    34693469        }
    3470         else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     3470        else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    34713471        {
    34723472            /*
    … …  
    34863486     * See Intel spec. 26.6.1 "Interruptibility state". See @bugref{7445}.
    34873487     */
    3488     if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
     3488    if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
    34893489        && (pVCpu->hm.s.vmx.u32PinCtls & VMX_PIN_CTLS_VIRT_NMI))
    34903490    {
    … …  
    62106210         * See Intel spec. 30.7.1.2 "Resuming Guest Software after Handling an Exception". See @bugref{7445}.
    62116211         */
    6212         if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS)
     6212        if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS)
    62136213            && uIdtVectorType == VMX_IDT_VECTORING_INFO_TYPE_NMI
    62146214            && (   enmRaise   == IEMXCPTRAISE_PREV_EVENT
    … …  
    63126312         * See Intel spec. 30.7.1.2 "Resuming guest software after handling an exception".
    63136313         */
    6314         if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     6314        if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    63156315        {
    63166316            Log4Func(("Setting VMCPU_FF_BLOCK_NMIS. fValid=%RTbool uExitReason=%u\n",
    … …  
    64966496        if (!u32Val)
    64976497        {
    6498             if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     6498            if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    64996499            {
    65006500                rc =  hmR0VmxImportGuestRip(pVCpu);
    … …  
    65036503            }
    65046504
    6505             if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     6505            if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    65066506                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
    65076507        }
    … …  
    65166516                EMSetInhibitInterruptsPC(pVCpu, pCtx->rip);
    65176517            }
    6518             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     6518            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    65196519                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    65206520
    65216521            if (u32Val & VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI)
    65226522            {
    6523                 if (!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     6523                if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    65246524                    VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
    65256525            }
    6526             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     6526            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    65276527                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
    65286528        }
    … …  
    68416841    if (VMMRZCallRing3IsEnabled(pVCpu))
    68426842    {
    6843         if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
     6843        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
    68446844        {
    68456845            Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & CPUMCTX_EXTRN_CR3));
    … …  
    68476847        }
    68486848
    6849         if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
     6849        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
    68506850            PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    68516851
    6852         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    6853         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
     6852        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
     6853        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    68546854    }
    68556855
    … …  
    69126912        Assert(!(ASMAtomicUoReadU64(&pCtx->fExtrn) & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4)));
    69136913        VBOXSTRICTRC rcStrict2 = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4,
    6914                                             VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
     6914                                            VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
    69156915        if (rcStrict2 != VINF_SUCCESS)
    69166916        {
    … …  
    69336933    /* Pending VM request packets, such as hardware interrupts. */
    69346934    if (   VM_FF_IS_PENDING(pVM, VM_FF_REQUEST)
    6935         || VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_REQUEST))
     6935        || VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_REQUEST))
    69366936    {
    69376937        Log4Func(("Pending VM request forcing us back to ring-3\n"));
    … …  
    75197519     */
    75207520                                                               /** @todo SMI. SMIs take priority over NMIs. */
    7521     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INTERRUPT_NMI))    /* NMI. NMIs take priority over regular interrupts. */
     7521    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))        /* NMI. NMIs take priority over regular interrupts. */
    75227522    {
    75237523        /* On some CPUs block-by-STI also blocks NMIs. See Intel spec. 26.3.1.5 "Checks On Guest Non-Register State". */
    … …  
    85278527     * the below force flags to be set.
    85288528     */
    8529     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
     8529    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
    85308530    {
    85318531        Assert(!(ASMAtomicUoReadU64(&pVCpu->cpum.GstCtx.fExtrn) & CPUMCTX_EXTRN_CR3));
    … …  
    85338533        AssertMsgReturn(rc2 == VINF_SUCCESS || rc2 == VINF_PGM_SYNC_CR3,
    85348534                        ("%Rrc\n", rc2), RT_FAILURE_NP(rc2) ? rc2 : VERR_IPE_UNEXPECTED_INFO_STATUS);
    8535         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    8536     }
    8537     if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
     8535        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
     8536    }
     8537    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
    85388538    {
    85398539        PGMGstUpdatePaePdpes(pVCpu, &pVCpu->hm.s.aPdpes[0]);
    8540         Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
     8540        Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    85418541    }
    85428542
    … …  
    88498849            VMMRZCallRing3Enable(pVCpu);
    88508850
    8851             Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
    8852             Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
     8851            Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
     8852            Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
    88538853
    88548854#if defined(HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE) || defined(HMVMX_ALWAYS_SAVE_FULL_GUEST_STATE)
    … …  
    1046510465
    1046610466    /* Update interrupt inhibition. */
    10467     if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     10467    if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
    1046810468        && pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
    1046910469        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
    … …  
    1129011290    }
    1129111291
    11292     Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS));
     11292    Assert(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS));
    1129311293
    1129411294    /*
    … …  
    1130211302    bool const fBlockSti = RT_BOOL(fIntrState & VMX_VMCS_GUEST_INT_STATE_BLOCK_STI);
    1130311303    if (   fBlockSti
    11304         && VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
     11304        && VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
    1130511305    {
    1130611306        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);

  • trunk/src/VBox/VMM/VMMR0/NEMR0Native-win.cpp

    r74517 r74785  
    12191219        pInput->Elements[iReg].Name                 = HvRegisterInterruptState;
    12201220        pInput->Elements[iReg].Value.Reg64          = 0;
    1221         if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     1221        if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
    12221222            && EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
    12231223            pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;
    1224         if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_BLOCK_NMIS))
     1224        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
    12251225            pInput->Elements[iReg].Value.InterruptState.NmiMasked = 1;
    12261226        iReg++;
    … …  
    12291229    {
    12301230        if (   pVCpu->nem.s.fLastInterruptShadow
    1231             || (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     1231            || (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
    12321232                && EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip))
    12331233        {
    … …  
    12351235            pInput->Elements[iReg].Name                 = HvRegisterInterruptState;
    12361236            pInput->Elements[iReg].Value.Reg64          = 0;
    1237             if (   VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
     1237            if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
    12381238                && EMGetInhibitInterruptsPC(pVCpu) == pCtx->rip)
    12391239                pInput->Elements[iReg].Value.InterruptState.InterruptShadow = 1;

  • trunk/src/VBox/VMM/VMMR0/VMMR0.cpp

    r73203 r74785  
    904904        case VINF_EM_RAW_TO_R3:
    905905            STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3Total);
    906             if (VM_FF_IS_PENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
     906            if (VM_FF_IS_SET(pVM, VM_FF_TM_VIRTUAL_SYNC))
    907907                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3TMVirt);
    908             else if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
     908            else if (VM_FF_IS_SET(pVM, VM_FF_PGM_NEED_HANDY_PAGES))
    909909                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3HandyPages);
    910             else if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_QUEUES))
     910            else if (VM_FF_IS_SET(pVM, VM_FF_PDM_QUEUES))
    911911                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3PDMQueues);
    912             else if (VM_FF_IS_PENDING(pVM, VM_FF_EMT_RENDEZVOUS))
     912            else if (VM_FF_IS_SET(pVM, VM_FF_EMT_RENDEZVOUS))
    913913                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3Rendezvous);
    914             else if (VM_FF_IS_PENDING(pVM, VM_FF_PDM_DMA))
     914            else if (VM_FF_IS_SET(pVM, VM_FF_PDM_DMA))
    915915                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3DMA);
    916             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TIMER))
     916            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TIMER))
    917917                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3Timer);
    918             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
     918            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PDM_CRITSECT))
    919919                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3CritSect);
    920             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TO_R3))
     920            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TO_R3))
    921921                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3FF);
    922             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_IEM))
     922            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IEM))
    923923                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3Iem);
    924             else if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_IOM))
     924            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_IOM))
    925925                STAM_COUNTER_INC(&pVM->vmm.s.StatRZRetToR3Iom);
    926926            else
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