Changeset 74835 in vbox for trunk/include
- Timestamp:
- Oct 15, 2018 8:04:21 AM (6 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/vm.h
r74803 r74835 90 90 VMCPUSTATE_32BIT_HACK = 0x7fffffff 91 91 } VMCPUSTATE; 92 93 /** Enables 64-bit FFs. */ 94 #define VMCPU_WITH_64_BIT_FFS 92 95 93 96 … … 427 430 428 431 /** This action forces the VM to check any pending interrupts on the APIC. */ 429 #define VMCPU_FF_INTERRUPT_APIC RT_BIT_ 32(VMCPU_FF_INTERRUPT_APIC_BIT)432 #define VMCPU_FF_INTERRUPT_APIC RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT) 430 433 #define VMCPU_FF_INTERRUPT_APIC_BIT 0 431 434 /** This action forces the VM to check any pending interrups on the PIC. */ 432 #define VMCPU_FF_INTERRUPT_PIC RT_BIT_ 32(VMCPU_FF_INTERRUPT_PIC_BIT)435 #define VMCPU_FF_INTERRUPT_PIC RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT) 433 436 #define VMCPU_FF_INTERRUPT_PIC_BIT 1 434 437 /** This action forces the VM to schedule and run pending timer (TM). 435 438 * @remarks Don't move - PATM compatibility. */ 436 #define VMCPU_FF_TIMER RT_BIT_ 32(VMCPU_FF_TIMER_BIT)439 #define VMCPU_FF_TIMER RT_BIT_64(VMCPU_FF_TIMER_BIT) 437 440 #define VMCPU_FF_TIMER_BIT 2 438 441 /** This action forces the VM to check any pending NMIs. */ 439 #define VMCPU_FF_INTERRUPT_NMI RT_BIT_ 32(VMCPU_FF_INTERRUPT_NMI_BIT)442 #define VMCPU_FF_INTERRUPT_NMI RT_BIT_64(VMCPU_FF_INTERRUPT_NMI_BIT) 440 443 #define VMCPU_FF_INTERRUPT_NMI_BIT 3 441 444 /** This action forces the VM to check any pending SMIs. */ 442 #define VMCPU_FF_INTERRUPT_SMI RT_BIT_ 32(VMCPU_FF_INTERRUPT_SMI_BIT)445 #define VMCPU_FF_INTERRUPT_SMI RT_BIT_64(VMCPU_FF_INTERRUPT_SMI_BIT) 443 446 #define VMCPU_FF_INTERRUPT_SMI_BIT 4 444 447 /** PDM critical section unlocking is pending, process promptly upon return to R3. */ 445 #define VMCPU_FF_PDM_CRITSECT RT_BIT_ 32(VMCPU_FF_PDM_CRITSECT_BIT)448 #define VMCPU_FF_PDM_CRITSECT RT_BIT_64(VMCPU_FF_PDM_CRITSECT_BIT) 446 449 #define VMCPU_FF_PDM_CRITSECT_BIT 5 447 450 /** Special EM internal force flag that is used by EMUnhaltAndWakeUp() to force … … 449 452 * nor cleared by emR3ForcedActions (similar to VMCPU_FF_BLOCK_NMIS), instead it 450 453 * is cleared the next time EM leaves the HALTED state. */ 451 #define VMCPU_FF_UNHALT RT_BIT_ 32(VMCPU_FF_UNHALT_BIT)454 #define VMCPU_FF_UNHALT RT_BIT_64(VMCPU_FF_UNHALT_BIT) 452 455 #define VMCPU_FF_UNHALT_BIT 6 453 456 /** Pending IEM action (mask). */ 454 #define VMCPU_FF_IEM RT_BIT_ 32(VMCPU_FF_IEM_BIT)457 #define VMCPU_FF_IEM RT_BIT_64(VMCPU_FF_IEM_BIT) 455 458 /** Pending IEM action (bit number). */ 456 459 #define VMCPU_FF_IEM_BIT 7 … … 459 462 /** This action forces the VM to update APIC's asynchronously arrived 460 463 * interrupts as pending interrupts. */ 461 #define VMCPU_FF_UPDATE_APIC RT_BIT_ 32(VMCPU_FF_UPDATE_APIC_BIT)464 #define VMCPU_FF_UPDATE_APIC RT_BIT_64(VMCPU_FF_UPDATE_APIC_BIT) 462 465 /** This action forces the VM to service pending requests from other 463 466 * thread or requests which must be executed in another context. */ 464 #define VMCPU_FF_REQUEST RT_BIT_ 32(VMCPU_FF_REQUEST_BIT)467 #define VMCPU_FF_REQUEST RT_BIT_64(VMCPU_FF_REQUEST_BIT) 465 468 #define VMCPU_FF_REQUEST_BIT 9 466 469 /** Pending DBGF event (alternative to passing VINF_EM_DBG_EVENT around). */ 467 #define VMCPU_FF_DBGF RT_BIT_ 32(VMCPU_FF_DBGF_BIT)470 #define VMCPU_FF_DBGF RT_BIT_64(VMCPU_FF_DBGF_BIT) 468 471 /** The bit number for VMCPU_FF_DBGF. */ 469 472 #define VMCPU_FF_DBGF_BIT 10 470 473 /** Pending MTF (Monitor Trap Flag) event - Intel only. */ 471 #define VMCPU_FF_MTF RT_BIT_ 32(VMCPU_FF_MTF_BIT)474 #define VMCPU_FF_MTF RT_BIT_64(VMCPU_FF_MTF_BIT) 472 475 /** The bit number for VMCPU_FF_MTF. */ 473 476 #define VMCPU_FF_MTF_BIT 11 474 477 /** This action forces the VM to service any pending updates to CR3 (used only 475 478 * by HM). */ 476 #define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_ 32(VMCPU_FF_HM_UPDATE_CR3_BIT)479 #define VMCPU_FF_HM_UPDATE_CR3 RT_BIT_64(VMCPU_FF_HM_UPDATE_CR3_BIT) 477 480 #define VMCPU_FF_HM_UPDATE_CR3_BIT 12 478 481 /** This action forces the VM to service any pending updates to PAE PDPEs (used 479 482 * only by HM). */ 480 #define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_ 32(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT)483 #define VMCPU_FF_HM_UPDATE_PAE_PDPES RT_BIT_64(VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT) 481 484 #define VMCPU_FF_HM_UPDATE_PAE_PDPES_BIT 13 482 485 /** This action forces the VM to resync the page tables before going 483 486 * back to execute guest code. (GLOBAL FLUSH) */ 484 #define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_ 32(VMCPU_FF_PGM_SYNC_CR3_BIT)487 #define VMCPU_FF_PGM_SYNC_CR3 RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_BIT) 485 488 #define VMCPU_FF_PGM_SYNC_CR3_BIT 16 486 489 /** Same as VM_FF_PGM_SYNC_CR3 except that global pages can be skipped. 487 490 * (NON-GLOBAL FLUSH) */ 488 #define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_ 32(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT)491 #define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL RT_BIT_64(VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT) 489 492 #define VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL_BIT 17 490 493 /** Check for pending TLB shootdown actions (deprecated) 491 494 * Reserved for furture HM re-use if necessary / safe. 492 495 * Consumer: HM */ 493 #define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_ 32(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT)496 #define VMCPU_FF_TLB_SHOOTDOWN_UNUSED RT_BIT_64(VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT) 494 497 #define VMCPU_FF_TLB_SHOOTDOWN_UNUSED_BIT 18 495 498 /** Check for pending TLB flush action. 496 499 * Consumer: HM 497 500 * @todo rename to VMCPU_FF_HM_TLB_FLUSH */ 498 #define VMCPU_FF_TLB_FLUSH RT_BIT_ 32(VMCPU_FF_TLB_FLUSH_BIT)501 #define VMCPU_FF_TLB_FLUSH RT_BIT_64(VMCPU_FF_TLB_FLUSH_BIT) 499 502 /** The bit number for VMCPU_FF_TLB_FLUSH. */ 500 503 #define VMCPU_FF_TLB_FLUSH_BIT 19 501 504 #ifdef VBOX_WITH_RAW_MODE 502 505 /** Check the interrupt and trap gates */ 503 # define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_ 32(VMCPU_FF_TRPM_SYNC_IDT_BIT)506 # define VMCPU_FF_TRPM_SYNC_IDT RT_BIT_64(VMCPU_FF_TRPM_SYNC_IDT_BIT) 504 507 # define VMCPU_FF_TRPM_SYNC_IDT_BIT 20 505 508 /** Check Guest's TSS ring 0 stack */ 506 # define VMCPU_FF_SELM_SYNC_TSS RT_BIT_ 32(VMCPU_FF_SELM_SYNC_TSS_BIT)509 # define VMCPU_FF_SELM_SYNC_TSS RT_BIT_64(VMCPU_FF_SELM_SYNC_TSS_BIT) 507 510 # define VMCPU_FF_SELM_SYNC_TSS_BIT 21 508 511 /** Check Guest's GDT table */ 509 # define VMCPU_FF_SELM_SYNC_GDT RT_BIT_ 32(VMCPU_FF_SELM_SYNC_GDT_BIT)512 # define VMCPU_FF_SELM_SYNC_GDT RT_BIT_64(VMCPU_FF_SELM_SYNC_GDT_BIT) 510 513 # define VMCPU_FF_SELM_SYNC_GDT_BIT 22 511 514 /** Check Guest's LDT table */ 512 # define VMCPU_FF_SELM_SYNC_LDT RT_BIT_ 32(VMCPU_FF_SELM_SYNC_LDT_BIT)515 # define VMCPU_FF_SELM_SYNC_LDT RT_BIT_64(VMCPU_FF_SELM_SYNC_LDT_BIT) 513 516 # define VMCPU_FF_SELM_SYNC_LDT_BIT 23 514 517 #endif /* VBOX_WITH_RAW_MODE */ 515 518 /** Inhibit interrupts pending. See EMGetInhibitInterruptsPC(). */ 516 #define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_ 32(VMCPU_FF_INHIBIT_INTERRUPTS_BIT)519 #define VMCPU_FF_INHIBIT_INTERRUPTS RT_BIT_64(VMCPU_FF_INHIBIT_INTERRUPTS_BIT) 517 520 #define VMCPU_FF_INHIBIT_INTERRUPTS_BIT 24 518 521 /** Block injection of non-maskable interrupts to the guest. */ 519 #define VMCPU_FF_BLOCK_NMIS RT_BIT_ 32(VMCPU_FF_BLOCK_NMIS_BIT)522 #define VMCPU_FF_BLOCK_NMIS RT_BIT_64(VMCPU_FF_BLOCK_NMIS_BIT) 520 523 #define VMCPU_FF_BLOCK_NMIS_BIT 25 521 524 #ifdef VBOX_WITH_RAW_MODE 522 525 /** CSAM needs to scan the page that's being executed */ 523 # define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_ 32(VMCPU_FF_CSAM_SCAN_PAGE_BIT)526 # define VMCPU_FF_CSAM_SCAN_PAGE RT_BIT_64(VMCPU_FF_CSAM_SCAN_PAGE_BIT) 524 527 # define VMCPU_FF_CSAM_SCAN_PAGE_BIT 26 525 528 /** CSAM needs to do some homework. */ 526 # define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_ 32(VMCPU_FF_CSAM_PENDING_ACTION_BIT)529 # define VMCPU_FF_CSAM_PENDING_ACTION RT_BIT_64(VMCPU_FF_CSAM_PENDING_ACTION_BIT) 527 530 # define VMCPU_FF_CSAM_PENDING_ACTION_BIT 27 528 531 #endif /* VBOX_WITH_RAW_MODE */ 529 532 /** Force return to Ring-3. */ 530 #define VMCPU_FF_TO_R3 RT_BIT_ 32(VMCPU_FF_TO_R3_BIT)533 #define VMCPU_FF_TO_R3 RT_BIT_64(VMCPU_FF_TO_R3_BIT) 531 534 #define VMCPU_FF_TO_R3_BIT 28 532 535 /** Force return to ring-3 to service pending I/O or MMIO write. … … 534 537 * VINF_IOM_R3_MMIO_COMMIT_WRITE, allowing VINF_EM_DBG_BREAKPOINT and similar 535 538 * status codes to be propagated at the same time without loss. */ 536 #define VMCPU_FF_IOM RT_BIT_ 32(VMCPU_FF_IOM_BIT)539 #define VMCPU_FF_IOM RT_BIT_64(VMCPU_FF_IOM_BIT) 537 540 #define VMCPU_FF_IOM_BIT 29 538 541 #ifdef VBOX_WITH_RAW_MODE 539 542 /** CPUM need to adjust CR0.TS/EM before executing raw-mode code again. */ 540 # define VMCPU_FF_CPUM RT_BIT_ 32(VMCPU_FF_CPUM_BIT)543 # define VMCPU_FF_CPUM RT_BIT_64(VMCPU_FF_CPUM_BIT) 541 544 /** The bit number for VMCPU_FF_CPUM. */ 542 545 # define VMCPU_FF_CPUM_BIT 30 543 546 #endif /* VBOX_WITH_RAW_MODE */ 544 547 /** Hardware virtualized nested-guest interrupt pending. */ 545 #define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_ 32(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT)548 #define VMCPU_FF_INTERRUPT_NESTED_GUEST RT_BIT_64(VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT) 546 549 #define VMCPU_FF_INTERRUPT_NESTED_GUEST_BIT 31 547 550 … … 682 685 # define VMCPU_FF_SET(pVCpu, fFlag) do { \ 683 686 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \ 684 AssertCompile((fFlag) == RT_BIT_ 32(fFlag##_BIT)); \687 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \ 685 688 ASMAtomicBitSet(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \ 686 689 } while (0) … … 736 739 # define VMCPU_FF_CLEAR(pVCpu, fFlag) do { \ 737 740 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \ 738 AssertCompile((fFlag) == RT_BIT_ 32(fFlag##_BIT)); \741 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \ 739 742 ASMAtomicBitClear(&(pVCpu)->fLocalForcedActions, fFlag##_BIT); \ 740 743 } while (0) … … 801 804 { \ 802 805 AssertCompile(RT_IS_POWER_OF_TWO(fFlag)); \ 803 AssertCompile((fFlag) == RT_BIT_ 32(fFlag##_BIT)); \806 AssertCompile((fFlag) == RT_BIT_64(fFlag##_BIT)); \ 804 807 return RT_BOOL(a_pVCpu->fLocalForcedActions & (fFlag)); \ 805 808 }(pVCpu))
Note:
See TracChangeset
for help on using the changeset viewer.