Changeset 75199 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Oct 31, 2018 9:03:20 AM (6 years ago)

Author:

vboxsync

Message:

VMM/HMVMXR0: Save FS, GS before reading the FS/GS base MSRs and also only when the MSR read/write needs them.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -11935 +11935 @@
      * MSRs required.  That would require changes to IEM and possibly CPUM too.
      * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
-    uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;  NOREF(idMsr); /* Save it. */
+    uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
     int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
     rc    |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_ALL_MSRS);
+    switch (idMsr)
+    {
+        /* The FS and GS base MSRs are not part of the above all MSRs mask. */
+        case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
+        case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
+    }
     AssertRCReturn(rc, rc);
 
@@ -11994 +12000 @@
      * MSRs required.  That would require changes to IEM and possibly CPUM too.
      * (Should probably do it lazy fashion from CPUMAllMsrs.cpp). */
-    uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx; /* Save it. */
+    uint32_t const idMsr = pVCpu->cpum.GstCtx.ecx;
     int rc = hmR0VmxReadExitInstrLenVmcs(pVmxTransient);
     rc    |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
-                                             | CPUMCTX_EXTRN_ALL_MSRS | CPUMCTX_EXTRN_FS | CPUMCTX_EXTRN_GS);
+                                             | CPUMCTX_EXTRN_ALL_MSRS);
+    switch (idMsr)
+    {
+        /*
+         * The FS and GS base MSRs are not part of the above all MSRs mask.
+         *
+         * Although we don't need to fetch the base as it will be overwritten shortly, while
+         * loading guest-state we would also load the entire segment register including limit
+         * and attributes and thus we need to load them here.
+         */
+        case MSR_K8_FS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_FS); break;
+        case MSR_K8_GS_BASE: rc |= HMVMX_CPUMCTX_IMPORT_STATE(pVCpu, CPUMCTX_EXTRN_GS); break;
+    }
     AssertRCReturn(rc, rc);