Changeset 75493 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Nov 15, 2018 5:06:55 PM (6 years ago)

Author:

vboxsync

Message:

VMM: Nested VMX: bugref: 9180 Use PGM physical page handler for the APIC-access page.

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• CPUMAllMsrs.cpp (modified) (2 diffs)
• CPUMAllVmx.cpp (modified) (2 diffs)
• HMVMXAll.cpp (modified) (1 diff)
• IEMAll.cpp (modified) (5 diffs)
• IEMAllCImplVmxInstr.cpp.h (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/CPUMAllMsrs.cpp

@@ -1278 +1278 @@
         && CPUMIsGuestVmxProcCtls2Set(pVCpu, &pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
     {
-        /** @todo NSTVMX: perhaps IEMExecVmxVirtApicAccessMsr should be moved to
-         *        HMVMXAll.cpp? */
         VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, puValue, false /* fWrite */);
-        Assert(rcStrict == VINF_SUCCESS || rcStrict == VERR_OUT_OF_RANGE || rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
-        if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
-        {
-            if (rcStrict == VERR_OUT_OF_RANGE)
-                return VERR_CPUM_RAISE_GP_0;
-            Assert(rcStrict == VINF_SUCCESS);
+        if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
             return VINF_SUCCESS;
-        }
+        if (rcStrict == VERR_OUT_OF_RANGE)
+            return VERR_CPUM_RAISE_GP_0;
+        Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
     }
 #endif
@@ -1303 +1298 @@
         && CPUMIsGuestVmxProcCtls2Set(pVCpu, &pVCpu->cpum.s.Guest, VMX_PROC_CTLS2_VIRT_X2APIC_MODE))
     {
-        /** @todo NSTVMX: perhaps IEMExecVmxVirtApicAccessMsr should be moved to
-         *        HMVMXAll.cpp? */
         VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMsr(pVCpu, idMsr, &uValue, true /* fWrite */);
-        Assert(rcStrict == VINF_SUCCESS || rcStrict == VERR_OUT_OF_RANGE || rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
-        if (rcStrict != VINF_VMX_INTERCEPT_NOT_ACTIVE)
-        {
-            if (rcStrict == VERR_OUT_OF_RANGE)
-                return VERR_CPUM_RAISE_GP_0;
-            Assert(rcStrict == VINF_SUCCESS);
+        if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
             return VINF_SUCCESS;
-        }
+        if (rcStrict == VERR_OUT_OF_RANGE)
+            return VERR_CPUM_RAISE_GP_0;
+        Assert(rcStrict == VINF_VMX_INTERCEPT_NOT_ACTIVE);
     }
 #endif

trunk/src/VBox/VMM/VMMAll/CPUMAllVmx.cpp

@@ -21 +21 @@
 *********************************************************************************************************************************/
 #define LOG_GROUP LOG_GROUP_CPUM
+#include <VBox/log.h>
 #include <VBox/vmm/cpum.h>
-#include <VBox/log.h>
+#include "CPUMInternal.h"
+#include <VBox/vmm/iem.h>
+#include <VBox/vmm/pgm.h>
+#include <VBox/vmm/vm.h>
 
 
@@ -134 +138 @@
 }
 
+#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
+/**
+ * @callback_method_impl{FNPGMPHYSHANDLER, VMX APIC-access page accesses}
+ *
+ * @remarks The @a pvUser argument is currently unused.
+ */
+PGM_ALL_CB2_DECL(VBOXSTRICTRC) cpumVmxApicAccessPageHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhysFault, void *pvPhys,
+                                                            void *pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType,
+                                                            PGMACCESSORIGIN enmOrigin, void *pvUser)
+{
+    RT_NOREF4(pVM, pvPhys, enmOrigin, pvUser);
+
+    uint16_t const offAccess = (GCPhysFault & PAGE_OFFSET_MASK);
+    bool const fWrite = RT_BOOL(enmAccessType == PGMACCESSTYPE_WRITE);
+    VBOXSTRICTRC rcStrict = IEMExecVmxVirtApicAccessMem(pVCpu, offAccess, cbBuf, pvBuf, fWrite);
+    if (rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
+        rcStrict = VINF_SUCCESS;
+    return rcStrict;
+}
+#endif
+
+
+/**
+ * Registers the PGM physical page handelr for teh VMX APIC-access page.
+ *
+ * @returns VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   GCPhysApicAccess    The guest-physical address of the APIC-access page.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) CPUMVmxApicAccessPageRegister(PVMCPU pVCpu, RTGCPHYS GCPhysApicAccess)
+{
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    int rc = PGMHandlerPhysicalRegister(pVM, GCPhysApicAccess, GCPhysApicAccess, pVM->cpum.s.hVmxApicAccessPage,
+                                        NIL_RTR3PTR /* pvUserR3 */, NIL_RTR0PTR /* pvUserR0 */,  NIL_RTRCPTR /* pvUserRC */,
+                                        NULL /* pszDesc */);
+    return rc;
+}
+
+
+/**
+ * Registers the PGM physical page handelr for teh VMX APIC-access page.
+ *
+ * @returns VBox status code.
+ * @param   pVCpu               The cross context virtual CPU structure.
+ * @param   GCPhysApicAccess    The guest-physical address of the APIC-access page.
+ */
+VMM_INT_DECL(VBOXSTRICTRC) CPUMVmxApicAccessPageDeregister(PVMCPU pVCpu, RTGCPHYS GCPhysApicAccess)
+{
+    /** @todo NSTVMX: If there's anything else to do while APIC-access page is
+     *        de-registered, do it here. */
+    PVM pVM = pVCpu->CTX_SUFF(pVM);
+    if (PGMHandlerPhysicalIsRegistered(pVM, GCPhysApicAccess))
+        return PGMHandlerPhysicalDeregister(pVM, GCPhysApicAccess);
+    return VINF_SUCCESS;
+}
+

trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp

@@ -132 +132 @@
     VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccess           , "AddrApicAccess"            ),
     VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic , "AddrApicAccessEqVirtApic"  ),
+    VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrApicAccessHandlerReg , "AddrApicAccessHandlerReg"  ),
     VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrEntryMsrLoad         , "AddrEntryMsrLoad"          ),
     VMXV_DIAG_DESC(kVmxVDiag_Vmentry_AddrExitMsrLoad          , "AddrExitMsrLoad"           ),

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -8910 +8910 @@
     iemMemUpdateWrittenCounter(pVCpu, fAccess, cbMem);
     *ppvMem = pvMem;
-
-#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-    /*
-     * Check if this is an APIC-access and whether it needs to be virtualized.
-     */
-    if (   CPUMIsGuestInVmxNonRootMode(IEM_GET_CTX(pVCpu))
-        && IEM_VMX_IS_PROCCTLS2_SET(pVCpu, VMX_PROC_CTLS2_VIRT_APIC_ACCESS))
-    {
-        RTGCPHYS const GCPhysMemAccessBase  = GCPhysFirst & ~(RTGCPHYS)PAGE_OFFSET_MASK;
-        RTGCPHYS const GCPhysApicAccessBase = CPUMGetGuestVmxApicAccessPageAddr(pVCpu, IEM_GET_CTX(pVCpu))
-                                            & ~(RTGCPHYS)PAGE_OFFSET_MASK;
-        if (GCPhysMemAccessBase == GCPhysApicAccessBase)
-        {
-            Assert(pvMem);
-            uint16_t const offAccess = GCPhysFirst & (RTGCPHYS)PAGE_OFFSET_MASK;
-            return iemVmxVirtApicAccessMem(pVCpu, offAccess, cbMem, pvMem, fAccess);
-        }
-    }
-#endif
 
     return VINF_SUCCESS;
@@ -13951 +13932 @@
             int32_t const rcPassUp = pVCpu->iem.s.rcPassUp;
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-            if (   (   rcStrict == VINF_VMX_VMEXIT
-                    || rcStrict == VINF_VMX_MODIFIES_BEHAVIOR)
+            if (   rcStrict == VINF_VMX_VMEXIT
                 && rcPassUp == VINF_SUCCESS)
                 rcStrict = VINF_SUCCESS;
@@ -15701 +15681 @@
  *
  * @returns Strict VBox status code.
- * @retval  VINF_SUCCESS if the MSR access was virtualized.
+ * @retval  VINF_VMX_MODIFIES_BEHAVIOR if the MSR access was virtualized.
  * @retval  VINF_VMX_INTERCEPT_NOT_ACTIVE if the MSR access must be handled by
  *          the x2APIC device.
  * @retval  VERR_OUT_RANGE if the caller must raise \#GP(0).
+ *
  * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
  * @param   idMsr       The MSR being read.
@@ -15714 +15695 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
+    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
     Assert(pu64Value);
 
@@ -15726 +15707 @@
     return iemExecStatusCodeFiddling(pVCpu, rcStrict);
 
+}
+
+
+/**
+ * Interface for HM and EM to virtualize memory-mapped APIC accesses.
+ *
+ * @returns Strict VBox status code.
+ * @retval  VINF_VMX_MODIFIES_BEHAVIOR if the memory access was virtualized.
+ *
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   offAccess   The offset of the register being accessed (within the
+ *                      APIC-access page).
+ * @param   cbAccess    The size of the access in bytes.
+ * @param   pvData      Pointer to the data being written or where to store the data
+ *                      being read.
+ * @param   fWrite      Whether this is a write or read access.
+ * @thread  EMT(pVCpu)
+ */
+VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMem(PVMCPU pVCpu, uint16_t offAccess, size_t cbAccess, void *pvData,
+                                                       bool fWrite)
+{
+    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
+    Assert(pvData);
+
+    /** @todo NSTVMX: Unfortunately, the caller has no idea about instruction fetch
+     *        accesses, so we only use read/write here. Maybe in the future the PGM
+     *        physical handler will be extended to include this information? */
+    uint32_t const fAccess = fWrite ? IEM_ACCESS_TYPE_WRITE : IEM_ACCESS_TYPE_READ;
+    VBOXSTRICTRC rcStrict = iemVmxVirtApicAccessMem(pVCpu, offAccess, cbAccess, pvData, fAccess);
+    if (pVCpu->iem.s.cActiveMappings)
+        iemMemRollback(pVCpu);
+    return iemExecStatusCodeFiddling(pVCpu, rcStrict);
 }
 

trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

@@ -2681 +2681 @@
     PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
     bool const fHostInLongMode = RT_BOOL(pVmcs->u32ExitCtls & VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
+    bool const fVirtApicAccess = RT_BOOL(pVmcs->u32ProcCtls2 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
 
     /* We cannot return from a long-mode guest to a host that is not in long mode. */
@@ -2706 +2707 @@
     /* Clear address range monitoring. */
     EMMonitorWaitClear(pVCpu);
+
+    /* De-register the handler for the APIC-access page. */
+    if (fVirtApicAccess)
+    {
+        RTGCPHYS const GCPhysApicAccess = pVmcs->u64AddrApicAccess.u;
+        int rc = CPUMVmxApicAccessPageDeregister(pVCpu, GCPhysApicAccess);
+        if (RT_FAILURE(rc))
+            return rc;
+    }
 
     /* Perform the VMX transition (PGM updates). */
@@ -4236 +4246 @@
  *
  * @returns VBox strict status code.
+ * @retval VINF_VMX_MODIFIES_BEHAVIOR if the access was virtualized.
+ * @retval VINF_VMX_VMEXIT if the access causes a VM-exit.
+ *
  * @param   pVCpu       The cross context virtual CPU structure.
  * @param   offAccess   The offset of the register being accessed (within the
  *                      APIC-access page).
  * @param   cbAccess    The size of the access in bytes.
- * @param   pvData      Pointer to the data being read or written.
+ * @param   pvData      Pointer to the data being written or where to store the data
+ *                      being read.
  * @param   fAccess     The type of access (must contain IEM_ACCESS_TYPE_READ or
  *                      IEM_ACCESS_TYPE_WRITE or IEM_ACCESS_INSTRUCTION).
@@ -6006 +6020 @@
                 IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic);
         }
+
+        /* Register the handler for the APIC-access page. */
+        int rc = CPUMVmxApicAccessPageRegister(pVCpu, GCPhysApicAccess);
+        if (RT_FAILURE(rc))
+            IEM_VMX_VMENTRY_FAILED_RET(pVCpu, pszInstr, pszFailure, kVmxVDiag_Vmentry_AddrApicAccessHandlerReg);
     }