Changeset 75957 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Dec 5, 2018 8:06:38 AM (6 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAll.cpp
r75830 r75957 15716 15716 15717 15717 /** 15718 * Interface for HM and EM to perform a APIC-write emulation. 15718 * Interface for HM and EM to perform an APIC-write emulation which may cause a 15719 * VM-exit. 15719 15720 * 15720 15721 * @returns Strict VBox status code. … … 15722 15723 * @thread EMT(pVCpu) 15723 15724 */ 15724 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxV irtApicWriteEmulation(PVMCPU pVCpu)15725 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPU pVCpu) 15725 15726 { 15726 15727 IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK); -
trunk/src/VBox/VMM/VMMR3/EM.cpp
r75917 r75957 2111 2111 } 2112 2112 2113 /* SMIs take priority over if we ever support them will have to be injected here. */ 2113 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 2114 /* 2115 * VMX Nested-guest APIC-write VM-exit. 2116 * Takes priority over SMI, INIT signals. 2117 * See Intel spec. 29.4.3.2 "APIC-Write Emulation". 2118 */ 2119 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_VMX_APIC_WRITE)) 2120 { 2121 rc2 = VBOXSTRICTRC_VAL(IEMExecVmxVmexitApicWrite(pVCpu)); 2122 if (rc2 != VINF_VMX_INTERCEPT_NOT_ACTIVE) 2123 UPDATE_RC(); 2124 } 2125 #endif 2126 2127 /** @todo SMIs. If we implement SMIs, this is where they will have to be 2128 * delivered. */ 2114 2129 2115 2130 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX … … 2138 2153 #endif 2139 2154 2140 /** @todo Enable when I get time to test this specific code path later. */2141 #if 02142 2155 /* 2143 2156 * NMIs. … … 2162 2175 } 2163 2176 } 2164 }2165 #endif 2177 UPDATE_RC(); 2178 } 2166 2179 2167 2180 /* 2168 2181 * Interrupts. 2169 2182 */ 2170 bool fWakeupPending = false;2171 2183 if ( !VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY) 2172 2184 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
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