VirtualBox

Changeset 76224 in vbox for trunk/src


Ignore:
Timestamp:
Dec 14, 2018 5:18:44 AM (6 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
127491
Message:

PCnet: Slightly tweaked to add the option of emulating PCnet-ISA, not requiring PCI.

Location:
trunk/src/VBox/Devices
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Network/DevPCNet.cpp

    r76060 r76224  
    99 *      AMD Am79C973/Am79C975 PCnet-FAST III Single-Chip 10/100 Mbps PCI Ethernet Controller datasheet
    1010 *      AMD publication# 20510  Rev:E  Amendment/0  Issue Date: August 2000
     11 * and
     12 *      AMD Am79C960 PCnet-ISA III Single-Chip ISA Single-Chip Ethernet Controller datasheet
     13 *      AMD publication# 16907  Rev:B  Amendment/0  Issue Date: May 1994
    1114 */
    1215
    1316/*
    14  * Copyright (C) 2006-2017 Oracle Corporation
     17 * Copyright (C) 2006-2018 Oracle Corporation
    1518 *
    1619 * This file is part of VirtualBox Open Source Edition (OSE), as
    … …  
    233236/** @name Version for the PCnet/FAST III 79C973 card
    234237 * @{ */
    235 #define CSR_VERSION_LOW_79C973  0x5003  /* the lower two bits must be 11b for AMD */
    236 #define CSR_VERSION_LOW_79C970A 0x1003  /* the lower two bits must be 11b for AMD */
     238#define CSR_VERSION_LOW_79C973  0x5003  /* the lower two bits are always 11b for AMD (JEDEC) */
     239#define CSR_VERSION_LOW_79C970A 0x1003
     240#define CSR_VERSION_LOW_79C960  0x0003
    237241#define CSR_VERSION_HIGH        0x0262
    238242/** @}  */
    … …  
    245249*   Structures and Typedefs                                                                                                      *
    246250*********************************************************************************************************************************/
     251
     252/**
     253 * Emulated device types.
     254 */
     255enum PCNET_DEVICE_TYPE
     256{
     257    DEV_AM79C970A   = 0,    /* PCnet-PCI II (PCI, 10 Mbps). */
     258    DEV_AM79C973    = 1,    /* PCnet-FAST III (PCI, 10/100 Mbps). */
     259    DEV_AM79C960    = 2     /* PCnet-ISA (ISA, 10 Mbps, NE2100/NE1500T compatible) */
     260};
     261
     262#define PCNET_IS_PCI(pcnet) ((pcnet->uDevType == DEV_AM79C970A) || (pcnet->uDevType == DEV_AM79C973))
     263#define PCNET_IS_ISA(pcnet) (pcnet->uDevType == DEV_AM79C960)
     264
     265/*
     266 *  Note: Old adapters, including the original NE2100/NE1500T, used the LANCE (Am7990) or
     267 *  possibly C-LANCE (Am79C90) chips. Those only had the RAP/RDP register and any PROMs were
     268 *  decoded by external circuitry; as a consequence, different vendors used different layouts.
     269 *  Several different variants are known:
     270 *
     271 *   1) Racal Interlan NI6510 (before PCnet-based EtherBlaster variants):
     272 *      - RDP     at iobase + 0x00 (16-bit)
     273 *      - RAP     at iobase + 0x02 (16-bit)
     274 *      - reset   at iobase + 0x04 (8-bit)
     275 *      - config  at iobase + 0x05 (8-bit)
     276 *      - PROM    at iobase + 0x08
     277 *
     278 *   2) BICC Data Networks ISOLAN 4110-2 (ISA) / 4110-3 (MCA):
     279 *      - PROM    at iobase + 0x00
     280 *      - reset   at iobase + 0x04
     281 *      - config  at iobase + 0x05
     282 *      - RDP     at iobase + 0x0c (16-bit)
     283 *      - RAP     at iobase + 0x0e (16-bit)
     284 *
     285 *   3) Novell NE2100/NE1500T, AMD Am2100, all PCnet chips:
     286 *      - PROM    at iobase + 0x00
     287 *      - RDP     at iobase + 0x10 (16-bit)
     288 *      - RAP     at iobase + 0x12 (16-bit)
     289 *      - reset   at iobase + 0x14 (16-bit)
     290 *      - BDP/IDP at iobase + 0x16 (16-bit)
     291 *
     292 * There were also non-busmastering LANCE adapters, such as the BICC 4110-1, DEC DEPCA,
     293 * or NTI 16. Those are uninteresting.
     294 */
     295
    247296/**
    248297 * PCNET state.
    … …  
    316365    /** Alignment padding. */
    317366    uint32_t                            Alignment1;
     367
    318368    /** Register Address Pointer */
    319369    uint32_t                            u32RAP;
    … …  
    343393    uint8_t                             abRecvBuf[4096];
    344394
     395    /** The configured IRQ for ISA operation. */
     396    uint8_t                             uIsaIrq;
    345397    /** Alignment padding. */
    346     uint32_t                            Alignment2;
     398    uint8_t                             Alignment2[3];
    347399
    348400    /** Size of a RX/TX descriptor (8 or 16 bytes according to SWSTYLE */
    … …  
    353405    /** Base address of the MMIO region. */
    354406    RTGCPHYS32                          MMIOBase;
    355     /** Base port of the I/O space region. */
     407
     408    /** Base port of the I/O space region (PCI). */
    356409    RTIOPORT                            IOPortBase;
    357410    /** If set the link is currently up. */
    … …  
    364417    /** The configured MAC address. */
    365418    RTMAC                               MacConfigured;
    366     /** Alignment padding. */
    367     uint8_t                             Alignment3[2];
     419    /** Base port of the I/O space region (ISA). */
     420    RTIOPORT                            IOPortBaseISA;
    368421
    369422    /** The LED. */
    … …  
    403456    /* True if R0 context is enabled. */
    404457    bool                                fR0Enabled;
    405     /* True: Emulate Am79C973. False: Emulate 79C970A. */
    406     bool                                fAm79C973;
     458    /* Emulated device type. */
     459    uint8_t                             uDevType;
     460    /* Backwards compatible shared memory region. */
     461    bool                                fSharedRegion;
    407462    /* Link speed to be reported through CSR68. */
    408     bool                                fSharedRegion;
    409     /* Alignment padding. */
    410463    uint32_t                            u32LinkSpeed;
    411464    /* MS to wait before we enable the link. */
    … …  
    660713
    661714/**
     715 * Memory write helper to handle PCI/ISA differences.
     716 *
     717 * @returns nothing.
     718 * @param   pThis       Pointer to the BusLogic device instance
     719 * @param   GCPhys      Guest physical memory address
     720 * @param   pvBuf       Host side buffer address
     721 * @param   cbWrite     Number of bytes to write
     722 */
     723static void pcnetPhysWrite(PPCNETSTATE pThis, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
     724{
     725    if (!PCNET_IS_ISA(pThis))
     726        PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvBuf, cbWrite);
     727    else
     728        PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns), GCPhys, pvBuf, cbWrite);
     729}
     730
     731/**
    662732 * Load transmit message descriptor
    663733 * Make sure we read the own flag first.
    … …  
    723793{
    724794    STAM_PROFILE_ADV_START(&pThis->CTX_SUFF_Z(StatTmdStore), a);
    725     PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
    726795    if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
    727796    {
    … …  
    732801        xda[3] =   ((uint32_t *)tmd)[2] >> 16;
    733802        xda[1] |=  0x8000;
    734         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
     803        pcnetPhysWrite(pThis, addr, (void*)&xda[0], sizeof(xda));
    735804        xda[1] &= ~0x8000;
    736         PDMDevHlpPCIPhysWrite(pDevIns, addr+3, (uint8_t*)xda + 3, 1);
     805        pcnetPhysWrite(pThis, addr+3, (uint8_t*)xda + 3, 1);
    737806    }
    738807    else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
    739808    {
    740809        ((uint32_t*)tmd)[1] |=  0x80000000;
    741         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)tmd, 16);
     810        pcnetPhysWrite(pThis, addr, (void*)tmd, 16);
    742811        ((uint32_t*)tmd)[1] &= ~0x80000000;
    743         PDMDevHlpPCIPhysWrite(pDevIns, addr+7, (uint8_t*)tmd + 7, 1);
     812        pcnetPhysWrite(pThis, addr+7, (uint8_t*)tmd + 7, 1);
    744813    }
    745814    else
    … …  
    751820        xda[3] = ((uint32_t *)tmd)[3];
    752821        xda[1] |=  0x80000000;
    753         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)&xda[0], sizeof(xda));
     822        pcnetPhysWrite(pThis, addr, (void*)&xda[0], sizeof(xda));
    754823        xda[1] &= ~0x80000000;
    755         PDMDevHlpPCIPhysWrite(pDevIns, addr+7, (uint8_t*)xda + 7, 1);
     824        pcnetPhysWrite(pThis, addr+7, (uint8_t*)xda + 7, 1);
    756825    }
    757826    STAM_PROFILE_ADV_STOP(&pThis->CTX_SUFF_Z(StatTmdStore), a);
    … …  
    821890DECLINLINE(void) pcnetRmdStorePassHost(PPCNETSTATE pThis, RMD *rmd, RTGCPHYS32 addr)
    822891{
    823     PPDMDEVINS pDevIns = PCNETSTATE_2_DEVINS(pThis);
    824892    if (RT_UNLIKELY(BCR_SWSTYLE(pThis) == 0))
    825893    {
    … …  
    830898        rda[3] =   ((uint32_t *)rmd)[2]      & 0xffff;
    831899        rda[1] |=  0x8000;
    832         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
     900        pcnetPhysWrite(pThis, addr, (void*)&rda[0], sizeof(rda));
    833901        rda[1] &= ~0x8000;
    834         PDMDevHlpPCIPhysWrite(pDevIns, addr+3, (uint8_t*)rda + 3, 1);
     902        pcnetPhysWrite(pThis, addr+3, (uint8_t*)rda + 3, 1);
    835903    }
    836904    else if (RT_LIKELY(BCR_SWSTYLE(pThis) != 3))
    837905    {
    838906        ((uint32_t*)rmd)[1] |=  0x80000000;
    839         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)rmd, 16);
     907        pcnetPhysWrite(pThis, addr, (void*)rmd, 16);
    840908        ((uint32_t*)rmd)[1] &= ~0x80000000;
    841         PDMDevHlpPCIPhysWrite(pDevIns, addr+7, (uint8_t*)rmd + 7, 1);
     909        pcnetPhysWrite(pThis, addr+7, (uint8_t*)rmd + 7, 1);
    842910    }
    843911    else
    … …  
    849917        rda[3] = ((uint32_t *)rmd)[3];
    850918        rda[1] |=  0x80000000;
    851         PDMDevHlpPCIPhysWrite(pDevIns, addr, (void*)&rda[0], sizeof(rda));
     919        pcnetPhysWrite(pThis, addr, (void*)&rda[0], sizeof(rda));
    852920        rda[1] &= ~0x80000000;
    853         PDMDevHlpPCIPhysWrite(pDevIns, addr+7, (uint8_t*)rda + 7, 1);
     921        pcnetPhysWrite(pThis, addr+7, (uint8_t*)rda + 7, 1);
    854922    }
    855923}
    … …  
    870938        cbDesc = 16;
    871939    PDMDevHlpPhysRead(pDevIns, addr, aBuf, cbDesc);
    872     PDMDevHlpPCIPhysWrite(pDevIns, addr, aBuf, cbDesc);
     940    pcnetPhysWrite(pThis, addr, aBuf, cbDesc);
    873941}
    874942#endif /* IN_RING3 */
    … …  
    12271295    CSR_XMTRL(pThis) = 1;
    12281296    pThis->aCSR[80]  = 0x1410;
    1229     pThis->aCSR[88]  = pThis->fAm79C973 ? CSR_VERSION_LOW_79C973 : CSR_VERSION_LOW_79C970A;
    1230     pThis->aCSR[89]  = CSR_VERSION_HIGH;
     1297    switch (pThis->uDevType)
     1298    {
     1299    default:
     1300    case DEV_AM79C970A:
     1301        pThis->aCSR[88] = CSR_VERSION_LOW_79C970A;
     1302        pThis->aCSR[89] = CSR_VERSION_HIGH;
     1303        break;
     1304    case DEV_AM79C973:
     1305        pThis->aCSR[88] = CSR_VERSION_LOW_79C973;
     1306        pThis->aCSR[89] = CSR_VERSION_HIGH;
     1307        break;
     1308    case DEV_AM79C960:
     1309        pThis->aCSR[88] = CSR_VERSION_LOW_79C960;
     1310        pThis->aCSR[89] = 0x0000;
     1311        break;
     1312    }
    12311313    pThis->aCSR[94]  = 0x0000;
    12321314    pThis->aCSR[100] = 0x0200;
    … …  
    13231405    if (RT_UNLIKELY(iISR != pThis->iISR))
    13241406    {
    1325         Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));
    1326         PDMDevHlpPCISetIrq(PCNETSTATE_2_DEVINS(pThis), 0, iISR);
     1407        if (!PCNET_IS_ISA(pThis))
     1408        {
     1409            Log(("#%d INTA=%d\n", PCNET_INST_NR, iISR));
     1410            PDMDevHlpPCISetIrq(PCNETSTATE_2_DEVINS(pThis), 0, iISR);
     1411        }
     1412        else
     1413        {
     1414            Log(("#%d IRQ=%d, state=%d\n", PCNET_INST_NR, pThis->uIsaIrq, iISR));
     1415            PDMDevHlpISASetIrq(PCNETSTATE_2_DEVINS(pThis), pThis->uIsaIrq, iISR);
     1416        }
    13271417        pThis->iISR = iISR;
    13281418    }
    … …  
    19041994             */
    19051995            PDMCritSectLeave(&pThis->CritSect);
    1906             PDMDevHlpPCIPhysWrite(pDevIns, rbadr, src, cbBuf);
     1996            pcnetPhysWrite(pThis, rbadr, src, cbBuf);
    19071997            int rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
    19081998            AssertReleaseRC(rc);
    … …  
    19512041                 * handler associated with it. See above for additional comments. */
    19522042                PDMCritSectLeave(&pThis->CritSect);
    1953                 PDMDevHlpPCIPhysWrite(pDevIns, rbadr2, src, cbBuf);
     2043                pcnetPhysWrite(pThis, rbadr2, src, cbBuf);
    19542044                rc = PDMCritSectEnter(&pThis->CritSect, VERR_SEM_BUSY);
    19552045                AssertReleaseRC(rc);
    … …  
    30773167            val &= 0xffff;
    30783168            pThis->aBCR[BCR_STVAL] = val;
    3079             if (pThis->fAm79C973)
     3169            if (pThis->uDevType == DEV_AM79C973)
    30803170                TMTimerSetNano(pThis->CTX_SUFF(pTimerSoftInt), 12800U * val);
    30813171            break;
    … …  
    32303320
    32313321        case BCR_MIIMDR:
    3232             if (pThis->fAm79C973 && (pThis->aBCR[BCR_MIIADDR] >> 5 & 0x1f) == 0)
     3322            if ((pThis->uDevType == DEV_AM79C973) && (pThis->aBCR[BCR_MIIADDR] >> 5 & 0x1f) == 0)
    32333323            {
    32343324                uint32_t miiaddr = pThis->aBCR[BCR_MIIADDR] & 0x1f;
    … …  
    32593349    memcpy(pThis->aPROM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
    32603350    pThis->aPROM[ 8] = 0x00;
    3261     pThis->aPROM[ 9] = 0x11;
     3351    pThis->aPROM[ 9] = 0x00;    /* 0x00/0xFF=ISA, 0x01=PnP, 0x10=VLB, 0x11=PCI */
    32623352    pThis->aPROM[12] = pThis->aPROM[13] = 0x00;
    32633353    pThis->aPROM[14] = pThis->aPROM[15] = 0x57;
    … …  
    39754065     * Show info.
    39764066     */
     4067    const char *pcszModel;
     4068    switch (pThis->uDevType)
     4069    {
     4070    case DEV_AM79C970A: pcszModel = "AM79C970A";    break;
     4071    case DEV_AM79C973:  pcszModel = "AM79C973";     break;
     4072    case DEV_AM79C960:  pcszModel = "AM79C960";     break;
     4073    default:            pcszModel = "Unknown";      break;
     4074    }
    39774075    pHlp->pfnPrintf(pHlp,
    39784076                    "pcnet #%d: port=%RTiop mmio=%RX32 mac-cfg=%RTmac %s%s%s\n",
    39794077                    pDevIns->iInstance,
    39804078                    pThis->IOPortBase, pThis->MMIOBase, &pThis->MacConfigured,
    3981                     pThis->fAm79C973 ? "Am79C973" : "Am79C970A", pThis->fGCEnabled ? " RC" : "", pThis->fR0Enabled ? " R0" : "");
     4079                    pcszModel, pThis->fGCEnabled ? " RC" : "", pThis->fR0Enabled ? " R0" : "");
    39824080
    39834081    PDMCritSectEnter(&pThis->CritSect, VERR_INTERNAL_ERROR); /* Take it here so we know why we're hanging... */
    … …  
    42174315{
    42184316    SSMR3PutMem(pSSM, &pThis->MacConfigured, sizeof(pThis->MacConfigured));
    4219     SSMR3PutBool(pSSM, pThis->fAm79C973);                   /* >= If version 0.8 */
     4317    SSMR3PutU8(pSSM, pThis->uDevType);
    42204318    SSMR3PutU32(pSSM, pThis->u32LinkSpeed);
    42214319}
    … …  
    42804378        return rc;
    42814379#endif
    4282     if (pThis->fAm79C973)
     4380    if (pThis->uDevType == DEV_AM79C973)
    42834381        rc = TMR3TimerSave(pThis->CTX_SUFF(pTimerSoftInt), pSSM);
    42844382    return rc;
    … …  
    43714469        LogRel(("PCnet#%u: The mac address differs: config=%RTmac saved=%RTmac\n", PCNET_INST_NR, &pThis->MacConfigured, &Mac));
    43724470
    4373     bool        fAm79C973;
    4374     rc = SSMR3GetBool(pSSM, &fAm79C973);
     4471    uint8_t     uDevType;
     4472    rc = SSMR3GetU8(pSSM, &uDevType);
    43754473    AssertRCReturn(rc, rc);
    4376     if (pThis->fAm79C973 != fAm79C973)
    4377         return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The fAm79C973 flag differs: config=%RTbool saved=%RTbool"), pThis->fAm79C973, fAm79C973);
     4474    if (pThis->uDevType != uDevType)
     4475        return SSMR3SetCfgError(pSSM, RT_SRC_POS, N_("The uDevType setting differs: config=%u saved=%u"), pThis->uDevType, uDevType);
    43784476
    43794477    uint32_t    u32LinkSpeed;
    … …  
    43904488        TMR3TimerLoad(pThis->CTX_SUFF(pTimerPoll), pSSM);
    43914489#endif
    4392         if (pThis->fAm79C973)
     4490        if (pThis->uDevType == DEV_AM79C973)
    43934491        {
    43944492            if (   SSM_VERSION_MAJOR(uVersion) >  0
    … …  
    48434941    pThis->pTimerPollRC  = TMTimerRCPtr(pThis->pTimerPollR3);
    48444942#endif
    4845     if (pThis->fAm79C973)
     4943    if (pThis->uDevType == DEV_AM79C973)
    48464944        pThis->pTimerSoftIntRC = TMTimerRCPtr(pThis->pTimerSoftIntR3);
    48474945}
    … …  
    48904988     * Validate configuration.
    48914989     */
    4892     if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "Am79C973\0" "LineSpeed\0" "GCEnabled\0" "R0Enabled\0" "PrivIfEnabled\0" "LinkUpDelay\0"))
     4990    if (!CFGMR3AreValuesValid(pCfg, "MAC\0" "CableConnected\0" "Am79C973\0" "ChipType\0" "LineSpeed\0" "GCEnabled\0" "R0Enabled\0" "PrivIfEnabled\0" "LinkUpDelay\0"))
    48934991        return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
    48944992                                N_("Invalid configuration for pcnet device"));
    … …  
    49065004                                N_("Configuration error: Failed to get the \"CableConnected\" value"));
    49075005
    4908     rc = CFGMR3QueryBoolDef(pCfg, "Am79C973", &pThis->fAm79C973, false);
     5006    /*
     5007     * Determine the model.
     5008     */
     5009    char szChipType[16];
     5010    rc = CFGMR3QueryStringDef(pCfg, "ChipType", &szChipType[0], sizeof(szChipType), "Am79C970A");
     5011    if (RT_FAILURE(rc))
     5012        return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
     5013                                N_("Configuration error: Querying \"ChipType\" as string failed"));
     5014
     5015    if (!strcmp(szChipType, "Am79C970A"))
     5016        pThis->uDevType = DEV_AM79C970A;    /* 10 Mbps PCnet-PCI II. */
     5017    else if (!strcmp(szChipType, "Am79C973"))
     5018        pThis->uDevType = DEV_AM79C970A;    /* 10/100 Mbps PCnet-FAST III. */
     5019    else if (!strcmp(szChipType, "Am79C960"))
     5020        pThis->uDevType = DEV_AM79C960;     /* 10 Mbps PCnet-ISA, NE2100/Am2100 compatible. */
     5021    else
     5022    {
     5023        return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS,
     5024                                   N_("Configuration error: The \"ChipType\" value \"%s\" is unsupported"),
     5025                                   szChipType);
     5026    }
     5027
     5028
     5029    /*
     5030     * Process the old model configuration. If present, it must take precedence for saved state compatibility.
     5031     */
     5032    bool fAm79C973;
     5033    rc = CFGMR3QueryBoolDef(pCfg, "Am79C973", &fAm79C973, false);
    49095034    if (RT_FAILURE(rc))
    49105035        return PDMDEV_SET_ERROR(pDevIns, rc,
    49115036                                N_("Configuration error: Failed to get the \"Am79C973\" value"));
     5037    if (fAm79C973)
     5038        pThis->uDevType = DEV_AM79C973;
     5039
     5040    /*
     5041     * Process ISA configuration options. The defaults are chosen to be NE2100/Am2100 compatible.
     5042     */
     5043    rc = CFGMR3QueryPortDef(pCfg, "Port", &pThis->IOPortBaseISA, 0x300);
     5044    if (RT_FAILURE(rc))
     5045        return PDMDEV_SET_ERROR(pDevIns, rc,
     5046                                N_("Configuration error: Failed to get the \"Port\" value"));
     5047
     5048    rc = CFGMR3QueryU8Def(pCfg, "IRQ", &pThis->uIsaIrq, 3);
     5049    if (RT_FAILURE(rc))
     5050        return PDMDEV_SET_ERROR(pDevIns, rc,
     5051                                N_("Configuration error: Failed to get the \"IRQ\" value"));
    49125052
    49135053    rc = CFGMR3QueryU32Def(pCfg, "LineSpeed", &pThis->u32LinkSpeed, 1000000); /* 1GBit/s (in kbps units)*/
    … …  
    49735113    pThis->PciDev.abConfig[0x06] = 0x80; /* status */
    49745114    pThis->PciDev.abConfig[0x07] = 0x02;
    4975     pThis->PciDev.abConfig[0x08] = pThis->fAm79C973 ? 0x40 : 0x10; /* revision */
     5115    pThis->PciDev.abConfig[0x08] = pThis->uDevType == DEV_AM79C973 ? 0x40 : 0x10; /* revision */
    49765116    pThis->PciDev.abConfig[0x09] = 0x00;
    49775117    pThis->PciDev.abConfig[0x0a] = 0x00; /* ethernet network controller */
    … …  
    50115151     * Register the PCI device, its I/O regions, the timer and the saved state item.
    50125152     */
    5013     rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
    5014     if (RT_FAILURE(rc))
    5015         return rc;
    5016     rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, PCNET_IOPORT_SIZE,  PCI_ADDRESS_SPACE_IO,  pcnetIOPortMap);
    5017     if (RT_FAILURE(rc))
    5018         return rc;
    5019     rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, PCNET_PNPMMIO_SIZE, PCI_ADDRESS_SPACE_MEM, pcnetMMIOMap);
    5020     if (RT_FAILURE(rc))
    5021         return rc;
     5153    if (PCNET_IS_PCI(pThis))
     5154    {
     5155        rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
     5156        if (RT_FAILURE(rc))
     5157            return rc;
     5158        rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, PCNET_IOPORT_SIZE,  PCI_ADDRESS_SPACE_IO,  pcnetIOPortMap);
     5159        if (RT_FAILURE(rc))
     5160            return rc;
     5161        rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1, PCNET_PNPMMIO_SIZE, PCI_ADDRESS_SPACE_MEM, pcnetMMIOMap);
     5162        if (RT_FAILURE(rc))
     5163            return rc;
     5164    }
     5165
     5166    /*
     5167     * Register ISA I/O ranges for PCnet-ISA.
     5168     */
     5169    if (PCNET_IS_ISA(pThis))
     5170    {
     5171        rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBaseISA, 0x10, 0, pcnetIOPortAPromWrite,
     5172                                     pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM");
     5173        if (RT_FAILURE(rc))
     5174            return rc;
     5175        rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBaseISA + 0x10, 0x10, 0, pcnetIOPortWrite,
     5176                                     pcnetIOPortRead, NULL, NULL, "PCnet");
     5177        if (RT_FAILURE(rc))
     5178            return rc;
     5179
     5180        if (pThis->fGCEnabled)
     5181        {
     5182            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBaseISA, 0x10, 0, "pcnetIOPortAPromWrite",
     5183                                           "pcnetIOPortAPromRead", NULL, NULL, "PCnet APROM");
     5184            if (RT_FAILURE(rc))
     5185                return rc;
     5186            rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBaseISA + 0x10, 0x10, 0, "pcnetIOPortWrite",
     5187                                           "pcnetIOPortRead", NULL, NULL, "PCnet");
     5188            if (RT_FAILURE(rc))
     5189                return rc;
     5190        }
     5191        if (pThis->fR0Enabled)
     5192        {
     5193            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBaseISA, 0x10, 0, "pcnetIOPortAPromWrite",
     5194                                           "pcnetIOPortAPromRead", NULL, NULL, "PCnet APROM");
     5195            if (RT_FAILURE(rc))
     5196                return rc;
     5197            rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBaseISA + 0x10, 0x10, 0, "pcnetIOPortWrite",
     5198                                           "pcnetIOPortRead", NULL, NULL, "PCnet");
     5199            if (RT_FAILURE(rc))
     5200                return rc;
     5201        }
     5202
     5203    }
     5204
    50225205
    50235206#ifdef PCNET_NO_POLLING
    … …  
    50475230    TMR3TimerSetCritSect(pThis->pTimerPollR3, &pThis->CritSect);
    50485231#endif
    5049     if (pThis->fAm79C973)
     5232    if (pThis->uDevType == DEV_AM79C973)
    50505233    {
    50515234        /* Software Interrupt timer */

  • trunk/src/VBox/Devices/testcase/tstDeviceStructSizeRC.cpp

    r76180 r76224  
    596596    GEN_CHECK_OFF(PCNETSTATE, fGCEnabled);
    597597    GEN_CHECK_OFF(PCNETSTATE, fR0Enabled);
    598     GEN_CHECK_OFF(PCNETSTATE, fAm79C973);
    599     GEN_CHECK_OFF(PCNETSTATE, u32LinkSpeed);
     598    GEN_CHECK_OFF(PCNETSTATE, uDevType);
    600599    GEN_CHECK_OFF(PCNETSTATE, StatReceiveBytes);
    601600    GEN_CHECK_OFF(PCNETSTATE, StatTransmitBytes);
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