VirtualBox

Changeset 76397 in vbox


Ignore:
Timestamp:
Dec 23, 2018 2:32:01 PM (6 years ago)
Author:
vboxsync
Message:

VBox/vmm/hm_svm.h,hm_vmx.h: Try avoid including VBox/err.h in widely used headers, so split out the inline stuff from hm_vmx.h into hmvmxinline.h. bugref:9344

Location:
trunk
Files:
15 edited
1 copied

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/hm_svm.h

    r76311 r76397  
    2828
    2929#include <VBox/types.h>
    30 #include <VBox/err.h>
    3130#include <iprt/assert.h>
    3231#include <iprt/asm.h>

  • trunk/include/VBox/vmm/hm_vmx.h

    r76198 r76397  
    2828
    2929#include <VBox/types.h>
    30 #include <VBox/err.h>
    3130#include <iprt/x86.h>
    32 #include <iprt/assert.h>
     31#include <iprt/assertcompile.h>
    3332
    3433/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
    … …  
    40644063
    40654064
    4066 /** @defgroup grp_hm_vmx_inline    VMX Inline Helpers
    4067  * @{
    4068  */
    4069 /**
    4070  * Gets the effective width of a VMCS field given it's encoding adjusted for
    4071  * HIGH/FULL access for 64-bit fields.
    4072  *
    4073  * @returns The effective VMCS field width.
    4074  * @param   uFieldEnc   The VMCS field encoding.
    4075  *
    4076  * @remarks Warning! This function does not verify the encoding is for a valid and
    4077  *          supported VMCS field.
    4078  */
    4079 DECLINLINE(uint8_t) HMVmxGetVmcsFieldWidthEff(uint32_t uFieldEnc)
    4080 {
    4081     /* Only the "HIGH" parts of all 64-bit fields have bit 0 set. */
    4082     if (uFieldEnc & RT_BIT(0))
    4083         return VMXVMCSFIELDWIDTH_32BIT;
    4084 
    4085     /* Bits 13:14 contains the width of the VMCS field, see VMXVMCSFIELDWIDTH_XXX. */
    4086     return (uFieldEnc >> 13) & 0x3;
    4087 }
    4088 
    4089 /**
    4090  * Returns whether the given VMCS field is a read-only VMCS field or not.
    4091  *
    4092  * @returns @c true if it's a read-only field, @c false otherwise.
    4093  * @param   uFieldEnc   The VMCS field encoding.
    4094  *
    4095  * @remarks Warning! This function does not verify the encoding is for a valid and
    4096  *          supported VMCS field.
    4097  */
    4098 DECLINLINE(bool) HMVmxIsVmcsFieldReadOnly(uint32_t uFieldEnc)
    4099 {
    4100     /* See Intel spec. B.4.2 "Natural-Width Read-Only Data Fields". */
    4101     return (RT_BF_GET(uFieldEnc, VMX_BF_VMCS_ENC_TYPE) == VMXVMCSFIELDTYPE_VMEXIT_INFO);
    4102 }
    4103 
    4104 /**
    4105  * Returns whether the given VM-entry interruption-information type is valid or not.
    4106  *
    4107  * @returns @c true if it's a valid type, @c false otherwise.
    4108  * @param   fSupportsMTF    Whether the Monitor-Trap Flag CPU feature is supported.
    4109  * @param   uType           The VM-entry interruption-information type.
    4110  */
    4111 DECLINLINE(bool) HMVmxIsEntryIntInfoTypeValid(bool fSupportsMTF, uint8_t uType)
    4112 {
    4113     /* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
    4114     switch (uType)
    4115     {
    4116         case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
    4117         case VMX_ENTRY_INT_INFO_TYPE_NMI:
    4118         case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
    4119         case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
    4120         case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
    4121         case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:           return true;
    4122         case VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT:       return fSupportsMTF;
    4123         default:
    4124             return false;
    4125     }
    4126 }
    4127 
    4128 /**
    4129  * Returns whether the given VM-entry interruption-information vector and type
    4130  * combination is valid or not.
    4131  *
    4132  * @returns @c true if it's a valid vector/type combination, @c false otherwise.
    4133  * @param   uVector     The VM-entry interruption-information vector.
    4134  * @param   uType       The VM-entry interruption-information type.
    4135  *
    4136  * @remarks Warning! This function does not validate the type field individually.
    4137  *          Use it after verifying type is valid using HMVmxIsEntryIntInfoTypeValid.
    4138  */
    4139 DECLINLINE(bool) HMVmxIsEntryIntInfoVectorValid(uint8_t uVector, uint8_t uType)
    4140 {
    4141     /* See Intel spec. 26.2.1.3 "VM-Entry Control Fields". */
    4142     if (   uType == VMX_ENTRY_INT_INFO_TYPE_NMI
    4143         && uVector != X86_XCPT_NMI)
    4144         return false;
    4145     if (   uType == VMX_ENTRY_INT_INFO_TYPE_HW_XCPT
    4146         && uVector > X86_XCPT_LAST)
    4147         return false;
    4148     if (   uType == VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT
    4149         && uVector != VMX_ENTRY_INT_INFO_VECTOR_MTF)
    4150         return false;
    4151     return true;
    4152 }
    4153 
    4154 
    4155 /**
    4156  * Returns whether or not the VM-exit is trap-like or fault-like.
    4157  *
    4158  * @returns @c true if it's a trap-like VM-exit, @c false otherwise.
    4159  * @param   uExitReason     The VM-exit reason.
    4160  *
    4161  * @remarks Warning! This does not validate the VM-exit reason.
    4162  */
    4163 DECLINLINE(bool) HMVmxIsVmexitTrapLike(uint32_t uExitReason)
    4164 {
    4165     /*
    4166      * Trap-like VM-exits - The instruction causing the VM-exit completes before the
    4167      * VM-exit occurs.
    4168      *
    4169      * Fault-like VM-exits - The instruction causing the VM-exit is not completed before
    4170      * the VM-exit occurs.
    4171      *
    4172      * See Intel spec. 25.5.2 "Monitor Trap Flag".
    4173      * See Intel spec. 29.1.4 "EOI Virtualization".
    4174      * See Intel spec. 29.4.3.3 "APIC-Write VM Exits".
    4175      * See Intel spec. 29.1.2 "TPR Virtualization".
    4176      */
    4177     /** @todo NSTVMX: r=ramshankar: What about VM-exits due to debug traps (single-step,
    4178      *        I/O breakpoints, data breakpoints), debug exceptions (data breakpoint)
    4179      *        delayed by MovSS blocking, machine-check exceptions. */
    4180     switch (uExitReason)
    4181     {
    4182         case VMX_EXIT_MTF:
    4183         case VMX_EXIT_VIRTUALIZED_EOI:
    4184         case VMX_EXIT_APIC_WRITE:
    4185         case VMX_EXIT_TPR_BELOW_THRESHOLD:
    4186             return true;
    4187     }
    4188     return false;
    4189 }
    4190 
    4191 
    4192 /**
    4193  * Returns whether the VM-entry is vectoring or not given the VM-entry interruption
    4194  * information field.
    4195  *
    4196  * @returns @c true if the VM-entry is vectoring, @c false otherwise.
    4197  * @param   uEntryIntInfo       The VM-entry interruption information field.
    4198  * @param   pEntryIntInfoType   The VM-entry interruption information type field.
    4199  *                              Optional, can be NULL. Only updated when this
    4200  *                              function returns @c true.
    4201  */
    4202 DECLINLINE(bool) HMVmxIsVmentryVectoring(uint32_t uEntryIntInfo, uint8_t *pEntryIntInfoType)
    4203 {
    4204     /*
    4205      * The definition of what is a vectoring VM-entry is taken
    4206      * from Intel spec. 26.6 "Special Features of VM Entry".
    4207      */
    4208     if (!VMX_ENTRY_INT_INFO_IS_VALID(uEntryIntInfo))
    4209         return false;
    4210 
    4211     /* Scope and keep variable defines on top to satisy archaic c89 nonsense. */
    4212     {
    4213         uint8_t const uType = VMX_ENTRY_INT_INFO_TYPE(uEntryIntInfo);
    4214         switch (uType)
    4215         {
    4216             case VMX_ENTRY_INT_INFO_TYPE_EXT_INT:
    4217             case VMX_ENTRY_INT_INFO_TYPE_NMI:
    4218             case VMX_ENTRY_INT_INFO_TYPE_HW_XCPT:
    4219             case VMX_ENTRY_INT_INFO_TYPE_SW_INT:
    4220             case VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT:
    4221             case VMX_ENTRY_INT_INFO_TYPE_SW_XCPT:
    4222             {
    4223                 if (pEntryIntInfoType)
    4224                     *pEntryIntInfoType = uType;
    4225                 return true;
    4226             }
    4227         }
    4228     }
    4229     return false;
    4230 }
    4231 /** @} */
    4232 
    4233 
    4234 /** @defgroup grp_hm_vmx_c    VMX Assembly Helpers
     4065/** @defgroup grp_hm_vmx_c    VMX C Helpers
    42354066 *
    42364067 * These are functions that strictly only implement VT-x functionality that is in
    … …  
    42474078
    42484079
    4249 /** @defgroup grp_hm_vmx_asm    VMX Assembly Helpers
    4250  * @{
    4251  */
    4252 
    4253 /**
    4254  * Restores some host-state fields that need not be done on every VM-exit.
    4255  *
    4256  * @returns VBox status code.
    4257  * @param   fRestoreHostFlags   Flags of which host registers needs to be
    4258  *                              restored.
    4259  * @param   pRestoreHost        Pointer to the host-restore structure.
    4260  */
    4261 DECLASM(int) VMXRestoreHostState(uint32_t fRestoreHostFlags, PVMXRESTOREHOST pRestoreHost);
    4262 
    4263 
    4264 /**
    4265  * Dispatches an NMI to the host.
    4266  */
    4267 DECLASM(int) VMXDispatchHostNmi(void);
    4268 
    4269 
    4270 /**
    4271  * Executes VMXON.
    4272  *
    4273  * @returns VBox status code.
    4274  * @param   HCPhysVmxOn      Physical address of VMXON structure.
    4275  */
    4276 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4277 DECLASM(int) VMXEnable(RTHCPHYS HCPhysVmxOn);
    4278 #else
    4279 DECLINLINE(int) VMXEnable(RTHCPHYS HCPhysVmxOn)
    4280 {
    4281 # if RT_INLINE_ASM_GNU_STYLE
    4282     int rc = VINF_SUCCESS;
    4283     __asm__ __volatile__ (
    4284        "push     %3                                             \n\t"
    4285        "push     %2                                             \n\t"
    4286        ".byte    0xf3, 0x0f, 0xc7, 0x34, 0x24  # VMXON [esp]    \n\t"
    4287        "ja       2f                                             \n\t"
    4288        "je       1f                                             \n\t"
    4289        "movl     $" RT_XSTR(VERR_VMX_INVALID_VMXON_PTR)", %0    \n\t"
    4290        "jmp      2f                                             \n\t"
    4291        "1:                                                      \n\t"
    4292        "movl     $" RT_XSTR(VERR_VMX_VMXON_FAILED)", %0         \n\t"
    4293        "2:                                                      \n\t"
    4294        "add      $8, %%esp                                      \n\t"
    4295        :"=rm"(rc)
    4296        :"0"(VINF_SUCCESS),
    4297         "ir"((uint32_t)HCPhysVmxOn),        /* don't allow direct memory reference here, */
    4298         "ir"((uint32_t)(HCPhysVmxOn >> 32)) /* this would not work with -fomit-frame-pointer */
    4299        :"memory"
    4300        );
    4301     return rc;
    4302 
    4303 # elif VMX_USE_MSC_INTRINSICS
    4304     unsigned char rcMsc = __vmx_on(&HCPhysVmxOn);
    4305     if (RT_LIKELY(rcMsc == 0))
    4306         return VINF_SUCCESS;
    4307     return rcMsc == 2 ? VERR_VMX_INVALID_VMXON_PTR : VERR_VMX_VMXON_FAILED;
    4308 
    4309 # else
    4310     int rc = VINF_SUCCESS;
    4311     __asm
    4312     {
    4313         push    dword ptr [HCPhysVmxOn + 4]
    4314         push    dword ptr [HCPhysVmxOn]
    4315         _emit   0xf3
    4316         _emit   0x0f
    4317         _emit   0xc7
    4318         _emit   0x34
    4319         _emit   0x24     /* VMXON [esp] */
    4320         jnc     vmxon_good
    4321         mov     dword ptr [rc], VERR_VMX_INVALID_VMXON_PTR
    4322         jmp     the_end
    4323 
    4324 vmxon_good:
    4325         jnz     the_end
    4326         mov     dword ptr [rc], VERR_VMX_VMXON_FAILED
    4327 the_end:
    4328         add     esp, 8
    4329     }
    4330     return rc;
    4331 # endif
    4332 }
     4080/** @} */
     4081
    43334082#endif
    43344083
    4335 
    4336 /**
    4337  * Executes VMXOFF.
    4338  */
    4339 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4340 DECLASM(void) VMXDisable(void);
    4341 #else
    4342 DECLINLINE(void) VMXDisable(void)
    4343 {
    4344 # if RT_INLINE_ASM_GNU_STYLE
    4345     __asm__ __volatile__ (
    4346        ".byte 0x0f, 0x01, 0xc4  # VMXOFF                        \n\t"
    4347        );
    4348 
    4349 # elif VMX_USE_MSC_INTRINSICS
    4350     __vmx_off();
    4351 
    4352 # else
    4353     __asm
    4354     {
    4355         _emit   0x0f
    4356         _emit   0x01
    4357         _emit   0xc4   /* VMXOFF */
    4358     }
    4359 # endif
    4360 }
    4361 #endif
    4362 
    4363 
    4364 /**
    4365  * Executes VMCLEAR.
    4366  *
    4367  * @returns VBox status code.
    4368  * @param   HCPhysVmcs       Physical address of VM control structure.
    4369  */
    4370 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4371 DECLASM(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs);
    4372 #else
    4373 DECLINLINE(int) VMXClearVmcs(RTHCPHYS HCPhysVmcs)
    4374 {
    4375 # if RT_INLINE_ASM_GNU_STYLE
    4376     int rc = VINF_SUCCESS;
    4377     __asm__ __volatile__ (
    4378        "push    %3                                              \n\t"
    4379        "push    %2                                              \n\t"
    4380        ".byte   0x66, 0x0f, 0xc7, 0x34, 0x24  # VMCLEAR [esp]   \n\t"
    4381        "jnc     1f                                              \n\t"
    4382        "movl    $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0      \n\t"
    4383        "1:                                                      \n\t"
    4384        "add     $8, %%esp                                       \n\t"
    4385        :"=rm"(rc)
    4386        :"0"(VINF_SUCCESS),
    4387         "ir"((uint32_t)HCPhysVmcs),        /* don't allow direct memory reference here, */
    4388         "ir"((uint32_t)(HCPhysVmcs >> 32)) /* this would not work with -fomit-frame-pointer */
    4389        :"memory"
    4390        );
    4391     return rc;
    4392 
    4393 # elif VMX_USE_MSC_INTRINSICS
    4394     unsigned char rcMsc = __vmx_vmclear(&HCPhysVmcs);
    4395     if (RT_LIKELY(rcMsc == 0))
    4396         return VINF_SUCCESS;
    4397     return VERR_VMX_INVALID_VMCS_PTR;
    4398 
    4399 # else
    4400     int rc = VINF_SUCCESS;
    4401     __asm
    4402     {
    4403         push    dword ptr [HCPhysVmcs + 4]
    4404         push    dword ptr [HCPhysVmcs]
    4405         _emit   0x66
    4406         _emit   0x0f
    4407         _emit   0xc7
    4408         _emit   0x34
    4409         _emit   0x24     /* VMCLEAR [esp] */
    4410         jnc     success
    4411         mov     dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
    4412 success:
    4413         add     esp, 8
    4414     }
    4415     return rc;
    4416 # endif
    4417 }
    4418 #endif
    4419 
    4420 
    4421 /**
    4422  * Executes VMPTRLD.
    4423  *
    4424  * @returns VBox status code.
    4425  * @param   HCPhysVmcs       Physical address of VMCS structure.
    4426  */
    4427 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4428 DECLASM(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs);
    4429 #else
    4430 DECLINLINE(int) VMXActivateVmcs(RTHCPHYS HCPhysVmcs)
    4431 {
    4432 # if RT_INLINE_ASM_GNU_STYLE
    4433     int rc = VINF_SUCCESS;
    4434     __asm__ __volatile__ (
    4435        "push    %3                                              \n\t"
    4436        "push    %2                                              \n\t"
    4437        ".byte   0x0f, 0xc7, 0x34, 0x24  # VMPTRLD [esp]         \n\t"
    4438        "jnc     1f                                              \n\t"
    4439        "movl    $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0      \n\t"
    4440        "1:                                                      \n\t"
    4441        "add     $8, %%esp                                       \n\t"
    4442        :"=rm"(rc)
    4443        :"0"(VINF_SUCCESS),
    4444         "ir"((uint32_t)HCPhysVmcs),        /* don't allow direct memory reference here, */
    4445         "ir"((uint32_t)(HCPhysVmcs >> 32)) /* this will not work with -fomit-frame-pointer */
    4446        );
    4447     return rc;
    4448 
    4449 # elif VMX_USE_MSC_INTRINSICS
    4450     unsigned char rcMsc = __vmx_vmptrld(&HCPhysVmcs);
    4451     if (RT_LIKELY(rcMsc == 0))
    4452         return VINF_SUCCESS;
    4453     return VERR_VMX_INVALID_VMCS_PTR;
    4454 
    4455 # else
    4456     int rc = VINF_SUCCESS;
    4457     __asm
    4458     {
    4459         push    dword ptr [HCPhysVmcs + 4]
    4460         push    dword ptr [HCPhysVmcs]
    4461         _emit   0x0f
    4462         _emit   0xc7
    4463         _emit   0x34
    4464         _emit   0x24     /* VMPTRLD [esp] */
    4465         jnc     success
    4466         mov     dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
    4467 
    4468 success:
    4469         add     esp, 8
    4470     }
    4471     return rc;
    4472 # endif
    4473 }
    4474 #endif
    4475 
    4476 
    4477 /**
    4478  * Executes VMPTRST.
    4479  *
    4480  * @returns VBox status code.
    4481  * @param   pHCPhysVmcs    Where to store the physical address of the current
    4482  *                         VMCS.
    4483  */
    4484 DECLASM(int) VMXGetActivatedVmcs(RTHCPHYS *pHCPhysVmcs);
    4485 
    4486 
    4487 /**
    4488  * Executes VMWRITE.
    4489  *
    4490  * @returns VBox status code.
    4491  * @retval  VINF_SUCCESS.
    4492  * @retval  VERR_VMX_INVALID_VMCS_PTR.
    4493  * @retval  VERR_VMX_INVALID_VMCS_FIELD.
    4494  *
    4495  * @param   uFieldEnc       VMCS field encoding.
    4496  * @param   u32Val          The 32-bit value to set.
    4497  *
    4498  * @remarks The values of the two status codes can be OR'ed together, the result
    4499  *          will be VERR_VMX_INVALID_VMCS_PTR.
    4500  */
    4501 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4502 DECLASM(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val);
    4503 #else
    4504 DECLINLINE(int) VMXWriteVmcs32(uint32_t uFieldEnc, uint32_t u32Val)
    4505 {
    4506 # if RT_INLINE_ASM_GNU_STYLE
    4507     int rc = VINF_SUCCESS;
    4508     __asm__ __volatile__ (
    4509        ".byte  0x0f, 0x79, 0xc2        # VMWRITE eax, edx       \n\t"
    4510        "ja     2f                                               \n\t"
    4511        "je     1f                                               \n\t"
    4512        "movl   $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0       \n\t"
    4513        "jmp    2f                                               \n\t"
    4514        "1:                                                      \n\t"
    4515        "movl   $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0     \n\t"
    4516        "2:                                                      \n\t"
    4517        :"=rm"(rc)
    4518        :"0"(VINF_SUCCESS),
    4519         "a"(uFieldEnc),
    4520         "d"(u32Val)
    4521        );
    4522     return rc;
    4523 
    4524 # elif VMX_USE_MSC_INTRINSICS
    4525      unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u32Val);
    4526      if (RT_LIKELY(rcMsc == 0))
    4527          return VINF_SUCCESS;
    4528      return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
    4529 
    4530 #else
    4531     int rc = VINF_SUCCESS;
    4532     __asm
    4533     {
    4534         push   dword ptr [u32Val]
    4535         mov    eax, [uFieldEnc]
    4536         _emit  0x0f
    4537         _emit  0x79
    4538         _emit  0x04
    4539         _emit  0x24     /* VMWRITE eax, [esp] */
    4540         jnc    valid_vmcs
    4541         mov    dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
    4542         jmp    the_end
    4543 
    4544 valid_vmcs:
    4545         jnz    the_end
    4546         mov    dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
    4547 the_end:
    4548         add    esp, 4
    4549     }
    4550     return rc;
    4551 # endif
    4552 }
    4553 #endif
    4554 
    4555 /**
    4556  * Executes VMWRITE.
    4557  *
    4558  * @returns VBox status code.
    4559  * @retval  VINF_SUCCESS.
    4560  * @retval  VERR_VMX_INVALID_VMCS_PTR.
    4561  * @retval  VERR_VMX_INVALID_VMCS_FIELD.
    4562  *
    4563  * @param   uFieldEnc       The VMCS field encoding.
    4564  * @param   u64Val          The 16, 32 or 64-bit value to set.
    4565  *
    4566  * @remarks The values of the two status codes can be OR'ed together, the result
    4567  *          will be VERR_VMX_INVALID_VMCS_PTR.
    4568  */
    4569 #if !defined(RT_ARCH_X86)
    4570 # if !VMX_USE_MSC_INTRINSICS || ARCH_BITS != 64
    4571 DECLASM(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val);
    4572 # else  /* VMX_USE_MSC_INTRINSICS */
    4573 DECLINLINE(int) VMXWriteVmcs64(uint32_t uFieldEnc, uint64_t u64Val)
    4574 {
    4575     unsigned char rcMsc = __vmx_vmwrite(uFieldEnc, u64Val);
    4576     if (RT_LIKELY(rcMsc == 0))
    4577         return VINF_SUCCESS;
    4578     return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
    4579 }
    4580 # endif /* VMX_USE_MSC_INTRINSICS */
    4581 #else
    4582 # define VMXWriteVmcs64(uFieldEnc, u64Val)    VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val) /** @todo dead ugly, picking up pVCpu like this */
    4583 VMMR0DECL(int) VMXWriteVmcs64Ex(PVMCPU pVCpu, uint32_t uFieldEnc, uint64_t u64Val);
    4584 #endif
    4585 
    4586 #if ARCH_BITS == 32
    4587 # define VMXWriteVmcsHstN                       VMXWriteVmcs32
    4588 # define VMXWriteVmcsGstN(uFieldEnc, u64Val)     VMXWriteVmcs64Ex(pVCpu, uFieldEnc, u64Val)
    4589 #else  /* ARCH_BITS == 64 */
    4590 # define VMXWriteVmcsHstN                       VMXWriteVmcs64
    4591 # define VMXWriteVmcsGstN                       VMXWriteVmcs64
    4592 #endif
    4593 
    4594 
    4595 /**
    4596  * Invalidate a page using INVEPT.
    4597  *
    4598  * @returns VBox status code.
    4599  * @param   enmFlush        Type of flush.
    4600  * @param   pDescriptor     Pointer to the descriptor.
    4601  */
    4602 DECLASM(int) VMXR0InvEPT(VMXTLBFLUSHEPT enmFlush, uint64_t *pDescriptor);
    4603 
    4604 
    4605 /**
    4606  * Invalidate a page using INVVPID.
    4607  *
    4608  * @returns VBox status code.
    4609  * @param   enmFlush        Type of flush.
    4610  * @param   pDescriptor     Pointer to the descriptor.
    4611  */
    4612 DECLASM(int) VMXR0InvVPID(VMXTLBFLUSHVPID enmFlush, uint64_t *pDescriptor);
    4613 
    4614 
    4615 /**
    4616  * Executes VMREAD for a 32-bit field.
    4617  *
    4618  * @returns VBox status code.
    4619  * @retval  VINF_SUCCESS.
    4620  * @retval  VERR_VMX_INVALID_VMCS_PTR.
    4621  * @retval  VERR_VMX_INVALID_VMCS_FIELD.
    4622  *
    4623  * @param   uFieldEnc       The VMCS field encoding.
    4624  * @param   pData           Where to store VMCS field value.
    4625  *
    4626  * @remarks The values of the two status codes can be OR'ed together, the result
    4627  *          will be VERR_VMX_INVALID_VMCS_PTR.
    4628  */
    4629 #if ((RT_INLINE_ASM_EXTERNAL || !defined(RT_ARCH_X86)) && !VMX_USE_MSC_INTRINSICS)
    4630 DECLASM(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData);
    4631 #else
    4632 DECLINLINE(int) VMXReadVmcs32(uint32_t uFieldEnc, uint32_t *pData)
    4633 {
    4634 # if RT_INLINE_ASM_GNU_STYLE
    4635     int rc = VINF_SUCCESS;
    4636     __asm__ __volatile__ (
    4637        "movl   $" RT_XSTR(VINF_SUCCESS)", %0                     \n\t"
    4638        ".byte  0x0f, 0x78, 0xc2        # VMREAD eax, edx         \n\t"
    4639        "ja     2f                                                \n\t"
    4640        "je     1f                                                \n\t"
    4641        "movl   $" RT_XSTR(VERR_VMX_INVALID_VMCS_PTR)", %0        \n\t"
    4642        "jmp    2f                                                \n\t"
    4643        "1:                                                       \n\t"
    4644        "movl   $" RT_XSTR(VERR_VMX_INVALID_VMCS_FIELD)", %0      \n\t"
    4645        "2:                                                       \n\t"
    4646        :"=&r"(rc),
    4647         "=d"(*pData)
    4648        :"a"(uFieldEnc),
    4649         "d"(0)
    4650        );
    4651     return rc;
    4652 
    4653 # elif VMX_USE_MSC_INTRINSICS
    4654     unsigned char rcMsc;
    4655 #  if ARCH_BITS == 32
    4656     rcMsc = __vmx_vmread(uFieldEnc, pData);
    4657 #  else
    4658     uint64_t u64Tmp;
    4659     rcMsc = __vmx_vmread(uFieldEnc, &u64Tmp);
    4660     *pData = (uint32_t)u64Tmp;
    4661 #  endif
    4662     if (RT_LIKELY(rcMsc == 0))
    4663         return VINF_SUCCESS;
    4664     return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
    4665 
    4666 #else
    4667     int rc = VINF_SUCCESS;
    4668     __asm
    4669     {
    4670         sub     esp, 4
    4671         mov     dword ptr [esp], 0
    4672         mov     eax, [uFieldEnc]
    4673         _emit   0x0f
    4674         _emit   0x78
    4675         _emit   0x04
    4676         _emit   0x24     /* VMREAD eax, [esp] */
    4677         mov     edx, pData
    4678         pop     dword ptr [edx]
    4679         jnc     valid_vmcs
    4680         mov     dword ptr [rc], VERR_VMX_INVALID_VMCS_PTR
    4681         jmp     the_end
    4682 
    4683 valid_vmcs:
    4684         jnz     the_end
    4685         mov     dword ptr [rc], VERR_VMX_INVALID_VMCS_FIELD
    4686 the_end:
    4687     }
    4688     return rc;
    4689 # endif
    4690 }
    4691 #endif
    4692 
    4693 /**
    4694  * Executes VMREAD for a 64-bit field.
    4695  *
    4696  * @returns VBox status code.
    4697  * @retval  VINF_SUCCESS.
    4698  * @retval  VERR_VMX_INVALID_VMCS_PTR.
    4699  * @retval  VERR_VMX_INVALID_VMCS_FIELD.
    4700  *
    4701  * @param   uFieldEnc       The VMCS field encoding.
    4702  * @param   pData           Where to store VMCS field value.
    4703  *
    4704  * @remarks The values of the two status codes can be OR'ed together, the result
    4705  *          will be VERR_VMX_INVALID_VMCS_PTR.
    4706  */
    4707 #if (!defined(RT_ARCH_X86) && !VMX_USE_MSC_INTRINSICS)
    4708 DECLASM(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData);
    4709 #else
    4710 DECLINLINE(int) VMXReadVmcs64(uint32_t uFieldEnc, uint64_t *pData)
    4711 {
    4712 # if VMX_USE_MSC_INTRINSICS
    4713     unsigned char rcMsc;
    4714 #  if ARCH_BITS == 32
    4715     size_t        uLow;
    4716     size_t        uHigh;
    4717     rcMsc  = __vmx_vmread(uFieldEnc, &uLow);
    4718     rcMsc |= __vmx_vmread(uFieldEnc + 1, &uHigh);
    4719     *pData = RT_MAKE_U64(uLow, uHigh);
    4720 # else
    4721     rcMsc = __vmx_vmread(uFieldEnc, pData);
    4722 # endif
    4723     if (RT_LIKELY(rcMsc == 0))
    4724         return VINF_SUCCESS;
    4725     return rcMsc == 2 ? VERR_VMX_INVALID_VMCS_PTR : VERR_VMX_INVALID_VMCS_FIELD;
    4726 
    4727 # elif ARCH_BITS == 32
    4728     int rc;
    4729     uint32_t val_hi, val;
    4730     rc  = VMXReadVmcs32(uFieldEnc, &val);
    4731     rc |= VMXReadVmcs32(uFieldEnc + 1, &val_hi);
    4732     AssertRC(rc);
    4733     *pData = RT_MAKE_U64(val, val_hi);
    4734     return rc;
    4735 
    4736 # else
    4737 #  error "Shouldn't be here..."
    4738 # endif
    4739 }
    4740 #endif
    4741 
    4742 
    4743 /**
    4744  * Gets the last instruction error value from the current VMCS.
    4745  *
    4746  * @returns VBox status code.
    4747  */
    4748 DECLINLINE(uint32_t) VMXGetLastError(void)
    4749 {
    4750 #if ARCH_BITS == 64
    4751     uint64_t uLastError = 0;
    4752     int rc = VMXReadVmcs64(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
    4753     AssertRC(rc);
    4754     return (uint32_t)uLastError;
    4755 
    4756 #else /* 32-bit host: */
    4757     uint32_t uLastError = 0;
    4758     int rc = VMXReadVmcs32(VMX_VMCS32_RO_VM_INSTR_ERROR, &uLastError);
    4759     AssertRC(rc);
    4760     return uLastError;
    4761 #endif
    4762 }
    4763 
    4764 /** @} */
    4765 
    4766 /** @} */
    4767 
    4768 #endif
    4769 

  • trunk/include/VBox/vmm/hmvmxinline.h

    r76385 r76397  
    2424 */
    2525
    26 #ifndef ___VBox_vmm_vmx_h
    27 #define ___VBox_vmm_vmx_h
    28 
    29 #include <VBox/types.h>
     26#ifndef ___VBox_vmm_hmvmxinline_h
     27#define ___VBox_vmm_hmvmxinline_h
     28
     29#include <VBox/vmm/hm_vmx.h>
    3030#include <VBox/err.h>
    31 #include <iprt/x86.h>
    32 #include <iprt/assert.h>
    3331
    3432/* In Visual C++ versions prior to 2012, the vmx intrinsics are only available
    … …  
    5351
    5452
    55 /** @defgroup grp_hm_vmx    VMX Types and Definitions
    56  * @ingroup grp_hm
    57  * @{
    58  */
    59 
    60 /** @name Host-state restoration flags.
    61  * @note If you change these values don't forget to update the assembly
    62  *       defines as well!
    63  * @{
    64  */
    65 #define VMX_RESTORE_HOST_SEL_DS                                 RT_BIT(0)
    66 #define VMX_RESTORE_HOST_SEL_ES                                 RT_BIT(1)
    67 #define VMX_RESTORE_HOST_SEL_FS                                 RT_BIT(2)
    68 #define VMX_RESTORE_HOST_SEL_GS                                 RT_BIT(3)
    69 #define VMX_RESTORE_HOST_SEL_TR                                 RT_BIT(4)
    70 #define VMX_RESTORE_HOST_GDTR                                   RT_BIT(5)
    71 #define VMX_RESTORE_HOST_IDTR                                   RT_BIT(6)
    72 #define VMX_RESTORE_HOST_GDT_READ_ONLY                          RT_BIT(7)
    73 #define VMX_RESTORE_HOST_REQUIRED                               RT_BIT(8)
    74 #define VMX_RESTORE_HOST_GDT_NEED_WRITABLE                      RT_BIT(9)
    75 /** @} */
    76 
    77 /**
    78  * Host-state restoration structure.
    79  * This holds host-state fields that require manual restoration.
    80  * Assembly version found in hm_vmx.mac (should be automatically verified).
    81  */
    82 typedef struct VMXRESTOREHOST
    83 {
    84     RTSEL       uHostSelDS;     /* 0x00 */
    85     RTSEL       uHostSelES;     /* 0x02 */
    86     RTSEL       uHostSelFS;     /* 0x04 */
    87     RTSEL       uHostSelGS;     /* 0x06 */
    88     RTSEL       uHostSelTR;     /* 0x08 */
    89     uint8_t     abPadding0[4];
    90     X86XDTR64   HostGdtr;       /**< 0x0e - should be aligned by it's 64-bit member. */
    91     uint8_t     abPadding1[6];
    92     X86XDTR64   HostGdtrRw;     /**< 0x1e - should be aligned by it's 64-bit member. */
    93     uint8_t     abPadding2[6];
    94     X86XDTR64   HostIdtr;       /**< 0x2e - should be aligned by it's 64-bit member. */
    95     uint64_t    uHostFSBase;    /* 0x38 */
    96     uint64_t    uHostGSBase;    /* 0x40 */
    97 } VMXRESTOREHOST;
    98 /** Pointer to VMXRESTOREHOST. */
    99 typedef VMXRESTOREHOST *PVMXRESTOREHOST;
    100 AssertCompileSize(X86XDTR64, 10);
    101 AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtr.uAddr,   16);
    102 AssertCompileMemberOffset(VMXRESTOREHOST, HostGdtrRw.uAddr, 32);
    103 AssertCompileMemberOffset(VMXRESTOREHOST, HostIdtr.uAddr,   48);
    104 AssertCompileMemberOffset(VMXRESTOREHOST, uHostFSBase,      56);
    105 AssertCompileSize(VMXRESTOREHOST, 72);
    106 AssertCompileSizeAlignment(VMXRESTOREHOST, 8);
    107 
    108 /** @name Host-state MSR lazy-restoration flags.
    109  * @{
    110  */
    111 /** The host MSRs have been saved. */
    112 #define VMX_LAZY_MSRS_SAVED_HOST                                RT_BIT(0)
    113 /** The guest MSRs are loaded and in effect. */
    114 #define VMX_LAZY_MSRS_LOADED_GUEST                              RT_BIT(1)
    115 /** @} */
    116 
    117 /** @name VMX HM-error codes for VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO.
    118  *  UFC = Unsupported Feature Combination.
    119  * @{
    120  */
    121 /** Unsupported pin-based VM-execution controls combo. */
    122 #define VMX_UFC_CTRL_PIN_EXEC                                   1
    123 /** Unsupported processor-based VM-execution controls combo. */
    124 #define VMX_UFC_CTRL_PROC_EXEC                                  2
    125 /** Unsupported move debug register VM-exit combo. */
    126 #define VMX_UFC_CTRL_PROC_MOV_DRX_EXIT                          3
    127 /** Unsupported VM-entry controls combo. */
    128 #define VMX_UFC_CTRL_ENTRY                                      4
    129 /** Unsupported VM-exit controls combo. */
    130 #define VMX_UFC_CTRL_EXIT                                       5
    131 /** MSR storage capacity of the VMCS autoload/store area is not sufficient
    132  *  for storing host MSRs. */
    133 #define VMX_UFC_INSUFFICIENT_HOST_MSR_STORAGE                   6
    134 /** MSR storage capacity of the VMCS autoload/store area is not sufficient
    135  *  for storing guest MSRs. */
    136 #define VMX_UFC_INSUFFICIENT_GUEST_MSR_STORAGE                  7
    137 /** Invalid VMCS size. */
    138 #define VMX_UFC_INVALID_VMCS_SIZE                               8
    139 /** Unsupported secondary processor-based VM-execution controls combo. */
    140 #define VMX_UFC_CTRL_PROC_EXEC2                                 9
    141 /** Invalid unrestricted-guest execution controls combo. */
    142 #define VMX_UFC_INVALID_UX_COMBO                                10
    143 /** EPT flush type not supported. */
    144 #define VMX_UFC_EPT_FLUSH_TYPE_UNSUPPORTED                      11
    145 /** EPT paging structure memory type is not write-back. */
    146 #define VMX_UFC_EPT_MEM_TYPE_NOT_WB                             12
    147 /** EPT requires INVEPT instr. support but it's not available. */
    148 #define VMX_UFC_EPT_INVEPT_UNAVAILABLE                          13
    149 /** EPT requires page-walk length of 4. */
    150 #define VMX_UFC_EPT_PAGE_WALK_LENGTH_UNSUPPORTED                14
    151 /** @} */
    152 
    153 /** @name VMX HM-error codes for VERR_VMX_VMCS_FIELD_CACHE_INVALID.
    154  *  VCI = VMCS-field Cache Invalid.
    155  * @{
    156  */
    157 /** Cache of VM-entry controls invalid. */
    158 #define VMX_VCI_CTRL_ENTRY                                      300
    159 /** Cache of VM-exit controls invalid. */
    160 #define VMX_VCI_CTRL_EXIT                                       301
    161 /** Cache of pin-based VM-execution controls invalid. */
    162 #define VMX_VCI_CTRL_PIN_EXEC                                   302
    163 /** Cache of processor-based VM-execution controls invalid. */
    164 #define VMX_VCI_CTRL_PROC_EXEC                                  303
    165 /** Cache of secondary processor-based VM-execution controls invalid. */
    166 #define VMX_VCI_CTRL_PROC_EXEC2                                 304
    167 /** Cache of exception bitmap invalid. */
    168 #define VMX_VCI_CTRL_XCPT_BITMAP                                305
    169 /** Cache of TSC offset invalid. */
    170 #define VMX_VCI_CTRL_TSC_OFFSET                                 306
    171 /** @} */
    172 
    173 /** @name VMX HM-error codes for VERR_VMX_INVALID_GUEST_STATE.
    174  *  IGS = Invalid Guest State.
    175  * @{
    176  */
    177 /** An error occurred while checking invalid-guest-state. */
    178 #define VMX_IGS_ERROR                                           500
    179 /** The invalid guest-state checks did not find any reason why. */
    180 #define VMX_IGS_REASON_NOT_FOUND                                501
    181 /** CR0 fixed1 bits invalid. */
    182 #define VMX_IGS_CR0_FIXED1                                      502
    183 /** CR0 fixed0 bits invalid. */
    184 #define VMX_IGS_CR0_FIXED0                                      503
    185 /** CR0.PE and CR0.PE invalid VT-x/host combination. */
    186 #define VMX_IGS_CR0_PG_PE_COMBO                                 504
    187 /** CR4 fixed1 bits invalid. */
    188 #define VMX_IGS_CR4_FIXED1                                      505
    189 /** CR4 fixed0 bits invalid. */
    190 #define VMX_IGS_CR4_FIXED0                                      506
    191 /** Reserved bits in VMCS' DEBUGCTL MSR field not set to 0 when
    192  *  VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG is used. */
    193 #define VMX_IGS_DEBUGCTL_MSR_RESERVED                           507
    194 /** CR0.PG not set for long-mode when not using unrestricted guest. */
    195 #define VMX_IGS_CR0_PG_LONGMODE                                 508
    196 /** CR4.PAE not set for long-mode guest when not using unrestricted guest. */
    197 #define VMX_IGS_CR4_PAE_LONGMODE                                509
    198 /** CR4.PCIDE set for 32-bit guest. */
    199 #define VMX_IGS_CR4_PCIDE                                       510
    200 /** VMCS' DR7 reserved bits not set to 0. */
    201 #define VMX_IGS_DR7_RESERVED                                    511
    202 /** VMCS' PERF_GLOBAL MSR reserved bits not set to 0. */
    203 #define VMX_IGS_PERF_GLOBAL_MSR_RESERVED                        512
    204 /** VMCS' EFER MSR reserved bits not set to 0. */
    205 #define VMX_IGS_EFER_MSR_RESERVED                               513
    206 /** VMCS' EFER MSR.LMA does not match the IA32e mode guest control. */
    207 #define VMX_IGS_EFER_LMA_GUEST_MODE_MISMATCH                    514
    208 /** VMCS' EFER MSR.LMA does not match EFER.LME of the guest when using paging
    209  *  without unrestricted guest. */
    210 #define VMX_IGS_EFER_LMA_LME_MISMATCH                           515
    211 /** CS.Attr.P bit invalid. */
    212 #define VMX_IGS_CS_ATTR_P_INVALID                               516
    213 /** CS.Attr reserved bits not set to 0.  */
    214 #define VMX_IGS_CS_ATTR_RESERVED                                517
    215 /** CS.Attr.G bit invalid. */
    216 #define VMX_IGS_CS_ATTR_G_INVALID                               518
    217 /** CS is unusable. */
    218 #define VMX_IGS_CS_ATTR_UNUSABLE                                519
    219 /** CS and SS DPL unequal. */
    220 #define VMX_IGS_CS_SS_ATTR_DPL_UNEQUAL                          520
    221 /** CS and SS DPL mismatch. */
    222 #define VMX_IGS_CS_SS_ATTR_DPL_MISMATCH                         521
    223 /** CS Attr.Type invalid. */
    224 #define VMX_IGS_CS_ATTR_TYPE_INVALID                            522
    225 /** CS and SS RPL unequal. */
    226 #define VMX_IGS_SS_CS_RPL_UNEQUAL                               523
    227 /** SS.Attr.DPL and SS RPL unequal. */
    228 #define VMX_IGS_SS_ATTR_DPL_RPL_UNEQUAL                         524
    229 /** SS.Attr.DPL invalid for segment type. */
    230 #define VMX_IGS_SS_ATTR_DPL_INVALID                             525
    231 /** SS.Attr.Type invalid. */
    232 #define VMX_IGS_SS_ATTR_TYPE_INVALID                            526
    233 /** SS.Attr.P bit invalid. */
    234 #define VMX_IGS_SS_ATTR_P_INVALID                               527
    235 /** SS.Attr reserved bits not set to 0. */
    236 #define VMX_IGS_SS_ATTR_RESERVED                                528
    237 /** SS.Attr.G bit invalid. */
    238 #define VMX_IGS_SS_ATTR_G_INVALID                               529
    239 /** DS.Attr.A bit invalid. */
    240 #define VMX_IGS_DS_ATTR_A_INVALID                               530
    241 /** DS.Attr.P bit invalid. */
    242 #define VMX_IGS_DS_ATTR_P_INVALID                               531
    243 /** DS.Attr.DPL and DS RPL unequal. */
    244 #define VMX_IGS_DS_ATTR_DPL_RPL_UNEQUAL                         532
    245 /** DS.Attr reserved bits not set to 0. */
    246 #define VMX_IGS_DS_ATTR_RESERVED                                533
    247 /** DS.Attr.G bit invalid. */
    248 #define VMX_IGS_DS_ATTR_G_INVALID                               534
    249 /** DS.Attr.Type invalid. */
    250 #define VMX_IGS_DS_ATTR_TYPE_INVALID                            535
    251 /** ES.Attr.A bit invalid. */
    252 #define VMX_IGS_ES_ATTR_A_INVALID                               536
    253 /** ES.Attr.P bit invalid. */
    254 #define VMX_IGS_ES_ATTR_P_INVALID                               537
    255 /** ES.Attr.DPL and DS RPL unequal. */
    256 #define VMX_IGS_ES_ATTR_DPL_RPL_UNEQUAL                         538
    257 /** ES.Attr reserved bits not set to 0. */
    258 #define VMX_IGS_ES_ATTR_RESERVED                                539
    259 /** ES.Attr.G bit invalid. */
    260 #define VMX_IGS_ES_ATTR_G_INVALID                               540
    261 /** ES.Attr.Type invalid. */
    262 #define VMX_IGS_ES_ATTR_TYPE_INVALID                            541
    263 /** FS.Attr.A bit invalid. */
    264 #define VMX_IGS_FS_ATTR_A_INVALID                               542
    265 /** FS.Attr.P bit invalid. */
    266 #define VMX_IGS_FS_ATTR_P_INVALID                               543
    267 /** FS.Attr.DPL and DS RPL unequal. */
    268 #define VMX_IGS_FS_ATTR_DPL_RPL_UNEQUAL                         544
    269 /** FS.Attr reserved bits not set to 0. */
    270 #define VMX_IGS_FS_ATTR_RESERVED                                545
    271 /** FS.Attr.G bit invalid. */
    272 #define VMX_IGS_FS_ATTR_G_INVALID                               546
    273 /** FS.Attr.Type invalid. */
    274 #define VMX_IGS_FS_ATTR_TYPE_INVALID                            547
    275 /** GS.Attr.A bit invalid. */
    276 #define VMX_IGS_GS_ATTR_A_INVALID                               548
    277 /** GS.Attr.P bit invalid. */
    278 #define VMX_IGS_GS_ATTR_P_INVALID                               549
    279 /** GS.Attr.DPL and DS RPL unequal. */
    280 #define VMX_IGS_GS_ATTR_DPL_RPL_UNEQUAL                         550
    281 /** GS.Attr reserved bits not set to 0. */
    282 #define VMX_IGS_GS_ATTR_RESERVED                                551
    283 /** GS.Attr.G bit invalid. */
    284 #define VMX_IGS_GS_ATTR_G_INVALID                               552
    285 /** GS.Attr.Type invalid. */
    286 #define VMX_IGS_GS_ATTR_TYPE_INVALID                            553
    287 /** V86 mode CS.Base invalid. */
    288 #define VMX_IGS_V86_CS_BASE_INVALID                             554
    289 /** V86 mode CS.Limit invalid. */
    290 #define VMX_IGS_V86_CS_LIMIT_INVALID                            555
    291 /** V86 mode CS.Attr invalid. */
    292 #define VMX_IGS_V86_CS_ATTR_INVALID                             556
    293 /** V86 mode SS.Base invalid. */
    294 #define VMX_IGS_V86_SS_BASE_INVALID                             557
    295 /** V86 mode SS.Limit invalid. */
    296 #define VMX_IGS_V86_SS_LIMIT_INVALID                            558
    297 /** V86 mode SS.Attr invalid. */
    298 #define VMX_IGS_V86_SS_ATTR_INVALID                             559
    299 /** V86 mode DS.Base invalid. */
    300 #define VMX_IGS_V86_DS_BASE_INVALID                             560
    301 /** V86 mode DS.Limit invalid. */
    302 #define VMX_IGS_V86_DS_LIMIT_INVALID                            561
    303 /** V86 mode DS.Attr invalid. */
    304 #define VMX_IGS_V86_DS_ATTR_INVALID                             562
    305 /** V86 mode ES.Base invalid. */
    306 #define VMX_IGS_V86_ES_BASE_INVALID                             563
    307 /** V86 mode ES.Limit invalid. */
    308 #define VMX_IGS_V86_ES_LIMIT_INVALID                            564
    309 /** V86 mode ES.Attr invalid. */
    310 #define VMX_IGS_V86_ES_ATTR_INVALID                             565
    311 /** V86 mode FS.Base invalid. */
    312 #define VMX_IGS_V86_FS_BASE_INVALID                             566
    313 /** V86 mode FS.Limit invalid. */
    314 #define VMX_IGS_V86_FS_LIMIT_INVALID                            567
    315 /** V86 mode FS.Attr invalid. */
    316 #define VMX_IGS_V86_FS_ATTR_INVALID                             568
    317 /** V86 mode GS.Base invalid. */
    318 #define VMX_IGS_V86_GS_BASE_INVALID                             569
    319 /** V86 mode GS.Limit invalid. */
    320 #define VMX_IGS_V86_GS_LIMIT_INVALID                            570
    321 /** V86 mode GS.Attr invalid. */
    322 #define VMX_IGS_V86_GS_ATTR_INVALID                             571
    323 /** Longmode CS.Base invalid. */
    324 #define VMX_IGS_LONGMODE_CS_BASE_INVALID                        572
    325 /** Longmode SS.Base invalid. */
    326 #define VMX_IGS_LONGMODE_SS_BASE_INVALID                        573
    327 /** Longmode DS.Base invalid. */
    328 #define VMX_IGS_LONGMODE_DS_BASE_INVALID                        574
    329 /** Longmode ES.Base invalid. */
    330 #define VMX_IGS_LONGMODE_ES_BASE_INVALID                        575
    331 /** SYSENTER ESP is not canonical. */
    332 #define VMX_IGS_SYSENTER_ESP_NOT_CANONICAL                      576
    333 /** SYSENTER EIP is not canonical. */
    334 #define VMX_IGS_SYSENTER_EIP_NOT_CANONICAL                      577
    335 /** PAT MSR invalid. */
    336 #define VMX_IGS_PAT_MSR_INVALID                                 578
    337 /** PAT MSR reserved bits not set to 0. */
    338 #define VMX_IGS_PAT_MSR_RESERVED                                579
    339 /** GDTR.Base is not canonical. */
    340 #define VMX_IGS_GDTR_BASE_NOT_CANONICAL                         580
    341 /** IDTR.Base is not canonical. */
    342 #define VMX_IGS_IDTR_BASE_NOT_CANONICAL                         581
    343 /** GDTR.Limit invalid. */
    344 #define VMX_IGS_GDTR_LIMIT_INVALID                              582
    345 /** IDTR.Limit invalid. */
    346 #define VMX_IGS_IDTR_LIMIT_INVALID                              583
    347 /** Longmode RIP is invalid. */
    348 #define VMX_IGS_LONGMODE_RIP_INVALID                            584
    349 /** RFLAGS reserved bits not set to 0. */
    350 #define VMX_IGS_RFLAGS_RESERVED                                 585
    351 /** RFLAGS RA1 reserved bits not set to 1. */
    352 #define VMX_IGS_RFLAGS_RESERVED1                                586
    353 /** RFLAGS.VM (V86 mode) invalid. */
    354 #define VMX_IGS_RFLAGS_VM_INVALID                               587
    355 /** RFLAGS.IF invalid. */
    356 #define VMX_IGS_RFLAGS_IF_INVALID                               588
    357 /** Activity state invalid. */
    358 #define VMX_IGS_ACTIVITY_STATE_INVALID                          589
    359 /** Activity state HLT invalid when SS.Attr.DPL is not zero. */
    360 #define VMX_IGS_ACTIVITY_STATE_HLT_INVALID                      590
    361 /** Activity state ACTIVE invalid when block-by-STI or MOV SS. */
    362 #define VMX_IGS_ACTIVITY_STATE_ACTIVE_INVALID                   591
    363 /** Activity state SIPI WAIT invalid. */
    364 #define VMX_IGS_ACTIVITY_STATE_SIPI_WAIT_INVALID                592
    365 /** Interruptibility state reserved bits not set to 0. */
    366 #define VMX_IGS_INTERRUPTIBILITY_STATE_RESERVED                 593
    367 /** Interruptibility state cannot be block-by-STI -and- MOV SS. */
    368 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_MOVSS_INVALID        594
    369 /** Interruptibility state block-by-STI invalid for EFLAGS. */
    370 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_EFL_INVALID          595
    371 /** Interruptibility state invalid while trying to deliver external
    372  *  interrupt. */
    373 #define VMX_IGS_INTERRUPTIBILITY_STATE_EXT_INT_INVALID          596
    374 /** Interruptibility state block-by-MOVSS invalid while trying to deliver an
    375  *  NMI. */
    376 #define VMX_IGS_INTERRUPTIBILITY_STATE_MOVSS_INVALID            597
    377 /** Interruptibility state block-by-SMI invalid when CPU is not in SMM. */
    378 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_INVALID              598
    379 /** Interruptibility state block-by-SMI invalid when trying to enter SMM. */
    380 #define VMX_IGS_INTERRUPTIBILITY_STATE_SMI_SMM_INVALID          599
    381 /** Interruptibility state block-by-STI (maybe) invalid when trying to
    382  *  deliver an NMI. */
    383 #define VMX_IGS_INTERRUPTIBILITY_STATE_STI_INVALID              600
    384 /** Interruptibility state block-by-NMI invalid when virtual-NMIs control is
    385  *  active. */
    386 #define VMX_IGS_INTERRUPTIBILITY_STATE_NMI_INVALID              601
    387 /** Pending debug exceptions reserved bits not set to 0. */
    388 #define VMX_IGS_PENDING_DEBUG_RESERVED                          602
    389 /** Longmode pending debug exceptions reserved bits not set to 0. */
    390 #define VMX_IGS_LONGMODE_PENDING_DEBUG_RESERVED                 603
    391 /** Pending debug exceptions.BS bit is not set when it should be. */
    392 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_SET                   604
    393 /** Pending debug exceptions.BS bit is not clear when it should be. */
    394 #define VMX_IGS_PENDING_DEBUG_XCPT_BS_NOT_CLEAR                 605
    395 /** VMCS link pointer reserved bits not set to 0. */
    396 #define VMX_IGS_VMCS_LINK_PTR_RESERVED                          606
    397 /** TR cannot index into LDT, TI bit MBZ. */
    398 #define VMX_IGS_TR_TI_INVALID                                   607
    399 /** LDTR cannot index into LDT. TI bit MBZ. */
    400 #define VMX_IGS_LDTR_TI_INVALID                                 608
    401 /** TR.Base is not canonical. */
    402 #define VMX_IGS_TR_BASE_NOT_CANONICAL                           609
    403 /** FS.Base is not canonical. */
    404 #define VMX_IGS_FS_BASE_NOT_CANONICAL                           610
    405 /** GS.Base is not canonical. */
    406 #define VMX_IGS_GS_BASE_NOT_CANONICAL                           611
    407 /** LDTR.Base is not canonical. */
    408 #define VMX_IGS_LDTR_BASE_NOT_CANONICAL                         612
    409 /** TR is unusable. */
    410 #define VMX_IGS_TR_ATTR_UNUSABLE                                613
    411 /** TR.Attr.S bit invalid. */
    412 #define VMX_IGS_TR_ATTR_S_INVALID                               614
    413 /** TR is not present. */
    414 #define VMX_IGS_TR_ATTR_P_INVALID                               615
    415 /** TR.Attr reserved bits not set to 0. */
    416 #define VMX_IGS_TR_ATTR_RESERVED                                616
    417 /** TR.Attr.G bit invalid. */
    418 #define VMX_IGS_TR_ATTR_G_INVALID                               617
    419 /** Longmode TR.Attr.Type invalid. */
    420 #define VMX_IGS_LONGMODE_TR_ATTR_TYPE_INVALID                   618
    421 /** TR.Attr.Type invalid. */
    422 #define VMX_IGS_TR_ATTR_TYPE_INVALID                            619
    423 /** CS.Attr.S invalid. */
    424 #define VMX_IGS_CS_ATTR_S_INVALID                               620
    425 /** CS.Attr.DPL invalid. */
    426 #define VMX_IGS_CS_ATTR_DPL_INVALID                             621
    427 /** PAE PDPTE reserved bits not set to 0. */
    428 #define VMX_IGS_PAE_PDPTE_RESERVED                              623
    429 /** @} */
    430 
    431 /** @name VMX VMCS-Read cache indices.
    432  * @{
    433  */
    434 #define VMX_VMCS_GUEST_ES_BASE_CACHE_IDX                        0
    435 #define VMX_VMCS_GUEST_CS_BASE_CACHE_IDX                        1
    436 #define VMX_VMCS_GUEST_SS_BASE_CACHE_IDX                        2
    437 #define VMX_VMCS_GUEST_DS_BASE_CACHE_IDX                        3
    438 #define VMX_VMCS_GUEST_FS_BASE_CACHE_IDX                        4
    439 #define VMX_VMCS_GUEST_GS_BASE_CACHE_IDX                        5
    440 #define VMX_VMCS_GUEST_LDTR_BASE_CACHE_IDX                      6
    441 #define VMX_VMCS_GUEST_TR_BASE_CACHE_IDX                        7
    442 #define VMX_VMCS_GUEST_GDTR_BASE_CACHE_IDX                      8
    443 #define VMX_VMCS_GUEST_IDTR_BASE_CACHE_IDX                      9
    444 #define VMX_VMCS_GUEST_RSP_CACHE_IDX                            10
    445 #define VMX_VMCS_GUEST_RIP_CACHE_IDX                            11
    446 #define VMX_VMCS_GUEST_SYSENTER_ESP_CACHE_IDX                   12
    447 #define VMX_VMCS_GUEST_SYSENTER_EIP_CACHE_IDX                   13
    448 #define VMX_VMCS_RO_EXIT_QUALIFICATION_CACHE_IDX                14
    449 #define VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX                 15
    450 #define VMX_VMCS_MAX_CACHE_IDX                                  (VMX_VMCS_RO_GUEST_LINEAR_ADDR_CACHE_IDX + 1)
    451 #define VMX_VMCS_GUEST_CR3_CACHE_IDX                            16
    452 #define VMX_VMCS_MAX_NESTED_PAGING_CACHE_IDX                    (VMX_VMCS_GUEST_CR3_CACHE_IDX + 1)
    453 /** @} */
    454 
    455 /** @name VMX EPT paging structures
    456  * @{
    457  */
    458 
    459 /**
    460  * Number of page table entries in the EPT. (PDPTE/PDE/PTE)
    461  */
    462 #define EPT_PG_ENTRIES          X86_PG_PAE_ENTRIES
    463 
    464 /**
    465  * EPT Page Directory Pointer Entry. Bit view.
    466  * @todo uint64_t isn't safe for bitfields (gcc pedantic warnings, and IIRC,
    467  *       this did cause trouble with one compiler/version).
    468  */
    469 typedef struct EPTPML4EBITS
    470 {
    471     /** Present bit. */
    472     uint64_t    u1Present       : 1;
    473     /** Writable bit. */
    474     uint64_t    u1Write         : 1;
    475     /** Executable bit. */
    476     uint64_t    u1Execute       : 1;
    477     /** Reserved (must be 0). */
    478     uint64_t    u5Reserved      : 5;
    479     /** Available for software. */
    480     uint64_t    u4Available     : 4;
    481     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
    482     uint64_t    u40PhysAddr     : 40;
    483     /** Available for software. */
    484     uint64_t    u12Available    : 12;
    485 } EPTPML4EBITS;
    486 AssertCompileSize(EPTPML4EBITS, 8);
    487 
    488 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
    489 #define EPT_PML4E_PG_MASK       X86_PML4E_PG_MASK
    490 /** The page shift to get the PML4 index. */
    491 #define EPT_PML4_SHIFT          X86_PML4_SHIFT
    492 /** The PML4 index mask (apply to a shifted page address). */
    493 #define EPT_PML4_MASK           X86_PML4_MASK
    494 
    495 /**
    496  * EPT PML4E.
    497  */
    498 typedef union EPTPML4E
    499 {
    500     /** Normal view. */
    501     EPTPML4EBITS    n;
    502     /** Unsigned integer view. */
    503     X86PGPAEUINT    u;
    504     /** 64 bit unsigned integer view. */
    505     uint64_t        au64[1];
    506     /** 32 bit unsigned integer view. */
    507     uint32_t        au32[2];
    508 } EPTPML4E;
    509 AssertCompileSize(EPTPML4E, 8);
    510 /** Pointer to a PML4 table entry. */
    511 typedef EPTPML4E *PEPTPML4E;
    512 /** Pointer to a const PML4 table entry. */
    513 typedef const EPTPML4E *PCEPTPML4E;
    514 
    515 /**
    516  * EPT PML4 Table.
    517  */
    518 typedef struct EPTPML4
    519 {
    520     EPTPML4E    a[EPT_PG_ENTRIES];
    521 } EPTPML4;
    522 AssertCompileSize(EPTPML4, 0x1000);
    523 /** Pointer to an EPT PML4 Table. */
    524 typedef EPTPML4 *PEPTPML4;
    525 /** Pointer to a const EPT PML4 Table. */
    526 typedef const EPTPML4 *PCEPTPML4;
    527 
    528 /**
    529  * EPT Page Directory Pointer Entry. Bit view.
    530  */
    531 typedef struct EPTPDPTEBITS
    532 {
    533     /** Present bit. */
    534     uint64_t    u1Present       : 1;
    535     /** Writable bit. */
    536     uint64_t    u1Write         : 1;
    537     /** Executable bit. */
    538     uint64_t    u1Execute       : 1;
    539     /** Reserved (must be 0). */
    540     uint64_t    u5Reserved      : 5;
    541     /** Available for software. */
    542     uint64_t    u4Available     : 4;
    543     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
    544     uint64_t    u40PhysAddr     : 40;
    545     /** Available for software. */
    546     uint64_t    u12Available    : 12;
    547 } EPTPDPTEBITS;
    548 AssertCompileSize(EPTPDPTEBITS, 8);
    549 
    550 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
    551 #define EPT_PDPTE_PG_MASK       X86_PDPE_PG_MASK
    552 /** The page shift to get the PDPT index. */
    553 #define EPT_PDPT_SHIFT          X86_PDPT_SHIFT
    554 /** The PDPT index mask (apply to a shifted page address). */
    555 #define EPT_PDPT_MASK           X86_PDPT_MASK_AMD64
    556 
    557 /**
    558  * EPT Page Directory Pointer.
    559  */
    560 typedef union EPTPDPTE
    561 {
    562     /** Normal view. */
    563     EPTPDPTEBITS    n;
    564     /** Unsigned integer view. */
    565     X86PGPAEUINT    u;
    566     /** 64 bit unsigned integer view. */
    567     uint64_t        au64[1];
    568     /** 32 bit unsigned integer view. */
    569     uint32_t        au32[2];
    570 } EPTPDPTE;
    571 AssertCompileSize(EPTPDPTE, 8);
    572 /** Pointer to an EPT Page Directory Pointer Entry. */
    573 typedef EPTPDPTE *PEPTPDPTE;
    574 /** Pointer to a const EPT Page Directory Pointer Entry. */
    575 typedef const EPTPDPTE *PCEPTPDPTE;
    576 
    577 /**
    578  * EPT Page Directory Pointer Table.
    579  */
    580 typedef struct EPTPDPT
    581 {
    582     EPTPDPTE    a[EPT_PG_ENTRIES];
    583 } EPTPDPT;
    584 AssertCompileSize(EPTPDPT, 0x1000);
    585 /** Pointer to an EPT Page Directory Pointer Table. */
    586 typedef EPTPDPT *PEPTPDPT;
    587 /** Pointer to a const EPT Page Directory Pointer Table. */
    588 typedef const EPTPDPT *PCEPTPDPT;
    589 
    590 /**
    591  * EPT Page Directory Table Entry. Bit view.
    592  */
    593 typedef struct EPTPDEBITS
    594 {
    595     /** Present bit. */
    596     uint64_t    u1Present       : 1;
    597     /** Writable bit. */
    598     uint64_t    u1Write         : 1;
    599     /** Executable bit. */
    600     uint64_t    u1Execute       : 1;
    601     /** Reserved (must be 0). */
    602     uint64_t    u4Reserved      : 4;
    603     /** Big page (must be 0 here). */
    604     uint64_t    u1Size          : 1;
    605     /** Available for software. */
    606     uint64_t    u4Available     : 4;
    607     /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
    608     uint64_t    u40PhysAddr     : 40;
    609     /** Available for software. */
    610     uint64_t    u12Available    : 12;
    611 } EPTPDEBITS;
    612 AssertCompileSize(EPTPDEBITS, 8);
    613 
    614 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
    615 #define EPT_PDE_PG_MASK         X86_PDE_PAE_PG_MASK
    616 /** The page shift to get the PD index. */
    617 #define EPT_PD_SHIFT            X86_PD_PAE_SHIFT
    618 /** The PD index mask (apply to a shifted page address). */
    619 #define EPT_PD_MASK             X86_PD_PAE_MASK
    620 
    621 /**
    622  * EPT 2MB Page Directory Table Entry. Bit view.
    623  */
    624 typedef struct EPTPDE2MBITS
    625 {
    626     /** Present bit. */
    627     uint64_t    u1Present       : 1;
    628     /** Writable bit. */
    629     uint64_t    u1Write         : 1;
    630     /** Executable bit. */
    631     uint64_t    u1Execute       : 1;
    632     /** EPT Table Memory Type. MBZ for non-leaf nodes. */
    633     uint64_t    u3EMT           : 3;
    634     /** Ignore PAT memory type */
    635     uint64_t    u1IgnorePAT     : 1;
    636     /** Big page (must be 1 here). */
    637     uint64_t    u1Size          : 1;
    638     /** Available for software. */
    639     uint64_t    u4Available     : 4;
    640     /** Reserved (must be 0). */
    641     uint64_t    u9Reserved      : 9;
    642     /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
    643     uint64_t    u31PhysAddr     : 31;
    644     /** Available for software. */
    645     uint64_t    u12Available    : 12;
    646 } EPTPDE2MBITS;
    647 AssertCompileSize(EPTPDE2MBITS, 8);
    648 
    649 /** Bits 21-51 - - EPT - Physical Page number of the next level. */
    650 #define EPT_PDE2M_PG_MASK       X86_PDE2M_PAE_PG_MASK
    651 
    652 /**
    653  * EPT Page Directory Table Entry.
    654  */
    655 typedef union EPTPDE
    656 {
    657     /** Normal view. */
    658     EPTPDEBITS      n;
    659     /** 2MB view (big). */
    660     EPTPDE2MBITS    b;
    661     /** Unsigned integer view. */
    662     X86PGPAEUINT    u;
    663     /** 64 bit unsigned integer view. */
    664     uint64_t        au64[1];
    665     /** 32 bit unsigned integer view. */
    666     uint32_t        au32[2];
    667 } EPTPDE;
    668 AssertCompileSize(EPTPDE, 8);
    669 /** Pointer to an EPT Page Directory Table Entry. */
    670 typedef EPTPDE *PEPTPDE;
    671 /** Pointer to a const EPT Page Directory Table Entry. */
    672 typedef const EPTPDE *PCEPTPDE;
    673 
    674 /**
    675  * EPT Page Directory Table.
    676  */
    677 typedef struct EPTPD
    678 {
    679     EPTPDE      a[EPT_PG_ENTRIES];
    680 } EPTPD;
    681 AssertCompileSize(EPTPD, 0x1000);
    682 /** Pointer to an EPT Page Directory Table. */
    683 typedef EPTPD *PEPTPD;
    684 /** Pointer to a const EPT Page Directory Table. */
    685 typedef const EPTPD *PCEPTPD;
    686 
    687 /**
    688  * EPT Page Table Entry. Bit view.
    689  */
    690 typedef struct EPTPTEBITS
    691 {
    692     /** 0 - Present bit.
    693      * @remarks This is a convenience "misnomer". The bit actually indicates read access
    694      *          and the CPU will consider an entry with any of the first three bits set
    695      *          as present.  Since all our valid entries will have this bit set, it can
    696      *          be used as a present indicator and allow some code sharing. */
    697     uint64_t    u1Present       : 1;
    698     /** 1 - Writable bit. */
    699     uint64_t    u1Write         : 1;
    700     /** 2 - Executable bit. */
    701     uint64_t    u1Execute       : 1;
    702     /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
    703     uint64_t    u3EMT           : 3;
    704     /** 6 - Ignore PAT memory type */
    705     uint64_t    u1IgnorePAT     : 1;
    706     /** 11:7 - Available for software. */
    707     uint64_t    u5Available     : 5;
    708     /** 51:12 - Physical address of page. Restricted by maximum physical
    709      *  address width of the cpu. */
    710     uint64_t    u40PhysAddr     : 40;
    711     /** 63:52 - Available for software. */
    712     uint64_t    u12Available    : 12;
    713 } EPTPTEBITS;
    714 AssertCompileSize(EPTPTEBITS, 8);
    715 
    716 /** Bits 12-51 - - EPT - Physical Page number of the next level. */
    717 #define EPT_PTE_PG_MASK         X86_PTE_PAE_PG_MASK
    718 /** The page shift to get the EPT PTE index. */
    719 #define EPT_PT_SHIFT            X86_PT_PAE_SHIFT
    720 /** The EPT PT index mask (apply to a shifted page address). */
    721 #define EPT_PT_MASK             X86_PT_PAE_MASK
    722 
    723 /**
    724  * EPT Page Table Entry.
    725  */
    726 typedef union EPTPTE
    727 {
    728     /** Normal view. */
    729     EPTPTEBITS      n;
    730     /** Unsigned integer view. */
    731     X86PGPAEUINT    u;
    732     /** 64 bit unsigned integer view. */
    733     uint64_t        au64[1];
    734     /** 32 bit unsigned integer view. */
    735     uint32_t        au32[2];
    736 } EPTPTE;
    737 AssertCompileSize(EPTPTE, 8);
    738 /** Pointer to an EPT Page Directory Table Entry. */
    739 typedef EPTPTE *PEPTPTE;
    740 /** Pointer to a const EPT Page Directory Table Entry. */
    741 typedef const EPTPTE *PCEPTPTE;
    742 
    743 /**
    744  * EPT Page Table.
    745  */
    746 typedef struct EPTPT
    747 {
    748     EPTPTE      a[EPT_PG_ENTRIES];
    749 } EPTPT;
    750 AssertCompileSize(EPTPT, 0x1000);
    751 /** Pointer to an extended page table. */
    752 typedef EPTPT *PEPTPT;
    753 /** Pointer to a const extended table. */
    754 typedef const EPTPT *PCEPTPT;
    755 
    756 /** @} */
    757 
    758 /**
    759  * VMX VPID flush types.
    760  * @note Valid enum members are in accordance to the VT-x spec.
    761  */
    762 typedef enum
    763 {
    764     /** Invalidate a specific page. */
    765     VMXTLBFLUSHVPID_INDIV_ADDR                 = 0,
    766     /** Invalidate one context (specific VPID). */
    767     VMXTLBFLUSHVPID_SINGLE_CONTEXT             = 1,
    768     /** Invalidate all contexts (all VPIDs). */
    769     VMXTLBFLUSHVPID_ALL_CONTEXTS               = 2,
    770     /** Invalidate a single VPID context retaining global mappings. */
    771     VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS = 3,
    772     /** Unsupported by VirtualBox. */
    773     VMXTLBFLUSHVPID_NOT_SUPPORTED              = 0xbad0,
    774     /** Unsupported by CPU. */
    775     VMXTLBFLUSHVPID_NONE                       = 0xbad1
    776 } VMXTLBFLUSHVPID;
    777 AssertCompileSize(VMXTLBFLUSHVPID, 4);
    778 
    779 /**
    780  * VMX EPT flush types.
    781  * @note Valid enums values are in accordance to the VT-x spec.
    782  */
    783 typedef enum
    784 {
    785     /** Invalidate one context (specific EPT). */
    786     VMXTLBFLUSHEPT_SINGLE_CONTEXT              = 1,
    787     /* Invalidate all contexts (all EPTs) */
    788     VMXTLBFLUSHEPT_ALL_CONTEXTS                = 2,
    789     /** Unsupported by VirtualBox.   */
    790     VMXTLBFLUSHEPT_NOT_SUPPORTED               = 0xbad0,
    791     /** Unsupported by CPU. */
    792     VMXTLBFLUSHEPT_NONE                        = 0xbad1
    793 } VMXTLBFLUSHEPT;
    794 AssertCompileSize(VMXTLBFLUSHEPT, 4);
    795 
    796 /**
    797  * VMX Posted Interrupt Descriptor.
    798  * In accordance to the VT-x spec.
    799  */
    800 typedef struct VMXPOSTEDINTRDESC
    801 {
    802     uint32_t    aVectorBitmap[8];
    803     uint32_t    fOutstandingNotification : 1;
    804     uint32_t    uReserved0               : 31;
    805     uint8_t     au8Reserved0[28];
    806 } VMXPOSTEDINTRDESC;
    807 AssertCompileMemberSize(VMXPOSTEDINTRDESC, aVectorBitmap, 32);
    808 AssertCompileSize(VMXPOSTEDINTRDESC, 64);
    809 /** Pointer to a posted interrupt descriptor. */
    810 typedef VMXPOSTEDINTRDESC *PVMXPOSTEDINTRDESC;
    811 /** Pointer to a const posted interrupt descriptor. */
    812 typedef const VMXPOSTEDINTRDESC *PCVMXPOSTEDINTRDESC;
    813 
    814 /**
    815  * VMX VMCS revision identifier.
    816  */
    817 typedef union
    818 {
    819     struct
    820     {
    821         /** Revision identifier. */
    822         uint32_t    u31RevisionId : 31;
    823         /** Whether this is a shadow VMCS. */
    824         uint32_t    fIsShadowVmcs : 1;
    825     } n;
    826     /* The unsigned integer view. */
    827     uint32_t        u;
    828 } VMXVMCSREVID;
    829 AssertCompileSize(VMXVMCSREVID, 4);
    830 /** Pointer to the VMXVMCSREVID union. */
    831 typedef VMXVMCSREVID *PVMXVMCSREVID;
    832 /** Pointer to a const VMXVVMCSREVID union. */
    833 typedef const VMXVMCSREVID *PCVMXVMCSREVID;
    834 
    835 /**
    836  * VMX VM-exit instruction information.
    837  */
    838 typedef union
    839 {
    840     /** Plain unsigned int representation. */
    841     uint32_t    u;
    842 
    843     /** INS and OUTS information. */
    844     struct
    845     {
    846         uint32_t    u7Reserved0 : 7;
    847         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    848         uint32_t    u3AddrSize  : 3;
    849         uint32_t    u5Reserved1 : 5;
    850         /** The segment register (X86_SREG_XXX). */
    851         uint32_t    iSegReg     : 3;
    852         uint32_t    uReserved2  : 14;
    853     } StrIo;
    854 
    855     struct
    856     {
    857         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    858         uint32_t    u2Scaling       : 2;
    859         uint32_t    u5Undef0        : 5;
    860         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    861         uint32_t    u3AddrSize      : 3;
    862         /** Cleared to 0. */
    863         uint32_t    u1Cleared0      : 1;
    864         uint32_t    u4Undef0        : 4;
    865         /** The segment register (X86_SREG_XXX). */
    866         uint32_t    iSegReg         : 3;
    867         /** The index register (X86_GREG_XXX). */
    868         uint32_t    iIdxReg         : 4;
    869         /** Set if index register is invalid. */
    870         uint32_t    fIdxRegInvalid  : 1;
    871         /** The base register (X86_GREG_XXX). */
    872         uint32_t    iBaseReg        : 4;
    873         /** Set if base register is invalid. */
    874         uint32_t    fBaseRegInvalid : 1;
    875         /** Register 2 (X86_GREG_XXX). */
    876         uint32_t    iReg2           : 4;
    877     } Inv;
    878 
    879     /** VMCLEAR, VMPTRLD, VMPTRST, VMXON, XRSTORS, XSAVES information. */
    880     struct
    881     {
    882         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    883         uint32_t    u2Scaling       : 2;
    884         uint32_t    u5Reserved0     : 5;
    885         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    886         uint32_t    u3AddrSize      : 3;
    887         /** Cleared to 0. */
    888         uint32_t    u1Cleared0      : 1;
    889         uint32_t    u4Reserved0     : 4;
    890         /** The segment register (X86_SREG_XXX). */
    891         uint32_t    iSegReg         : 3;
    892         /** The index register (X86_GREG_XXX). */
    893         uint32_t    iIdxReg         : 4;
    894         /** Set if index register is invalid. */
    895         uint32_t    fIdxRegInvalid  : 1;
    896         /** The base register (X86_GREG_XXX). */
    897         uint32_t    iBaseReg        : 4;
    898         /** Set if base register is invalid. */
    899         uint32_t    fBaseRegInvalid : 1;
    900         /** Register 2 (X86_GREG_XXX). */
    901         uint32_t    iReg2           : 4;
    902     } VmxXsave;
    903 
    904     /** LIDT, LGDT, SIDT, SGDT information. */
    905     struct
    906     {
    907         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    908         uint32_t    u2Scaling       : 2;
    909         uint32_t    u5Undef0        : 5;
    910         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    911         uint32_t    u3AddrSize      : 3;
    912         /** Always cleared to 0. */
    913         uint32_t    u1Cleared0      : 1;
    914         /** Operand size; 0=16-bit, 1=32-bit, undefined for 64-bit.  */
    915         uint32_t    uOperandSize    : 1;
    916         uint32_t    u3Undef0        : 3;
    917         /** The segment register (X86_SREG_XXX). */
    918         uint32_t    iSegReg         : 3;
    919         /** The index register (X86_GREG_XXX). */
    920         uint32_t    iIdxReg         : 4;
    921         /** Set if index register is invalid. */
    922         uint32_t    fIdxRegInvalid  : 1;
    923         /** The base register (X86_GREG_XXX). */
    924         uint32_t    iBaseReg        : 4;
    925         /** Set if base register is invalid. */
    926         uint32_t    fBaseRegInvalid : 1;
    927         /** Instruction identity (VMX_INSTR_ID_XXX). */
    928         uint32_t    u2InstrId       : 2;
    929         uint32_t    u2Undef0        : 2;
    930     } GdtIdt;
    931 
    932     /** LLDT, LTR, SLDT, STR information. */
    933     struct
    934     {
    935         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    936         uint32_t    u2Scaling       : 2;
    937         uint32_t    u1Undef0        : 1;
    938         /** Register 1 (X86_GREG_XXX). */
    939         uint32_t    iReg1           : 4;
    940         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    941         uint32_t    u3AddrSize      : 3;
    942         /** Memory/Register - Always cleared to 0 to indicate memory operand. */
    943         uint32_t    fIsRegOperand   : 1;
    944         uint32_t    u4Undef0        : 4;
    945         /** The segment register (X86_SREG_XXX). */
    946         uint32_t    iSegReg         : 3;
    947         /** The index register (X86_GREG_XXX). */
    948         uint32_t    iIdxReg         : 4;
    949         /** Set if index register is invalid. */
    950         uint32_t    fIdxRegInvalid  : 1;
    951         /** The base register (X86_GREG_XXX). */
    952         uint32_t    iBaseReg        : 4;
    953         /** Set if base register is invalid. */
    954         uint32_t    fBaseRegInvalid : 1;
    955         /** Instruction identity (VMX_INSTR_ID_XXX). */
    956         uint32_t    u2InstrId       : 2;
    957         uint32_t    u2Undef0        : 2;
    958     } LdtTr;
    959 
    960     /** RDRAND, RDSEED information. */
    961     struct
    962     {
    963         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    964         uint32_t    u2Undef0        : 2;
    965         /** Destination register (X86_GREG_XXX). */
    966         uint32_t    iReg1           : 4;
    967         uint32_t    u4Undef0        : 4;
    968         /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused.  */
    969         uint32_t    u2OperandSize   : 2;
    970         uint32_t    u19Def0         : 20;
    971     } RdrandRdseed;
    972 
    973     struct
    974     {
    975         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    976         uint32_t    u2Scaling       : 2;
    977         uint32_t    u1Undef0        : 1;
    978         /** Register 1 (X86_GREG_XXX). */
    979         uint32_t    iReg1           : 4;
    980         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    981         uint32_t    u3AddrSize      : 3;
    982         /** Memory or register operand. */
    983         uint32_t    fIsRegOperand   : 1;
    984         /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused.  */
    985         uint32_t    u4Undef0        : 4;
    986         /** The segment register (X86_SREG_XXX). */
    987         uint32_t    iSegReg         : 3;
    988         /** The index register (X86_GREG_XXX). */
    989         uint32_t    iIdxReg         : 4;
    990         /** Set if index register is invalid. */
    991         uint32_t    fIdxRegInvalid  : 1;
    992         /** The base register (X86_GREG_XXX). */
    993         uint32_t    iBaseReg        : 4;
    994         /** Set if base register is invalid. */
    995         uint32_t    fBaseRegInvalid : 1;
    996         /** Register 2 (X86_GREG_XXX). */
    997         uint32_t    iReg2           : 4;
    998     } VmreadVmwrite;
    999 
    1000     /** This is a combination field of all instruction information. Note! Not all field
    1001      *  combinations are valid (e.g., iReg1 is undefined for memory operands) and
    1002      *  specialized fields are overwritten by their generic counterparts (e.g. no
    1003      *  instruction identity field). */
    1004     struct
    1005     {
    1006         /** Scaling; 0=no scaling, 1=scale-by-2, 2=scale-by-4, 3=scale-by-8. */
    1007         uint32_t    u2Scaling       : 2;
    1008         uint32_t    u1Undef0        : 1;
    1009         /** Register 1 (X86_GREG_XXX). */
    1010         uint32_t    iReg1           : 4;
    1011         /** The address size; 0=16-bit, 1=32-bit, 2=64-bit, rest undefined. */
    1012         uint32_t    u3AddrSize      : 3;
    1013         /** Memory/Register - Always cleared to 0 to indicate memory operand. */
    1014         uint32_t    fIsRegOperand   : 1;
    1015         /** Operand size; 0=16-bit, 1=32-bit, 2=64-bit, 3=unused.  */
    1016         uint32_t    uOperandSize    : 2;
    1017         uint32_t    u2Undef0        : 2;
    1018         /** The segment register (X86_SREG_XXX). */
    1019         uint32_t    iSegReg         : 3;
    1020         /** The index register (X86_GREG_XXX). */
    1021         uint32_t    iIdxReg         : 4;
    1022         /** Set if index register is invalid. */
    1023         uint32_t    fIdxRegInvalid  : 1;
    1024         /** The base register (X86_GREG_XXX). */
    1025         uint32_t    iBaseReg        : 4;
    1026         /** Set if base register is invalid. */
    1027         uint32_t    fBaseRegInvalid : 1;
    1028         /** Register 2 (X86_GREG_XXX) or instruction identity. */
    1029         uint32_t    iReg2           : 4;
    1030     } All;
    1031 } VMXEXITINSTRINFO;
    1032 AssertCompileSize(VMXEXITINSTRINFO, 4);
    1033 /** Pointer to a VMX VM-exit instruction info. struct. */
    1034 typedef VMXEXITINSTRINFO *PVMXEXITINSTRINFO;
    1035 /** Pointer to a const VMX VM-exit instruction info. struct. */
    1036 typedef const VMXEXITINSTRINFO *PCVMXEXITINSTRINFO;
    1037 
    1038 
    1039 /** @name VM-entry failure reported in VM-exit qualification.
    1040  * See Intel spec. 26.7 "VM-entry failures during or after loading guest-state".
    1041  */
    1042 /** No errors during VM-entry. */
    1043 #define VMX_ENTRY_FAIL_QUAL_NO_ERROR                            (0)
    1044 /** Not used. */
    1045 #define VMX_ENTRY_FAIL_QUAL_NOT_USED                            (1)
    1046 /** Error while loading PDPTEs. */
    1047 #define VMX_ENTRY_FAIL_QUAL_PDPTE                               (2)
    1048 /** NMI injection when blocking-by-STI is set. */
    1049 #define VMX_ENTRY_FAIL_QUAL_NMI_INJECT                          (3)
    1050 /** Invalid VMCS link pointer. */
    1051 #define VMX_ENTRY_FAIL_QUAL_VMCS_LINK_PTR                       (4)
    1052 /** @} */
    1053 
    1054 /**
    1055  * VMX MSR-bitmap read permissions.
    1056  */
    1057 typedef enum VMXMSREXITREAD
    1058 {
    1059     /** Reading this MSR causes a VM-exit. */
    1060     VMXMSREXIT_INTERCEPT_READ = 1,
    1061     /** Reading this MSR doesn't cause a VM-exit. */
    1062     VMXMSREXIT_PASSTHRU_READ
    1063 } VMXMSREXITREAD;
    1064 /** Pointer to MSR-bitmap read permissions. */
    1065 typedef VMXMSREXITREAD* PVMXMSREXITREAD;
    1066 
    1067 /**
    1068  * VMX MSR-bitmap write permissions.
    1069  */
    1070 typedef enum VMXMSREXITWRITE
    1071 {
    1072     /** Writing to this MSR causes a VM-exit. */
    1073     VMXMSREXIT_INTERCEPT_WRITE = 3,
    1074     /** Writing to this MSR does not cause a VM-exit. */
    1075     VMXMSREXIT_PASSTHRU_WRITE
    1076 } VMXMSREXITWRITE;
    1077 /** Pointer to MSR-bitmap write permissions. */
    1078 typedef VMXMSREXITWRITE* PVMXMSREXITWRITE;
    1079 
    1080 /**
    1081  * VMX MSR autoload/store element.
    1082  * In accordance to the VT-x spec.
    1083  */
    1084 typedef struct VMXAUTOMSR
    1085 {
    1086     /** The MSR Id. */
    1087     uint32_t    u32Msr;
    1088     /** Reserved (MBZ). */
    1089     uint32_t    u32Reserved;
    1090     /** The MSR value. */
    1091     uint64_t    u64Value;
    1092 } VMXAUTOMSR;
    1093 AssertCompileSize(VMXAUTOMSR, 16);
    1094 /** Pointer to an MSR load/store element. */
    1095 typedef VMXAUTOMSR *PVMXAUTOMSR;
    1096 /** Pointer to a const MSR load/store element. */
    1097 typedef const VMXAUTOMSR *PCVMXAUTOMSR;
    1098 
    1099 /** VMX auto load-store MSR (VMXAUTOMSR) offset mask. */
    1100 #define VMX_AUTOMSR_OFFSET_MASK         0xf
    1101 
    1102 /**
    1103  * VMX tagged-TLB flush types.
    1104  */
    1105 typedef enum
    1106 {
    1107     VMXTLBFLUSHTYPE_EPT,
    1108     VMXTLBFLUSHTYPE_VPID,
    1109     VMXTLBFLUSHTYPE_EPT_VPID,
    1110     VMXTLBFLUSHTYPE_NONE
    1111 } VMXTLBFLUSHTYPE;
    1112 /** Pointer to a VMXTLBFLUSHTYPE enum. */
    1113 typedef VMXTLBFLUSHTYPE *PVMXTLBFLUSHTYPE;
    1114 /** Pointer to a const VMXTLBFLUSHTYPE enum. */
    1115 typedef const VMXTLBFLUSHTYPE *PCVMXTLBFLUSHTYPE;
    1116 
    1117 /**
    1118  * VMX controls MSR.
    1119  */
    1120 typedef union
    1121 {
    1122     struct
    1123     {
    1124         /** Bits set here -must- be set in the corresponding VM-execution controls. */
    1125         uint32_t        allowed0;
    1126         /** Bits cleared here -must- be cleared in the corresponding VM-execution
    1127          *  controls. */
    1128         uint32_t        allowed1;
    1129     } n;
    1130     uint64_t            u;
    1131 } VMXCTLSMSR;
    1132 AssertCompileSize(VMXCTLSMSR, 8);
    1133 /** Pointer to a VMXCTLSMSR union. */
    1134 typedef VMXCTLSMSR *PVMXCTLSMSR;
    1135 /** Pointer to a const VMXCTLSMSR union. */
    1136 typedef const VMXCTLSMSR *PCVMXCTLSMSR;
    1137 
    1138 /**
    1139  * VMX MSRs.
    1140  * @remarks Although treated as a plain-old data (POD) in several places, please
    1141  *          update HMVmxGetHostMsr() if new MSRs are added here.
    1142  */
    1143 typedef struct VMXMSRS
    1144 {
    1145     uint64_t        u64FeatCtrl;
    1146     uint64_t        u64Basic;
    1147     VMXCTLSMSR      PinCtls;
    1148     VMXCTLSMSR      ProcCtls;
    1149     VMXCTLSMSR      ProcCtls2;
    1150     VMXCTLSMSR      ExitCtls;
    1151     VMXCTLSMSR      EntryCtls;
    1152     VMXCTLSMSR      TruePinCtls;
    1153     VMXCTLSMSR      TrueProcCtls;
    1154     VMXCTLSMSR      TrueEntryCtls;
    1155     VMXCTLSMSR      TrueExitCtls;
    1156     uint64_t        u64Misc;
    1157     uint64_t        u64Cr0Fixed0;
    1158     uint64_t        u64Cr0Fixed1;
    1159     uint64_t        u64Cr4Fixed0;
    1160     uint64_t        u64Cr4Fixed1;
    1161     uint64_t        u64VmcsEnum;
    1162     uint64_t        u64VmFunc;
    1163     uint64_t        u64EptVpidCaps;
    1164     uint64_t        a_u64Reserved[5];
    1165 } VMXMSRS;
    1166 AssertCompileSizeAlignment(VMXMSRS, 8);
    1167 AssertCompileSize(VMXMSRS, 192);
    1168 /** Pointer to a VMXMSRS struct. */
    1169 typedef VMXMSRS *PVMXMSRS;
    1170 /** Pointer to a const VMXMSRS struct. */
    1171 typedef const VMXMSRS *PCVMXMSRS;
    1172 
    1173 
    1174 /** @name VMX Basic Exit Reasons.
    1175  * @{
    1176  */
    1177 /** -1 Invalid exit code */
    1178 #define VMX_EXIT_INVALID                                      (-1)
    1179 /** 0 Exception or non-maskable interrupt (NMI). */
    1180 #define VMX_EXIT_XCPT_OR_NMI                                    0
    1181 /** 1 External interrupt. */
    1182 #define VMX_EXIT_EXT_INT                                        1
    1183 /** 2 Triple fault. */
    1184 #define VMX_EXIT_TRIPLE_FAULT                                   2
    1185 /** 3 INIT signal. */
    1186 #define VMX_EXIT_INIT_SIGNAL                                    3
    1187 /** 4 Start-up IPI (SIPI). */
    1188 #define VMX_EXIT_SIPI                                           4
    1189 /** 5 I/O system-management interrupt (SMI). */
    1190 #define VMX_EXIT_IO_SMI                                         5
    1191 /** 6 Other SMI. */
    1192 #define VMX_EXIT_SMI                                            6
    1193 /** 7 Interrupt window exiting. */
    1194 #define VMX_EXIT_INT_WINDOW                                     7
    1195 /** 8 NMI window exiting. */
    1196 #define VMX_EXIT_NMI_WINDOW                                     8
    1197 /** 9 Task switch. */
    1198 #define VMX_EXIT_TASK_SWITCH                                    9
    1199 /** 10 Guest software attempted to execute CPUID. */
    1200 #define VMX_EXIT_CPUID                                          10
    1201 /** 11 Guest software attempted to execute GETSEC. */
    1202 #define VMX_EXIT_GETSEC                                         11
    1203 /** 12 Guest software attempted to execute HLT. */
    1204 #define VMX_EXIT_HLT                                            12
    1205 /** 13 Guest software attempted to execute INVD. */
    1206 #define VMX_EXIT_INVD                                           13
    1207 /** 14 Guest software attempted to execute INVLPG. */
    1208 #define VMX_EXIT_INVLPG                                         14
    1209 /** 15 Guest software attempted to execute RDPMC. */
    1210 #define VMX_EXIT_RDPMC                                          15
    1211 /** 16 Guest software attempted to execute RDTSC. */
    1212 #define VMX_EXIT_RDTSC                                          16
    1213 /** 17 Guest software attempted to execute RSM in SMM. */
    1214 #define VMX_EXIT_RSM                                            17
    1215 /** 18 Guest software executed VMCALL. */
    1216 #define VMX_EXIT_VMCALL                                         18
    1217 /** 19 Guest software executed VMCLEAR. */
    1218 #define VMX_EXIT_VMCLEAR                                        19
    1219 /** 20 Guest software executed VMLAUNCH. */
    1220 #define VMX_EXIT_VMLAUNCH                                       20
    1221 /** 21 Guest software executed VMPTRLD. */
    1222 #define VMX_EXIT_VMPTRLD                                        21
    1223 /** 22 Guest software executed VMPTRST. */
    1224 #define VMX_EXIT_VMPTRST                                        22
    1225 /** 23 Guest software executed VMREAD. */
    1226 #define VMX_EXIT_VMREAD                                         23
    1227 /** 24 Guest software executed VMRESUME. */
    1228 #define VMX_EXIT_VMRESUME                                       24
    1229 /** 25 Guest software executed VMWRITE. */
    1230 #define VMX_EXIT_VMWRITE                                        25
    1231 /** 26 Guest software executed VMXOFF. */
    1232 #define VMX_EXIT_VMXOFF                                         26
    1233 /** 27 Guest software executed VMXON. */
    1234 #define VMX_EXIT_VMXON                                          27
    1235 /** 28 Control-register accesses. */
    1236 #define VMX_EXIT_MOV_CRX                                        28
    1237 /** 29 Debug-register accesses. */
    1238 #define VMX_EXIT_MOV_DRX                                        29
    1239 /** 30 I/O instruction. */
    1240 #define VMX_EXIT_IO_INSTR                                       30
    1241 /** 31 RDMSR. Guest software attempted to execute RDMSR. */
    1242 #define VMX_EXIT_RDMSR                                          31
    1243 /** 32 WRMSR. Guest software attempted to execute WRMSR. */
    1244 #define VMX_EXIT_WRMSR                                          32
    1245 /** 33 VM-entry failure due to invalid guest state. */
    1246 #define VMX_EXIT_ERR_INVALID_GUEST_STATE                        33
    1247 /** 34 VM-entry failure due to MSR loading. */
    1248 #define VMX_EXIT_ERR_MSR_LOAD                                   34
    1249 /** 36 Guest software executed MWAIT. */
    1250 #define VMX_EXIT_MWAIT                                          36
    1251 /** 37 VM-exit due to monitor trap flag. */
    1252 #define VMX_EXIT_MTF                                            37
    1253 /** 39 Guest software attempted to execute MONITOR. */
    1254 #define VMX_EXIT_MONITOR                                        39
    1255 /** 40 Guest software attempted to execute PAUSE. */
    1256 #define VMX_EXIT_PAUSE                                          40
    1257 /** 41 VM-entry failure due to machine-check. */
    1258 #define VMX_EXIT_ERR_MACHINE_CHECK                              41
    1259 /** 43 TPR below threshold. Guest software executed MOV to CR8. */
    1260 #define VMX_EXIT_TPR_BELOW_THRESHOLD                            43
    1261 /** 44 APIC access. Guest software attempted to access memory at a physical
    1262  *  address on the APIC-access page. */
    1263 #define VMX_EXIT_APIC_ACCESS                                    44
    1264 /** 45 Virtualized EOI. EOI virtualization was performed for a virtual
    1265  *  interrupt whose vector indexed a bit set in the EOI-exit bitmap. */
    1266 #define VMX_EXIT_VIRTUALIZED_EOI                                45
    1267 /** 46 Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT,
    1268  *  SGDT, or SIDT. */
    1269 #define VMX_EXIT_GDTR_IDTR_ACCESS                               46
    1270 /** 47 Access to LDTR or TR. Guest software attempted to execute LLDT, LTR,
    1271  *  SLDT, or STR. */
    1272 #define VMX_EXIT_LDTR_TR_ACCESS                                 47
    1273 /** 48 EPT violation. An attempt to access memory with a guest-physical address
    1274  *  was disallowed by the configuration of the EPT paging structures. */
    1275 #define VMX_EXIT_EPT_VIOLATION                                  48
    1276 /** 49 EPT misconfiguration. An attempt to access memory with a guest-physical
    1277  *  address encountered a misconfigured EPT paging-structure entry. */
    1278 #define VMX_EXIT_EPT_MISCONFIG                                  49
    1279 /** 50 INVEPT. Guest software attempted to execute INVEPT. */
    1280 #define VMX_EXIT_INVEPT                                         50
    1281 /** 51 RDTSCP. Guest software attempted to execute RDTSCP. */
    1282 #define VMX_EXIT_RDTSCP                                         51
    1283 /** 52 VMX-preemption timer expired. The preemption timer counted down to zero. */
    1284 #define VMX_EXIT_PREEMPT_TIMER                                  52
    1285 /** 53 INVVPID. Guest software attempted to execute INVVPID. */
    1286 #define VMX_EXIT_INVVPID                                        53
    1287 /** 54 WBINVD. Guest software attempted to execute WBINVD. */
    1288 #define VMX_EXIT_WBINVD                                         54
    1289 /** 55 XSETBV. Guest software attempted to execute XSETBV. */
    1290 #define VMX_EXIT_XSETBV                                         55
    1291 /** 56 APIC write. Guest completed write to virtual-APIC. */
    1292 #define VMX_EXIT_APIC_WRITE                                     56
    1293 /** 57 RDRAND. Guest software attempted to execute RDRAND. */
    1294 #define VMX_EXIT_RDRAND                                         57
    1295 /** 58 INVPCID. Guest software attempted to execute INVPCID. */
    1296 #define VMX_EXIT_INVPCID                                        58
    1297 /** 59 VMFUNC. Guest software attempted to execute VMFUNC. */
    1298 #define VMX_EXIT_VMFUNC                                         59
    1299 /** 60 ENCLS. Guest software attempted to execute ENCLS. */
    1300 #define VMX_EXIT_ENCLS                                          60
    1301 /** 61 - RDSEED - Guest software attempted to executed RDSEED and exiting was
    1302  * enabled. */
    1303 #define VMX_EXIT_RDSEED                                         61
    1304 /** 62 - Page-modification log full. */
    1305 #define VMX_EXIT_PML_FULL                                       62
    1306 /** 63 - XSAVES - Guest software attempted to executed XSAVES and exiting was
    1307  * enabled (XSAVES/XRSTORS was enabled too, of course). */
    1308 #define VMX_EXIT_XSAVES                                         63
    1309 /** 63 - XRSTORS - Guest software attempted to executed XRSTORS and exiting
    1310  * was enabled (XSAVES/XRSTORS was enabled too, of course). */
    1311 #define VMX_EXIT_XRSTORS                                        64
    1312 /** The maximum exit value (inclusive). */
    1313 #define VMX_EXIT_MAX                                            (VMX_EXIT_XRSTORS)
    1314 /** @} */
    1315 
    1316 
    1317 /** @name VM Instruction Errors.
    1318  * See Intel spec. "30.4 VM Instruction Error Numbers"
    1319  * @{
    1320  */
    1321 typedef enum
    1322 {
    1323     /** VMCALL executed in VMX root operation. */
    1324     VMXINSTRERR_VMCALL_VMXROOTMODE             = 1,
    1325     /** VMCLEAR with invalid physical address. */
    1326     VMXINSTRERR_VMCLEAR_INVALID_PHYSADDR       = 2,
    1327     /** VMCLEAR with VMXON pointer. */
    1328     VMXINSTRERR_VMCLEAR_VMXON_PTR              = 3,
    1329     /** VMLAUNCH with non-clear VMCS. */
    1330     VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS        = 4,
    1331     /** VMRESUME with non-launched VMCS. */
    1332     VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS     = 5,
    1333     /** VMRESUME after VMXOFF (VMXOFF and VMXON between VMLAUNCH and VMRESUME). */
    1334     VMXINSTRERR_VMRESUME_AFTER_VMXOFF          = 6,
    1335     /** VM-entry with invalid control field(s). */
    1336     VMXINSTRERR_VMENTRY_INVALID_CTLS           = 7,
    1337     /** VM-entry with invalid host-state field(s). */
    1338     VMXINSTRERR_VMENTRY_INVALID_HOST_STATE     = 8,
    1339     /** VMPTRLD with invalid physical address. */
    1340     VMXINSTRERR_VMPTRLD_INVALID_PHYSADDR       = 9,
    1341     /** VMPTRLD with VMXON pointer. */
    1342     VMXINSTRERR_VMPTRLD_VMXON_PTR              = 10,
    1343     /** VMPTRLD with incorrect VMCS revision identifier. */
    1344     VMXINSTRERR_VMPTRLD_INCORRECT_VMCS_REV     = 11,
    1345     /** VMREAD from unsupported VMCS component. */
    1346     VMXINSTRERR_VMREAD_INVALID_COMPONENT       = 12,
    1347     /** VMWRITE to unsupported VMCS component. */
    1348     VMXINSTRERR_VMWRITE_INVALID_COMPONENT      = 12,
    1349     /** VMWRITE to read-only VMCS component. */
    1350     VMXINSTRERR_VMWRITE_RO_COMPONENT           = 13,
    1351     /** VMXON executed in VMX root operation. */
    1352     VMXINSTRERR_VMXON_IN_VMXROOTMODE           = 15,
    1353     /** VM-entry with invalid executive-VMCS pointer. */
    1354     VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_PTR  = 16,
    1355     /** VM-entry with non-launched executive VMCS. */
    1356     VMXINSTRERR_VMENTRY_EXEC_VMCS_NON_LAUNCHED = 17,
    1357     /** VM-entry with executive-VMCS pointer not VMXON pointer. */
    1358     VMXINSTRERR_VMENTRY_EXEC_VMCS_PTR          = 18,
    1359     /** VMCALL with non-clear VMCS. */
    1360     VMXINSTRERR_VMCALL_NON_CLEAR_VMCS          = 19,
    1361     /** VMCALL with invalid VM-exit control fields. */
    1362     VMXINSTRERR_VMCALL_INVALID_EXITCTLS        = 20,
    1363     /** VMCALL with incorrect MSEG revision identifier. */
    1364     VMXINSTRERR_VMCALL_INVALID_MSEG_ID         = 22,
    1365     /** VMXOFF under dual-monitor treatment of SMIs and SMM. */
    1366     VMXINSTRERR_VMXOFF_DUAL_MON                = 23,
    1367     /** VMCALL with invalid SMM-monitor features. */
    1368     VMXINSTRERR_VMCALL_INVALID_SMMCTLS         = 24,
    1369     /** VM-entry with invalid VM-execution control fields in executive VMCS. */
    1370     VMXINSTRERR_VMENTRY_EXEC_VMCS_INVALID_CTLS = 25,
    1371     /** VM-entry with events blocked by MOV SS. */
    1372     VMXINSTRERR_VMENTRY_BLOCK_MOVSS            = 26,
    1373     /** Invalid operand to INVEPT/INVVPID. */
    1374     VMXINSTRERR_INVEPT_INVVPID_INVALID_OPERAND = 28
    1375 } VMXINSTRERR;
    1376 /** @} */
    1377 
    1378 
    1379 /** @name VMX abort reasons.
    1380  * See Intel spec. "27.7 VMX Aborts".
    1381  * Update HMVmxGetAbortDesc() if new reasons are added.
    1382  * @{
    1383  */
    1384 typedef enum
    1385 {
    1386     /** None - don't use this / uninitialized value. */
    1387     VMXABORT_NONE                  = 0,
    1388     /** VMX abort caused during saving of guest MSRs. */
    1389     VMXABORT_SAVE_GUEST_MSRS       = 1,
    1390     /** VMX abort caused during host PDPTE checks. */
    1391     VMXBOART_HOST_PDPTE            = 2,
    1392     /** VMX abort caused due to current VMCS being corrupted. */
    1393     VMXABORT_CURRENT_VMCS_CORRUPT  = 3,
    1394     /** VMX abort caused during loading of host MSRs. */
    1395     VMXABORT_LOAD_HOST_MSR         = 4,
    1396     /** VMX abort caused due to a machine-check exception during VM-exit. */
    1397     VMXABORT_MACHINE_CHECK_XCPT    = 5,
    1398     /** VMX abort caused due to invalid return from long mode. */
    1399     VMXABORT_HOST_NOT_IN_LONG_MODE = 6,
    1400     /* Type size hack. */
    1401     VMXABORT_32BIT_HACK            = 0x7fffffff
    1402 } VMXABORT;
    1403 AssertCompileSize(VMXABORT, 4);
    1404 /** @} */
    1405 
    1406 
    1407 /** @name VMX MSR - Basic VMX information.
    1408  * @{
    1409  */
    1410 /** VMCS (and related regions) memory type - Uncacheable. */
    1411 #define VMX_BASIC_MEM_TYPE_UC                                   0
    1412 /** VMCS (and related regions) memory type - Write back. */
    1413 #define VMX_BASIC_MEM_TYPE_WB                                   6
    1414 
    1415 /** Bit fields for MSR_IA32_VMX_BASIC.  */
    1416 /** VMCS revision identifier used by the processor. */
    1417 #define VMX_BF_BASIC_VMCS_ID_SHIFT                              0
    1418 #define VMX_BF_BASIC_VMCS_ID_MASK                               UINT64_C(0x000000007fffffff)
    1419 /** Bit 31 is reserved and RAZ. */
    1420 #define VMX_BF_BASIC_RSVD_32_SHIFT                              31
    1421 #define VMX_BF_BASIC_RSVD_32_MASK                               UINT64_C(0x0000000080000000)
    1422 /** VMCS size in bytes. */
    1423 #define VMX_BF_BASIC_VMCS_SIZE_SHIFT                            32
    1424 #define VMX_BF_BASIC_VMCS_SIZE_MASK                             UINT64_C(0x00001fff00000000)
    1425 /** Bits 45:47 are reserved. */
    1426 #define VMX_BF_BASIC_RSVD_45_47_SHIFT                           45
    1427 #define VMX_BF_BASIC_RSVD_45_47_MASK                            UINT64_C(0x0000e00000000000)
    1428 /** Width of physical addresses used for the VMCS and associated memory regions
    1429  *  (always 0 on CPUs that support Intel 64 architecture). */
    1430 #define VMX_BF_BASIC_PHYSADDR_WIDTH_SHIFT                       48
    1431 #define VMX_BF_BASIC_PHYSADDR_WIDTH_MASK                        UINT64_C(0x0001000000000000)
    1432 /** Dual-monitor treatment of SMI and SMM supported. */
    1433 #define VMX_BF_BASIC_DUAL_MON_SHIFT                             49
    1434 #define VMX_BF_BASIC_DUAL_MON_MASK                              UINT64_C(0x0002000000000000)
    1435 /** Memory type that must be used for the VMCS and associated memory regions. */
    1436 #define VMX_BF_BASIC_VMCS_MEM_TYPE_SHIFT                        50
    1437 #define VMX_BF_BASIC_VMCS_MEM_TYPE_MASK                         UINT64_C(0x003c000000000000)
    1438 /** VM-exit instruction information for INS/OUTS. */
    1439 #define VMX_BF_BASIC_VMCS_INS_OUTS_SHIFT                        54
    1440 #define VMX_BF_BASIC_VMCS_INS_OUTS_MASK                         UINT64_C(0x0040000000000000)
    1441 /** Whether 'true' VMX controls MSRs are supported for handling of default1 class
    1442  *  bits in VMX control MSRs. */
    1443 #define VMX_BF_BASIC_TRUE_CTLS_SHIFT                            55
    1444 #define VMX_BF_BASIC_TRUE_CTLS_MASK                             UINT64_C(0x0080000000000000)
    1445 /** Bits 56:63 are reserved and RAZ. */
    1446 #define VMX_BF_BASIC_RSVD_56_63_SHIFT                           56
    1447 #define VMX_BF_BASIC_RSVD_56_63_MASK                            UINT64_C(0xff00000000000000)
    1448 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_BASIC_, UINT64_C(0), UINT64_MAX,
    1449                             (VMCS_ID, RSVD_32, VMCS_SIZE, RSVD_45_47, PHYSADDR_WIDTH, DUAL_MON, VMCS_MEM_TYPE,
    1450                              VMCS_INS_OUTS, TRUE_CTLS, RSVD_56_63));
    1451 /** @} */
    1452 
    1453 
    1454 /** @name VMX MSR - Miscellaneous data.
    1455  * Bit fields for MSR_IA32_VMX_MISC.
    1456  * @{
    1457  */
    1458 /** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
    1459 #define VMX_MISC_EXIT_SAVE_EFER_LMA                             RT_BIT(5)
    1460 /** Whether Intel PT is supported in VMX operation. */
    1461 #define VMX_MISC_INTEL_PT                                       RT_BIT(14)
    1462 /** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
    1463  * VMWRITE cannot modify read-only VM-exit information fields. */
    1464 #define VMX_MISC_VMWRITE_ALL                                    RT_BIT(29)
    1465 /** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
    1466  *  instructions. */
    1467 #define VMX_MISC_ENTRY_INJECT_SOFT_INT                          RT_BIT(30)
    1468 /** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
    1469 #define VMX_MISC_MAX_MSRS(a_MiscMsr)                            (512 * (RT_BF_GET((a_MiscMsr), VMX_BF_MISC_MAX_MSRS) + 1))
    1470 /** Maximum CR3-target count supported by the CPU. */
    1471 #define VMX_MISC_CR3_TARGET_COUNT(a_MiscMsr)                    (((a) >> 16) & 0xff)
    1472 /** Relationship between the preemption timer and tsc. */
    1473 #define VMX_BF_MISC_PREEMPT_TIMER_TSC_SHIFT                     0
    1474 #define VMX_BF_MISC_PREEMPT_TIMER_TSC_MASK                      UINT64_C(0x000000000000001f)
    1475 /** Whether VM-exit stores EFER.LMA into the "IA32e mode guest" field. */
    1476 #define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_SHIFT                    5
    1477 #define VMX_BF_MISC_EXIT_SAVE_EFER_LMA_MASK                     UINT64_C(0x0000000000000020)
    1478 /** Activity states supported by the implementation. */
    1479 #define VMX_BF_MISC_ACTIVITY_STATES_SHIFT                       6
    1480 #define VMX_BF_MISC_ACTIVITY_STATES_MASK                        UINT64_C(0x00000000000001c0)
    1481 /** Bits 9:13 is reserved and RAZ. */
    1482 #define VMX_BF_MISC_RSVD_9_13_SHIFT                             9
    1483 #define VMX_BF_MISC_RSVD_9_13_MASK                              UINT64_C(0x0000000000003e00)
    1484 /** Whether Intel PT (Processor Trace) can be used in VMX operation.  */
    1485 #define VMX_BF_MISC_INTEL_PT_SHIFT                              14
    1486 #define VMX_BF_MISC_INTEL_PT_MASK                               UINT64_C(0x0000000000004000)
    1487 /** Whether RDMSR can be used to read IA32_SMBASE MSR in SMM. */
    1488 #define VMX_BF_MISC_SMM_READ_SMBASE_MSR_SHIFT                   15
    1489 #define VMX_BF_MISC_SMM_READ_SMBASE_MSR_MASK                    UINT64_C(0x0000000000008000)
    1490 /** Number of CR3 target values supported by the processor. (0-256) */
    1491 #define VMX_BF_MISC_CR3_TARGET_SHIFT                            16
    1492 #define VMX_BF_MISC_CR3_TARGET_MASK                             UINT64_C(0x0000000001ff0000)
    1493 /** Maximum number of MSRs in the VMCS. */
    1494 #define VMX_BF_MISC_MAX_MSRS_SHIFT                              25
    1495 #define VMX_BF_MISC_MAX_MSRS_MASK                               UINT64_C(0x000000000e000000)
    1496 /** Whether IA32_SMM_MONITOR_CTL MSR can be modified to allow VMXOFF to block
    1497  *  SMIs. */
    1498 #define VMX_BF_MISC_VMXOFF_BLOCK_SMI_SHIFT                      28
    1499 #define VMX_BF_MISC_VMXOFF_BLOCK_SMI_MASK                       UINT64_C(0x0000000010000000)
    1500 /** Whether VMWRITE to any valid VMCS field incl. read-only fields, otherwise
    1501  * VMWRITE cannot modify read-only VM-exit information fields. */
    1502 #define VMX_BF_MISC_VMWRITE_ALL_SHIFT                           29
    1503 #define VMX_BF_MISC_VMWRITE_ALL_MASK                            UINT64_C(0x0000000020000000)
    1504 /** Whether VM-entry can inject software interrupts, INT1 (ICEBP) with 0-length
    1505  *  instructions. */
    1506 #define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_SHIFT                 30
    1507 #define VMX_BF_MISC_ENTRY_INJECT_SOFT_INT_MASK                  UINT64_C(0x0000000040000000)
    1508 /** Bit 31 is reserved and RAZ. */
    1509 #define VMX_BF_MISC_RSVD_31_SHIFT                               31
    1510 #define VMX_BF_MISC_RSVD_31_MASK                                UINT64_C(0x0000000080000000)
    1511 /** 32-bit MSEG revision ID used by the processor. */
    1512 #define VMX_BF_MISC_MSEG_ID_SHIFT                               32
    1513 #define VMX_BF_MISC_MSEG_ID_MASK                                UINT64_C(0xffffffff00000000)
    1514 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_MISC_, UINT64_C(0), UINT64_MAX,
    1515                             (PREEMPT_TIMER_TSC, EXIT_SAVE_EFER_LMA, ACTIVITY_STATES, RSVD_9_13, INTEL_PT, SMM_READ_SMBASE_MSR,
    1516                              CR3_TARGET, MAX_MSRS, VMXOFF_BLOCK_SMI, VMWRITE_ALL, ENTRY_INJECT_SOFT_INT, RSVD_31, MSEG_ID));
    1517 /** @} */
    1518 
    1519 /** @name VMX MSR - VMCS enumeration.
    1520  * Bit fields for MSR_IA32_VMX_VMCS_ENUM.
    1521  * @{
    1522  */
    1523 /** Bit 0 is reserved and RAZ.  */
    1524 #define VMX_BF_VMCS_ENUM_RSVD_0_SHIFT                           0
    1525 #define VMX_BF_VMCS_ENUM_RSVD_0_MASK                            UINT64_C(0x0000000000000001)
    1526 /** Highest index value used in VMCS field encoding. */
    1527 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_SHIFT                      1
    1528 #define VMX_BF_VMCS_ENUM_HIGHEST_IDX_MASK                       UINT64_C(0x00000000000003fe)
    1529 /** Bit 10:63 is reserved and RAZ.  */
    1530 #define VMX_BF_VMCS_ENUM_RSVD_10_63_SHIFT                       10
    1531 #define VMX_BF_VMCS_ENUM_RSVD_10_63_MASK                        UINT64_C(0xfffffffffffffc00)
    1532 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENUM_, UINT64_C(0), UINT64_MAX,
    1533                             (RSVD_0, HIGHEST_IDX, RSVD_10_63));
    1534 /** @} */
    1535 
    1536 
    1537 /** @name VMX MSR - VM Functions.
    1538  * Bit fields for MSR_IA32_VMX_VMFUNC.
    1539  * @{
    1540  */
    1541 /** EPTP-switching function changes the value of the EPTP to one chosen from the EPTP list. */
    1542 #define VMX_BF_VMFUNC_EPTP_SWITCHING_SHIFT                      0
    1543 #define VMX_BF_VMFUNC_EPTP_SWITCHING_MASK                       UINT64_C(0x0000000000000001)
    1544 /** Bits 1:63 are reserved and RAZ. */
    1545 #define VMX_BF_VMFUNC_RSVD_1_63_SHIFT                           1
    1546 #define VMX_BF_VMFUNC_RSVD_1_63_MASK                            UINT64_C(0xfffffffffffffffe)
    1547 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMFUNC_, UINT64_C(0), UINT64_MAX,
    1548                             (EPTP_SWITCHING, RSVD_1_63));
    1549 /** @} */
    1550 
    1551 
    1552 /** @name VMX MSR - EPT/VPID capabilities.
    1553  * @{
    1554  */
    1555 #define MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY                    RT_BIT_64(0)
    1556 #define MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4            RT_BIT_64(6)
    1557 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC                        RT_BIT_64(8)
    1558 #define MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB                        RT_BIT_64(14)
    1559 #define MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M                        RT_BIT_64(16)
    1560 #define MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G                      RT_BIT_64(17)
    1561 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT                        RT_BIT_64(20)
    1562 #define MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY              RT_BIT_64(21)
    1563 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT         RT_BIT_64(25)
    1564 #define MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS           RT_BIT_64(26)
    1565 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID                       RT_BIT_64(32)
    1566 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR            RT_BIT_64(40)
    1567 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT        RT_BIT_64(41)
    1568 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS          RT_BIT_64(42)
    1569 #define MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS  RT_BIT_64(43)
    1570 /** @} */
    1571 
    1572 
    1573 /** @name Extended Page Table Pointer (EPTP)
    1574  * @{
    1575  */
    1576 /** Uncachable EPT paging structure memory type. */
    1577 #define VMX_EPT_MEMTYPE_UC                                      0
    1578 /** Write-back EPT paging structure memory type. */
    1579 #define VMX_EPT_MEMTYPE_WB                                      6
    1580 /** Shift value to get the EPT page walk length (bits 5-3) */
    1581 #define VMX_EPT_PAGE_WALK_LENGTH_SHIFT                          3
    1582 /** Mask value to get the EPT page walk length (bits 5-3) */
    1583 #define VMX_EPT_PAGE_WALK_LENGTH_MASK                           7
    1584 /** Default EPT page-walk length (1 less than the actual EPT page-walk
    1585  *  length) */
    1586 #define VMX_EPT_PAGE_WALK_LENGTH_DEFAULT                        3
    1587 /** @} */
    1588 
    1589 
    1590 /** @name VMCS field encoding: 16-bit guest fields.
    1591  * @{
    1592  */
    1593 #define VMX_VMCS16_VPID                                         0x0000
    1594 #define VMX_VMCS16_POSTED_INT_NOTIFY_VECTOR                     0x0002
    1595 #define VMX_VMCS16_EPTP_INDEX                                   0x0004
    1596 #define VMX_VMCS16_GUEST_ES_SEL                                 0x0800
    1597 #define VMX_VMCS16_GUEST_CS_SEL                                 0x0802
    1598 #define VMX_VMCS16_GUEST_SS_SEL                                 0x0804
    1599 #define VMX_VMCS16_GUEST_DS_SEL                                 0x0806
    1600 #define VMX_VMCS16_GUEST_FS_SEL                                 0x0808
    1601 #define VMX_VMCS16_GUEST_GS_SEL                                 0x080a
    1602 #define VMX_VMCS16_GUEST_LDTR_SEL                               0x080c
    1603 #define VMX_VMCS16_GUEST_TR_SEL                                 0x080e
    1604 #define VMX_VMCS16_GUEST_INTR_STATUS                            0x0810
    1605 #define VMX_VMCS16_GUEST_PML_INDEX                              0x0812
    1606 /** @} */
    1607 
    1608 
    1609 /** @name VMCS field encoding: 16-bits host fields.
    1610  * @{
    1611  */
    1612 #define VMX_VMCS16_HOST_ES_SEL                                  0x0c00
    1613 #define VMX_VMCS16_HOST_CS_SEL                                  0x0c02
    1614 #define VMX_VMCS16_HOST_SS_SEL                                  0x0c04
    1615 #define VMX_VMCS16_HOST_DS_SEL                                  0x0c06
    1616 #define VMX_VMCS16_HOST_FS_SEL                                  0x0c08
    1617 #define VMX_VMCS16_HOST_GS_SEL                                  0x0c0a
    1618 #define VMX_VMCS16_HOST_TR_SEL                                  0x0c0c
    1619 /** @} */
    1620 
    1621 
    1622 /** @name VMCS field encoding: 64-bit control fields.
    1623  * @{
    1624  */
    1625 #define VMX_VMCS64_CTRL_IO_BITMAP_A_FULL                        0x2000
    1626 #define VMX_VMCS64_CTRL_IO_BITMAP_A_HIGH                        0x2001
    1627 #define VMX_VMCS64_CTRL_IO_BITMAP_B_FULL                        0x2002
    1628 #define VMX_VMCS64_CTRL_IO_BITMAP_B_HIGH                        0x2003
    1629 #define VMX_VMCS64_CTRL_MSR_BITMAP_FULL                         0x2004
    1630 #define VMX_VMCS64_CTRL_MSR_BITMAP_HIGH                         0x2005
    1631 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_FULL                     0x2006
    1632 #define VMX_VMCS64_CTRL_EXIT_MSR_STORE_HIGH                     0x2007
    1633 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_FULL                      0x2008
    1634 #define VMX_VMCS64_CTRL_EXIT_MSR_LOAD_HIGH                      0x2009
    1635 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_FULL                     0x200a
    1636 #define VMX_VMCS64_CTRL_ENTRY_MSR_LOAD_HIGH                     0x200b
    1637 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_FULL                      0x200c
    1638 #define VMX_VMCS64_CTRL_EXEC_VMCS_PTR_HIGH                      0x200d
    1639 #define VMX_VMCS64_CTRL_EXEC_PML_ADDR_FULL                      0x200e
    1640 #define VMX_VMCS64_CTRL_EXEC_PML_ADDR_HIGH                      0x200f
    1641 #define VMX_VMCS64_CTRL_TSC_OFFSET_FULL                         0x2010
    1642 #define VMX_VMCS64_CTRL_TSC_OFFSET_HIGH                         0x2011
    1643 #define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_FULL                 0x2012
    1644 #define VMX_VMCS64_CTRL_VIRT_APIC_PAGEADDR_HIGH                 0x2013
    1645 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_FULL                    0x2014
    1646 #define VMX_VMCS64_CTRL_APIC_ACCESSADDR_HIGH                    0x2015
    1647 #define VMX_VMCS64_CTRL_POSTED_INTR_DESC_FULL                   0x2016
    1648 #define VMX_VMCS64_CTRL_POSTED_INTR_DESC_HIGH                   0x2017
    1649 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_FULL                       0x2018
    1650 #define VMX_VMCS64_CTRL_VMFUNC_CTRLS_HIGH                       0x2019
    1651 #define VMX_VMCS64_CTRL_EPTP_FULL                               0x201a
    1652 #define VMX_VMCS64_CTRL_EPTP_HIGH                               0x201b
    1653 #define VMX_VMCS64_CTRL_EOI_BITMAP_0_FULL                       0x201c
    1654 #define VMX_VMCS64_CTRL_EOI_BITMAP_0_HIGH                       0x201d
    1655 #define VMX_VMCS64_CTRL_EOI_BITMAP_1_FULL                       0x201e
    1656 #define VMX_VMCS64_CTRL_EOI_BITMAP_1_HIGH                       0x201f
    1657 #define VMX_VMCS64_CTRL_EOI_BITMAP_2_FULL                       0x2020
    1658 #define VMX_VMCS64_CTRL_EOI_BITMAP_2_HIGH                       0x2021
    1659 #define VMX_VMCS64_CTRL_EOI_BITMAP_3_FULL                       0x2022
    1660 #define VMX_VMCS64_CTRL_EOI_BITMAP_3_HIGH                       0x2023
    1661 #define VMX_VMCS64_CTRL_EPTP_LIST_FULL                          0x2024
    1662 #define VMX_VMCS64_CTRL_EPTP_LIST_HIGH                          0x2025
    1663 #define VMX_VMCS64_CTRL_VMREAD_BITMAP_FULL                      0x2026
    1664 #define VMX_VMCS64_CTRL_VMREAD_BITMAP_HIGH                      0x2027
    1665 #define VMX_VMCS64_CTRL_VMWRITE_BITMAP_FULL                     0x2028
    1666 #define VMX_VMCS64_CTRL_VMWRITE_BITMAP_HIGH                     0x2029
    1667 #define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_FULL                 0x202a
    1668 #define VMX_VMCS64_CTRL_VIRTXCPT_INFO_ADDR_HIGH                 0x202b
    1669 #define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_FULL                 0x202c
    1670 #define VMX_VMCS64_CTRL_XSS_EXITING_BITMAP_HIGH                 0x202d
    1671 #define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_FULL               0x202e
    1672 #define VMX_VMCS64_CTRL_ENCLS_EXITING_BITMAP_HIGH               0x202f
    1673 #define VMX_VMCS64_CTRL_TSC_MULTIPLIER_FULL                     0x2032
    1674 #define VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH                     0x2033
    1675 /** @} */
    1676 
    1677 
    1678 /** @name VMCS field encoding: 64-bit read-only data fields.
    1679  * @{
    1680  */
    1681 #define VMX_VMCS64_RO_GUEST_PHYS_ADDR_FULL                      0x2400
    1682 #define VMX_VMCS64_RO_GUEST_PHYS_ADDR_HIGH                      0x2401
    1683 /** @} */
    1684 
    1685 
    1686 /** @name VMCS field encoding: 64-bit guest fields.
    1687  * @{
    1688  */
    1689 #define VMX_VMCS64_GUEST_VMCS_LINK_PTR_FULL                     0x2800
    1690 #define VMX_VMCS64_GUEST_VMCS_LINK_PTR_HIGH                     0x2801
    1691 #define VMX_VMCS64_GUEST_DEBUGCTL_FULL                          0x2802
    1692 #define VMX_VMCS64_GUEST_DEBUGCTL_HIGH                          0x2803
    1693 #define VMX_VMCS64_GUEST_PAT_FULL                               0x2804
    1694 #define VMX_VMCS64_GUEST_PAT_HIGH                               0x2805
    1695 #define VMX_VMCS64_GUEST_EFER_FULL                              0x2806
    1696 #define VMX_VMCS64_GUEST_EFER_HIGH                              0x2807
    1697 #define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_FULL                  0x2808
    1698 #define VMX_VMCS64_GUEST_PERF_GLOBAL_CTRL_HIGH                  0x2809
    1699 #define VMX_VMCS64_GUEST_PDPTE0_FULL                            0x280a
    1700 #define VMX_VMCS64_GUEST_PDPTE0_HIGH                            0x280b
    1701 #define VMX_VMCS64_GUEST_PDPTE1_FULL                            0x280c
    1702 #define VMX_VMCS64_GUEST_PDPTE1_HIGH                            0x280d
    1703 #define VMX_VMCS64_GUEST_PDPTE2_FULL                            0x280e
    1704 #define VMX_VMCS64_GUEST_PDPTE2_HIGH                            0x280f
    1705 #define VMX_VMCS64_GUEST_PDPTE3_FULL                            0x2810
    1706 #define VMX_VMCS64_GUEST_PDPTE3_HIGH                            0x2811
    1707 #define VMX_VMCS64_GUEST_BNDCFGS_FULL                           0x2812
    1708 #define VMX_VMCS64_GUEST_BNDCFGS_HIGH                           0x2813
    1709 /** @} */
    1710 
    1711 
    1712 /** @name VMCS field encoding: 64-bit host fields.
    1713  * @{
    1714  */
    1715 #define VMX_VMCS64_HOST_PAT_FULL                                0x2c00
    1716 #define VMX_VMCS64_HOST_PAT_HIGH                                0x2c01
    1717 #define VMX_VMCS64_HOST_EFER_FULL                               0x2c02
    1718 #define VMX_VMCS64_HOST_EFER_HIGH                               0x2c03
    1719 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_FULL                   0x2c04
    1720 #define VMX_VMCS64_HOST_PERF_GLOBAL_CTRL_HIGH                   0x2c05
    1721 /** @} */
    1722 
    1723 
    1724 /** @name VMCS field encoding: 32-bit control fields.
    1725  * @{
    1726  */
    1727 #define VMX_VMCS32_CTRL_PIN_EXEC                                0x4000
    1728 #define VMX_VMCS32_CTRL_PROC_EXEC                               0x4002
    1729 #define VMX_VMCS32_CTRL_EXCEPTION_BITMAP                        0x4004
    1730 #define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MASK                    0x4006
    1731 #define VMX_VMCS32_CTRL_PAGEFAULT_ERROR_MATCH                   0x4008
    1732 #define VMX_VMCS32_CTRL_CR3_TARGET_COUNT                        0x400a
    1733 #define VMX_VMCS32_CTRL_EXIT                                    0x400c
    1734 #define VMX_VMCS32_CTRL_EXIT_MSR_STORE_COUNT                    0x400e
    1735 #define VMX_VMCS32_CTRL_EXIT_MSR_LOAD_COUNT                     0x4010
    1736 #define VMX_VMCS32_CTRL_ENTRY                                   0x4012
    1737 #define VMX_VMCS32_CTRL_ENTRY_MSR_LOAD_COUNT                    0x4014
    1738 #define VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO                 0x4016
    1739 #define VMX_VMCS32_CTRL_ENTRY_EXCEPTION_ERRCODE                 0x4018
    1740 #define VMX_VMCS32_CTRL_ENTRY_INSTR_LENGTH                      0x401a
    1741 #define VMX_VMCS32_CTRL_TPR_THRESHOLD                           0x401c
    1742 #define VMX_VMCS32_CTRL_PROC_EXEC2                              0x401e
    1743 #define VMX_VMCS32_CTRL_PLE_GAP                                 0x4020
    1744 #define VMX_VMCS32_CTRL_PLE_WINDOW                              0x4022
    1745 /** @} */
    1746 
    1747 
    1748 /** @name VMCS field encoding: 32-bits read-only fields.
    1749  * @{
    1750  */
    1751 #define VMX_VMCS32_RO_VM_INSTR_ERROR                            0x4400
    1752 #define VMX_VMCS32_RO_EXIT_REASON                               0x4402
    1753 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_INFO                    0x4404
    1754 #define VMX_VMCS32_RO_EXIT_INTERRUPTION_ERROR_CODE              0x4406
    1755 #define VMX_VMCS32_RO_IDT_VECTORING_INFO                        0x4408
    1756 #define VMX_VMCS32_RO_IDT_VECTORING_ERROR_CODE                  0x440a
    1757 #define VMX_VMCS32_RO_EXIT_INSTR_LENGTH                         0x440c
    1758 #define VMX_VMCS32_RO_EXIT_INSTR_INFO                           0x440e
    1759 /** @} */
    1760 
    1761 
    1762 /** @name VMCS field encoding: 32-bit guest-state fields.
    1763  * @{
    1764  */
    1765 #define VMX_VMCS32_GUEST_ES_LIMIT                               0x4800
    1766 #define VMX_VMCS32_GUEST_CS_LIMIT                               0x4802
    1767 #define VMX_VMCS32_GUEST_SS_LIMIT                               0x4804
    1768 #define VMX_VMCS32_GUEST_DS_LIMIT                               0x4806
    1769 #define VMX_VMCS32_GUEST_FS_LIMIT                               0x4808
    1770 #define VMX_VMCS32_GUEST_GS_LIMIT                               0x480a
    1771 #define VMX_VMCS32_GUEST_LDTR_LIMIT                             0x480c
    1772 #define VMX_VMCS32_GUEST_TR_LIMIT                               0x480e
    1773 #define VMX_VMCS32_GUEST_GDTR_LIMIT                             0x4810
    1774 #define VMX_VMCS32_GUEST_IDTR_LIMIT                             0x4812
    1775 #define VMX_VMCS32_GUEST_ES_ACCESS_RIGHTS                       0x4814
    1776 #define VMX_VMCS32_GUEST_CS_ACCESS_RIGHTS                       0x4816
    1777 #define VMX_VMCS32_GUEST_SS_ACCESS_RIGHTS                       0x4818
    1778 #define VMX_VMCS32_GUEST_DS_ACCESS_RIGHTS                       0x481a
    1779 #define VMX_VMCS32_GUEST_FS_ACCESS_RIGHTS                       0x481c
    1780 #define VMX_VMCS32_GUEST_GS_ACCESS_RIGHTS                       0x481e
    1781 #define VMX_VMCS32_GUEST_LDTR_ACCESS_RIGHTS                     0x4820
    1782 #define VMX_VMCS32_GUEST_TR_ACCESS_RIGHTS                       0x4822
    1783 #define VMX_VMCS32_GUEST_INT_STATE                              0x4824
    1784 #define VMX_VMCS32_GUEST_ACTIVITY_STATE                         0x4826
    1785 #define VMX_VMCS32_GUEST_SMBASE                                 0x4828
    1786 #define VMX_VMCS32_GUEST_SYSENTER_CS                            0x482a
    1787 #define VMX_VMCS32_PREEMPT_TIMER_VALUE                          0x482e
    1788 /** @} */
    1789 
    1790 
    1791 /** @name VMCS field encoding: 32-bit host-state fields.
    1792  * @{
    1793  */
    1794 #define VMX_VMCS32_HOST_SYSENTER_CS                             0x4C00
    1795 /** @} */
    1796 
    1797 
    1798 /** @name Natural width control fields.
    1799  * @{
    1800  */
    1801 #define VMX_VMCS_CTRL_CR0_MASK                                  0x6000
    1802 #define VMX_VMCS_CTRL_CR4_MASK                                  0x6002
    1803 #define VMX_VMCS_CTRL_CR0_READ_SHADOW                           0x6004
    1804 #define VMX_VMCS_CTRL_CR4_READ_SHADOW                           0x6006
    1805 #define VMX_VMCS_CTRL_CR3_TARGET_VAL0                           0x6008
    1806 #define VMX_VMCS_CTRL_CR3_TARGET_VAL1                           0x600a
    1807 #define VMX_VMCS_CTRL_CR3_TARGET_VAL2                           0x600c
    1808 #define VMX_VMCS_CTRL_CR3_TARGET_VAL3                           0x600e
    1809 /** @} */
    1810 
    1811 
    1812 /** @name Natural width read-only data fields.
    1813  * @{
    1814  */
    1815 #define VMX_VMCS_RO_EXIT_QUALIFICATION                          0x6400
    1816 #define VMX_VMCS_RO_IO_RCX                                      0x6402
    1817 #define VMX_VMCS_RO_IO_RSX                                      0x6404
    1818 #define VMX_VMCS_RO_IO_RDI                                      0x6406
    1819 #define VMX_VMCS_RO_IO_RIP                                      0x6408
    1820 #define VMX_VMCS_RO_GUEST_LINEAR_ADDR                           0x640a
    1821 /** @} */
    1822 
    1823 
    1824 /** @name VMCS field encoding: Natural width guest-state fields.
    1825  * @{
    1826  */
    1827 #define VMX_VMCS_GUEST_CR0                                      0x6800
    1828 #define VMX_VMCS_GUEST_CR3                                      0x6802
    1829 #define VMX_VMCS_GUEST_CR4                                      0x6804
    1830 #define VMX_VMCS_GUEST_ES_BASE                                  0x6806
    1831 #define VMX_VMCS_GUEST_CS_BASE                                  0x6808
    1832 #define VMX_VMCS_GUEST_SS_BASE                                  0x680a
    1833 #define VMX_VMCS_GUEST_DS_BASE                                  0x680c
    1834 #define VMX_VMCS_GUEST_FS_BASE                                  0x680e
    1835 #define VMX_VMCS_GUEST_GS_BASE                                  0x6810
    1836 #define VMX_VMCS_GUEST_LDTR_BASE                                0x6812
    1837 #define VMX_VMCS_GUEST_TR_BASE                                  0x6814
    1838 #define VMX_VMCS_GUEST_GDTR_BASE                                0x6816
    1839 #define VMX_VMCS_GUEST_IDTR_BASE                                0x6818
    1840 #define VMX_VMCS_GUEST_DR7                                      0x681a
    1841 #define VMX_VMCS_GUEST_RSP                                      0x681c
    1842 #define VMX_VMCS_GUEST_RIP                                      0x681e
    1843 #define VMX_VMCS_GUEST_RFLAGS                                   0x6820
    1844 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS                      0x6822
    1845 #define VMX_VMCS_GUEST_SYSENTER_ESP                             0x6824
    1846 #define VMX_VMCS_GUEST_SYSENTER_EIP                             0x6826
    1847 /** @} */
    1848 
    1849 
    1850 /** @name VMCS field encoding: Natural width host-state fields.
    1851  * @{
    1852  */
    1853 #define VMX_VMCS_HOST_CR0                                       0x6c00
    1854 #define VMX_VMCS_HOST_CR3                                       0x6c02
    1855 #define VMX_VMCS_HOST_CR4                                       0x6c04
    1856 #define VMX_VMCS_HOST_FS_BASE                                   0x6c06
    1857 #define VMX_VMCS_HOST_GS_BASE                                   0x6c08
    1858 #define VMX_VMCS_HOST_TR_BASE                                   0x6c0a
    1859 #define VMX_VMCS_HOST_GDTR_BASE                                 0x6c0c
    1860 #define VMX_VMCS_HOST_IDTR_BASE                                 0x6c0e
    1861 #define VMX_VMCS_HOST_SYSENTER_ESP                              0x6c10
    1862 #define VMX_VMCS_HOST_SYSENTER_EIP                              0x6c12
    1863 #define VMX_VMCS_HOST_RSP                                       0x6c14
    1864 #define VMX_VMCS_HOST_RIP                                       0x6c16
    1865 /** @} */
    1866 
    1867 
    1868 /** @name VMCS field encoding: Access.
    1869  * @{ */
    1870 typedef enum
    1871 {
    1872     VMXVMCSFIELDACCESS_FULL = 0,
    1873     VMXVMCSFIELDACCESS_HIGH
    1874 } VMXVMCSFIELDACCESS;
    1875 AssertCompileSize(VMXVMCSFIELDACCESS, 4);
    1876 /** @} */
    1877 
    1878 
    1879 /** @name VMCS field encoding: Type.
    1880  * @{ */
    1881 typedef enum
    1882 {
    1883     VMXVMCSFIELDTYPE_CONTROL = 0,
    1884     VMXVMCSFIELDTYPE_VMEXIT_INFO,
    1885     VMXVMCSFIELDTYPE_GUEST_STATE,
    1886     VMXVMCSFIELDTYPE_HOST_STATE
    1887 } VMXVMCSFIELDTYPE;
    1888 AssertCompileSize(VMXVMCSFIELDTYPE, 4);
    1889 /** @} */
    1890 
    1891 
    1892 /** @name VMCS field encoding: Width.
    1893  * @{ */
    1894 typedef enum
    1895 {
    1896     VMXVMCSFIELDWIDTH_16BIT = 0,
    1897     VMXVMCSFIELDWIDTH_64BIT,
    1898     VMXVMCSFIELDWIDTH_32BIT,
    1899     VMXVMCSFIELDWIDTH_NATURAL
    1900 } VMXVMCSFIELDWIDTH;
    1901 AssertCompileSize(VMXVMCSFIELDWIDTH, 4);
    1902 /** @} */
    1903 
    1904 /** @name VM-entry instruction length.
    1905  * @{ */
    1906 /** The maximum valid value for VM-entry instruction length while injecting a
    1907  *  software interrupt, software exception or privileged software exception. */
    1908 #define VMX_ENTRY_INSTR_LEN_MAX                                 15
    1909 /** @} */
    1910 
    1911 
    1912 /** @name VM-entry register masks.
    1913  * @{ */
    1914 /** CR0 bits ignored on VM-entry (ET, NW, CD and reserved bits bits 6:15, bit 17,
    1915  *  bits 19:28). */
    1916 #define VMX_ENTRY_CR0_IGNORE_MASK                               UINT64_C(0x7ffaffc0)
    1917 /** DR7 bits set here are always cleared on VM-entry (bit 12, bits 14:15). */
    1918 #define VMX_ENTRY_DR7_MBZ_MASK                                  UINT64_C(0xd000)
    1919 /** DR7 bits set here are always set on VM-entry (bit 10). */
    1920 #define VMX_ENTRY_DR7_MB1_MASK                                  UINT64_C(0x400)
    1921 /** @} */
    1922 
    1923 
    1924 /** @name Pin-based VM-execution controls.
    1925  * @{
    1926  */
    1927 /** External interrupt exiting. */
    1928 #define VMX_PIN_CTLS_EXT_INT_EXIT                               RT_BIT(0)
    1929 /** NMI exiting. */
    1930 #define VMX_PIN_CTLS_NMI_EXIT                                   RT_BIT(3)
    1931 /** Virtual NMIs. */
    1932 #define VMX_PIN_CTLS_VIRT_NMI                                   RT_BIT(5)
    1933 /** Activate VMX preemption timer. */
    1934 #define VMX_PIN_CTLS_PREEMPT_TIMER                              RT_BIT(6)
    1935 /** Process interrupts with the posted-interrupt notification vector. */
    1936 #define VMX_PIN_CTLS_POSTED_INT                                 RT_BIT(7)
    1937 /** Default1 class when true capability MSRs are not supported. */
    1938 #define VMX_PIN_CTLS_DEFAULT1                                   UINT32_C(0x00000016)
    1939 
    1940 /** Bit fields for MSR_IA32_VMX_PINBASED_CTLS and Pin-based VM-execution
    1941  *  controls field in the VMCS. */
    1942 #define VMX_BF_PIN_CTLS_EXT_INT_EXIT_SHIFT                      0
    1943 #define VMX_BF_PIN_CTLS_EXT_INT_EXIT_MASK                       UINT32_C(0x00000001)
    1944 #define VMX_BF_PIN_CTLS_UNDEF_1_2_SHIFT                         1
    1945 #define VMX_BF_PIN_CTLS_UNDEF_1_2_MASK                          UINT32_C(0x00000006)
    1946 #define VMX_BF_PIN_CTLS_NMI_EXIT_SHIFT                          3
    1947 #define VMX_BF_PIN_CTLS_NMI_EXIT_MASK                           UINT32_C(0x00000008)
    1948 #define VMX_BF_PIN_CTLS_UNDEF_4_SHIFT                           4
    1949 #define VMX_BF_PIN_CTLS_UNDEF_4_MASK                            UINT32_C(0x00000010)
    1950 #define VMX_BF_PIN_CTLS_VIRT_NMI_SHIFT                          5
    1951 #define VMX_BF_PIN_CTLS_VIRT_NMI_MASK                           UINT32_C(0x00000020)
    1952 #define VMX_BF_PIN_CTLS_PREEMPT_TIMER_SHIFT                     6
    1953 #define VMX_BF_PIN_CTLS_PREEMPT_TIMER_MASK                      UINT32_C(0x00000040)
    1954 #define VMX_BF_PIN_CTLS_POSTED_INT_SHIFT                        7
    1955 #define VMX_BF_PIN_CTLS_POSTED_INT_MASK                         UINT32_C(0x00000080)
    1956 #define VMX_BF_PIN_CTLS_UNDEF_8_31_SHIFT                        8
    1957 #define VMX_BF_PIN_CTLS_UNDEF_8_31_MASK                         UINT32_C(0xffffff00)
    1958 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PIN_CTLS_, UINT32_C(0), UINT32_MAX,
    1959                             (EXT_INT_EXIT, UNDEF_1_2, NMI_EXIT, UNDEF_4, VIRT_NMI, PREEMPT_TIMER, POSTED_INT, UNDEF_8_31));
    1960 /** @} */
    1961 
    1962 
    1963 /** @name Processor-based VM-execution controls.
    1964  * @{
    1965  */
    1966 /** VM-exit as soon as RFLAGS.IF=1 and no blocking is active. */
    1967 #define VMX_PROC_CTLS_INT_WINDOW_EXIT                           RT_BIT(2)
    1968 /** Use timestamp counter offset. */
    1969 #define VMX_PROC_CTLS_USE_TSC_OFFSETTING                        RT_BIT(3)
    1970 /** VM-exit when executing the HLT instruction. */
    1971 #define VMX_PROC_CTLS_HLT_EXIT                                  RT_BIT(7)
    1972 /** VM-exit when executing the INVLPG instruction. */
    1973 #define VMX_PROC_CTLS_INVLPG_EXIT                               RT_BIT(9)
    1974 /** VM-exit when executing the MWAIT instruction. */
    1975 #define VMX_PROC_CTLS_MWAIT_EXIT                                RT_BIT(10)
    1976 /** VM-exit when executing the RDPMC instruction. */
    1977 #define VMX_PROC_CTLS_RDPMC_EXIT                                RT_BIT(11)
    1978 /** VM-exit when executing the RDTSC/RDTSCP instruction. */
    1979 #define VMX_PROC_CTLS_RDTSC_EXIT                                RT_BIT(12)
    1980 /** VM-exit when executing the MOV to CR3 instruction. (forced to 1 on the
    1981  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    1982 #define VMX_PROC_CTLS_CR3_LOAD_EXIT                             RT_BIT(15)
    1983 /** VM-exit when executing the MOV from CR3 instruction. (forced to 1 on the
    1984  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    1985 #define VMX_PROC_CTLS_CR3_STORE_EXIT                            RT_BIT(16)
    1986 /** VM-exit on CR8 loads. */
    1987 #define VMX_PROC_CTLS_CR8_LOAD_EXIT                             RT_BIT(19)
    1988 /** VM-exit on CR8 stores. */
    1989 #define VMX_PROC_CTLS_CR8_STORE_EXIT                            RT_BIT(20)
    1990 /** Use TPR shadow. */
    1991 #define VMX_PROC_CTLS_USE_TPR_SHADOW                            RT_BIT(21)
    1992 /** VM-exit when virtual NMI blocking is disabled. */
    1993 #define VMX_PROC_CTLS_NMI_WINDOW_EXIT                           RT_BIT(22)
    1994 /** VM-exit when executing a MOV DRx instruction. */
    1995 #define VMX_PROC_CTLS_MOV_DR_EXIT                               RT_BIT(23)
    1996 /** VM-exit when executing IO instructions. */
    1997 #define VMX_PROC_CTLS_UNCOND_IO_EXIT                            RT_BIT(24)
    1998 /** Use IO bitmaps. */
    1999 #define VMX_PROC_CTLS_USE_IO_BITMAPS                            RT_BIT(25)
    2000 /** Monitor trap flag. */
    2001 #define VMX_PROC_CTLS_MONITOR_TRAP_FLAG                         RT_BIT(27)
    2002 /** Use MSR bitmaps. */
    2003 #define VMX_PROC_CTLS_USE_MSR_BITMAPS                           RT_BIT(28)
    2004 /** VM-exit when executing the MONITOR instruction. */
    2005 #define VMX_PROC_CTLS_MONITOR_EXIT                              RT_BIT(29)
    2006 /** VM-exit when executing the PAUSE instruction. */
    2007 #define VMX_PROC_CTLS_PAUSE_EXIT                                RT_BIT(30)
    2008 /** Whether the secondary processor based VM-execution controls are used. */
    2009 #define VMX_PROC_CTLS_USE_SECONDARY_CTLS                        RT_BIT(31)
    2010 /** Default1 class when true-capability MSRs are not supported. */
    2011 #define VMX_PROC_CTLS_DEFAULT1                                  UINT32_C(0x0401e172)
    2012 
    2013 /** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS and Processor-based VM-execution
    2014  *  controls field in the VMCS. */
    2015 #define VMX_BF_PROC_CTLS_UNDEF_0_1_SHIFT                        0
    2016 #define VMX_BF_PROC_CTLS_UNDEF_0_1_MASK                         UINT32_C(0x00000003)
    2017 #define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_SHIFT                  2
    2018 #define VMX_BF_PROC_CTLS_INT_WINDOW_EXIT_MASK                   UINT32_C(0x00000004)
    2019 #define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_SHIFT               3
    2020 #define VMX_BF_PROC_CTLS_USE_TSC_OFFSETTING_MASK                UINT32_C(0x00000008)
    2021 #define VMX_BF_PROC_CTLS_UNDEF_4_6_SHIFT                        4
    2022 #define VMX_BF_PROC_CTLS_UNDEF_4_6_MASK                         UINT32_C(0x00000070)
    2023 #define VMX_BF_PROC_CTLS_HLT_EXIT_SHIFT                         7
    2024 #define VMX_BF_PROC_CTLS_HLT_EXIT_MASK                          UINT32_C(0x00000080)
    2025 #define VMX_BF_PROC_CTLS_UNDEF_8_SHIFT                          8
    2026 #define VMX_BF_PROC_CTLS_UNDEF_8_MASK                           UINT32_C(0x00000100)
    2027 #define VMX_BF_PROC_CTLS_INVLPG_EXIT_SHIFT                      9
    2028 #define VMX_BF_PROC_CTLS_INVLPG_EXIT_MASK                       UINT32_C(0x00000200)
    2029 #define VMX_BF_PROC_CTLS_MWAIT_EXIT_SHIFT                       10
    2030 #define VMX_BF_PROC_CTLS_MWAIT_EXIT_MASK                        UINT32_C(0x00000400)
    2031 #define VMX_BF_PROC_CTLS_RDPMC_EXIT_SHIFT                       11
    2032 #define VMX_BF_PROC_CTLS_RDPMC_EXIT_MASK                        UINT32_C(0x00000800)
    2033 #define VMX_BF_PROC_CTLS_RDTSC_EXIT_SHIFT                       12
    2034 #define VMX_BF_PROC_CTLS_RDTSC_EXIT_MASK                        UINT32_C(0x00001000)
    2035 #define VMX_BF_PROC_CTLS_UNDEF_13_14_SHIFT                      13
    2036 #define VMX_BF_PROC_CTLS_UNDEF_13_14_MASK                       UINT32_C(0x00006000)
    2037 #define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_SHIFT                    15
    2038 #define VMX_BF_PROC_CTLS_CR3_LOAD_EXIT_MASK                     UINT32_C(0x00008000)
    2039 #define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_SHIFT                   16
    2040 #define VMX_BF_PROC_CTLS_CR3_STORE_EXIT_MASK                    UINT32_C(0x00010000)
    2041 #define VMX_BF_PROC_CTLS_UNDEF_17_18_SHIFT                      17
    2042 #define VMX_BF_PROC_CTLS_UNDEF_17_18_MASK                       UINT32_C(0x00060000)
    2043 #define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_SHIFT                    19
    2044 #define VMX_BF_PROC_CTLS_CR8_LOAD_EXIT_MASK                     UINT32_C(0x00080000)
    2045 #define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_SHIFT                   20
    2046 #define VMX_BF_PROC_CTLS_CR8_STORE_EXIT_MASK                    UINT32_C(0x00100000)
    2047 #define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_SHIFT                   21
    2048 #define VMX_BF_PROC_CTLS_USE_TPR_SHADOW_MASK                    UINT32_C(0x00200000)
    2049 #define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_SHIFT                  22
    2050 #define VMX_BF_PROC_CTLS_NMI_WINDOW_EXIT_MASK                   UINT32_C(0x00400000)
    2051 #define VMX_BF_PROC_CTLS_MOV_DR_EXIT_SHIFT                      23
    2052 #define VMX_BF_PROC_CTLS_MOV_DR_EXIT_MASK                       UINT32_C(0x00800000)
    2053 #define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_SHIFT                   24
    2054 #define VMX_BF_PROC_CTLS_UNCOND_IO_EXIT_MASK                    UINT32_C(0x01000000)
    2055 #define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_SHIFT                   25
    2056 #define VMX_BF_PROC_CTLS_USE_IO_BITMAPS_MASK                    UINT32_C(0x02000000)
    2057 #define VMX_BF_PROC_CTLS_UNDEF_26_SHIFT                         26
    2058 #define VMX_BF_PROC_CTLS_UNDEF_26_MASK                          UINT32_C(0x4000000)
    2059 #define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_SHIFT                27
    2060 #define VMX_BF_PROC_CTLS_MONITOR_TRAP_FLAG_MASK                 UINT32_C(0x08000000)
    2061 #define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_SHIFT                  28
    2062 #define VMX_BF_PROC_CTLS_USE_MSR_BITMAPS_MASK                   UINT32_C(0x10000000)
    2063 #define VMX_BF_PROC_CTLS_MONITOR_EXIT_SHIFT                     29
    2064 #define VMX_BF_PROC_CTLS_MONITOR_EXIT_MASK                      UINT32_C(0x20000000)
    2065 #define VMX_BF_PROC_CTLS_PAUSE_EXIT_SHIFT                       30
    2066 #define VMX_BF_PROC_CTLS_PAUSE_EXIT_MASK                        UINT32_C(0x40000000)
    2067 #define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_SHIFT               31
    2068 #define VMX_BF_PROC_CTLS_USE_SECONDARY_CTLS_MASK                UINT32_C(0x80000000)
    2069 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS_, UINT32_C(0), UINT32_MAX,
    2070                             (UNDEF_0_1, INT_WINDOW_EXIT, USE_TSC_OFFSETTING, UNDEF_4_6, HLT_EXIT, UNDEF_8, INVLPG_EXIT,
    2071                              MWAIT_EXIT, RDPMC_EXIT, RDTSC_EXIT, UNDEF_13_14, CR3_LOAD_EXIT, CR3_STORE_EXIT, UNDEF_17_18,
    2072                              CR8_LOAD_EXIT, CR8_STORE_EXIT, USE_TPR_SHADOW, NMI_WINDOW_EXIT, MOV_DR_EXIT, UNCOND_IO_EXIT,
    2073                              USE_IO_BITMAPS, UNDEF_26, MONITOR_TRAP_FLAG, USE_MSR_BITMAPS, MONITOR_EXIT, PAUSE_EXIT,
    2074                              USE_SECONDARY_CTLS));
    2075 /** @} */
    2076 
    2077 
    2078 /** @name Secondary Processor-based VM-execution controls.
    2079  * @{
    2080  */
    2081 /** Virtualize APIC accesses. */
    2082 #define VMX_PROC_CTLS2_VIRT_APIC_ACCESS                         RT_BIT(0)
    2083 /** EPT supported/enabled. */
    2084 #define VMX_PROC_CTLS2_EPT                                      RT_BIT(1)
    2085 /** Descriptor table instructions cause VM-exits. */
    2086 #define VMX_PROC_CTLS2_DESC_TABLE_EXIT                          RT_BIT(2)
    2087 /** RDTSCP supported/enabled. */
    2088 #define VMX_PROC_CTLS2_RDTSCP                                   RT_BIT(3)
    2089 /** Virtualize x2APIC mode. */
    2090 #define VMX_PROC_CTLS2_VIRT_X2APIC_MODE                         RT_BIT(4)
    2091 /** VPID supported/enabled. */
    2092 #define VMX_PROC_CTLS2_VPID                                     RT_BIT(5)
    2093 /** VM-exit when executing the WBINVD instruction. */
    2094 #define VMX_PROC_CTLS2_WBINVD_EXIT                              RT_BIT(6)
    2095 /** Unrestricted guest execution. */
    2096 #define VMX_PROC_CTLS2_UNRESTRICTED_GUEST                       RT_BIT(7)
    2097 /** APIC register virtualization. */
    2098 #define VMX_PROC_CTLS2_APIC_REG_VIRT                            RT_BIT(8)
    2099 /** Virtual-interrupt delivery. */
    2100 #define VMX_PROC_CTLS2_VIRT_INT_DELIVERY                        RT_BIT(9)
    2101 /** A specified number of pause loops cause a VM-exit. */
    2102 #define VMX_PROC_CTLS2_PAUSE_LOOP_EXIT                          RT_BIT(10)
    2103 /** VM-exit when executing RDRAND instructions. */
    2104 #define VMX_PROC_CTLS2_RDRAND_EXIT                              RT_BIT(11)
    2105 /** Enables INVPCID instructions. */
    2106 #define VMX_PROC_CTLS2_INVPCID                                  RT_BIT(12)
    2107 /** Enables VMFUNC instructions. */
    2108 #define VMX_PROC_CTLS2_VMFUNC                                   RT_BIT(13)
    2109 /** Enables VMCS shadowing. */
    2110 #define VMX_PROC_CTLS2_VMCS_SHADOWING                           RT_BIT(14)
    2111 /** Enables ENCLS VM-exits. */
    2112 #define VMX_PROC_CTLS2_ENCLS_EXIT                               RT_BIT(15)
    2113 /** VM-exit when executing RDSEED. */
    2114 #define VMX_PROC_CTLS2_RDSEED_EXIT                              RT_BIT(16)
    2115 /** Enables page-modification logging. */
    2116 #define VMX_PROC_CTLS2_PML                                      RT_BIT(17)
    2117 /** Controls whether EPT-violations may cause \#VE instead of exits. */
    2118 #define VMX_PROC_CTLS2_EPT_VE                                   RT_BIT(18)
    2119 /** Conceal VMX non-root operation from Intel processor trace (PT). */
    2120 #define VMX_PROC_CTLS2_CONCEAL_FROM_PT                          RT_BIT(19)
    2121 /** Enables XSAVES/XRSTORS instructions. */
    2122 #define VMX_PROC_CTLS2_XSAVES_XRSTORS                           RT_BIT(20)
    2123 /** Use TSC scaling. */
    2124 #define VMX_PROC_CTLS2_TSC_SCALING                              RT_BIT(25)
    2125 
    2126 /** Bit fields for MSR_IA32_VMX_PROCBASED_CTLS2 and Secondary processor-based
    2127  *  VM-execution controls field in the VMCS. */
    2128 #define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_SHIFT                0
    2129 #define VMX_BF_PROC_CTLS2_VIRT_APIC_ACCESS_MASK                 UINT32_C(0x00000001)
    2130 #define VMX_BF_PROC_CTLS2_EPT_SHIFT                             1
    2131 #define VMX_BF_PROC_CTLS2_EPT_MASK                              UINT32_C(0x00000002)
    2132 #define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_SHIFT                 2
    2133 #define VMX_BF_PROC_CTLS2_DESC_TABLE_EXIT_MASK                  UINT32_C(0x00000004)
    2134 #define VMX_BF_PROC_CTLS2_RDTSCP_SHIFT                          3
    2135 #define VMX_BF_PROC_CTLS2_RDTSCP_MASK                           UINT32_C(0x00000008)
    2136 #define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_SHIFT                4
    2137 #define VMX_BF_PROC_CTLS2_VIRT_X2APIC_MODE_MASK                 UINT32_C(0x00000010)
    2138 #define VMX_BF_PROC_CTLS2_VPID_SHIFT                            5
    2139 #define VMX_BF_PROC_CTLS2_VPID_MASK                             UINT32_C(0x00000020)
    2140 #define VMX_BF_PROC_CTLS2_WBINVD_EXIT_SHIFT                     6
    2141 #define VMX_BF_PROC_CTLS2_WBINVD_EXIT_MASK                      UINT32_C(0x00000040)
    2142 #define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_SHIFT              7
    2143 #define VMX_BF_PROC_CTLS2_UNRESTRICTED_GUEST_MASK               UINT32_C(0x00000080)
    2144 #define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_SHIFT                   8
    2145 #define VMX_BF_PROC_CTLS2_APIC_REG_VIRT_MASK                    UINT32_C(0x00000100)
    2146 #define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_SHIFT               9
    2147 #define VMX_BF_PROC_CTLS2_VIRT_INT_DELIVERY_MASK                UINT32_C(0x00000200)
    2148 #define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_SHIFT                 10
    2149 #define VMX_BF_PROC_CTLS2_PAUSE_LOOP_EXIT_MASK                  UINT32_C(0x00000400)
    2150 #define VMX_BF_PROC_CTLS2_RDRAND_EXIT_SHIFT                     11
    2151 #define VMX_BF_PROC_CTLS2_RDRAND_EXIT_MASK                      UINT32_C(0x00000800)
    2152 #define VMX_BF_PROC_CTLS2_INVPCID_SHIFT                         12
    2153 #define VMX_BF_PROC_CTLS2_INVPCID_MASK                          UINT32_C(0x00001000)
    2154 #define VMX_BF_PROC_CTLS2_VMFUNC_SHIFT                          13
    2155 #define VMX_BF_PROC_CTLS2_VMFUNC_MASK                           UINT32_C(0x00002000)
    2156 #define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_SHIFT                  14
    2157 #define VMX_BF_PROC_CTLS2_VMCS_SHADOWING_MASK                   UINT32_C(0x00004000)
    2158 #define VMX_BF_PROC_CTLS2_ENCLS_EXIT_SHIFT                      15
    2159 #define VMX_BF_PROC_CTLS2_ENCLS_EXIT_MASK                       UINT32_C(0x00008000)
    2160 #define VMX_BF_PROC_CTLS2_RDSEED_EXIT_SHIFT                     16
    2161 #define VMX_BF_PROC_CTLS2_RDSEED_EXIT_MASK                      UINT32_C(0x00010000)
    2162 #define VMX_BF_PROC_CTLS2_PML_SHIFT                             17
    2163 #define VMX_BF_PROC_CTLS2_PML_MASK                              UINT32_C(0x00020000)
    2164 #define VMX_BF_PROC_CTLS2_EPT_VE_SHIFT                          18
    2165 #define VMX_BF_PROC_CTLS2_EPT_VE_MASK                           UINT32_C(0x00040000)
    2166 #define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_SHIFT                 19
    2167 #define VMX_BF_PROC_CTLS2_CONCEAL_FROM_PT_MASK                  UINT32_C(0x00080000)
    2168 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_SHIFT                  20
    2169 #define VMX_BF_PROC_CTLS2_XSAVES_XRSTORS_MASK                   UINT32_C(0x00100000)
    2170 #define VMX_BF_PROC_CTLS2_UNDEF_21_24_SHIFT                     21
    2171 #define VMX_BF_PROC_CTLS2_UNDEF_21_24_MASK                      UINT32_C(0x01e00000)
    2172 #define VMX_BF_PROC_CTLS2_TSC_SCALING_SHIFT                     25
    2173 #define VMX_BF_PROC_CTLS2_TSC_SCALING_MASK                      UINT32_C(0x02000000)
    2174 #define VMX_BF_PROC_CTLS2_UNDEF_26_31_SHIFT                     26
    2175 #define VMX_BF_PROC_CTLS2_UNDEF_26_31_MASK                      UINT32_C(0xfc000000)
    2176 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_PROC_CTLS2_, UINT32_C(0), UINT32_MAX,
    2177                             (VIRT_APIC_ACCESS, EPT, DESC_TABLE_EXIT, RDTSCP, VIRT_X2APIC_MODE, VPID, WBINVD_EXIT,
    2178                              UNRESTRICTED_GUEST, APIC_REG_VIRT, VIRT_INT_DELIVERY, PAUSE_LOOP_EXIT, RDRAND_EXIT, INVPCID, VMFUNC,
    2179                              VMCS_SHADOWING, ENCLS_EXIT, RDSEED_EXIT, PML, EPT_VE, CONCEAL_FROM_PT, XSAVES_XRSTORS, UNDEF_21_24,
    2180                              TSC_SCALING, UNDEF_26_31));
    2181 /** @} */
    2182 
    2183 
    2184 /** @name VM-entry controls.
    2185  * @{
    2186  */
    2187 /** Load guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
    2188  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    2189 #define VMX_ENTRY_CTLS_LOAD_DEBUG                               RT_BIT(2)
    2190 /** 64-bit guest mode. Must be 0 for CPUs that don't support AMD64. */
    2191 #define VMX_ENTRY_CTLS_IA32E_MODE_GUEST                         RT_BIT(9)
    2192 /** In SMM mode after VM-entry. */
    2193 #define VMX_ENTRY_CTLS_ENTRY_TO_SMM                             RT_BIT(10)
    2194 /** Disable dual treatment of SMI and SMM; must be zero for VM-entry outside of SMM. */
    2195 #define VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON                      RT_BIT(11)
    2196 /** Whether the guest IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-entry. */
    2197 #define VMX_ENTRY_CTLS_LOAD_PERF_MSR                            RT_BIT(13)
    2198 /** Whether the guest IA32_PAT MSR is loaded on VM-entry. */
    2199 #define VMX_ENTRY_CTLS_LOAD_PAT_MSR                             RT_BIT(14)
    2200 /** Whether the guest IA32_EFER MSR is loaded on VM-entry. */
    2201 #define VMX_ENTRY_CTLS_LOAD_EFER_MSR                            RT_BIT(15)
    2202 /** Whether the guest IA32_BNDCFGS MSR is loaded on VM-entry. */
    2203 #define VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR                         RT_BIT(16)
    2204 /** Whether to conceal VMX from Intel PT (Processor Trace). */
    2205 #define VMX_ENTRY_CTLS_CONCEAL_VMX_PT                           RT_BIT(17)
    2206 /** Default1 class when true-capability MSRs are not supported. */
    2207 #define VMX_ENTRY_CTLS_DEFAULT1                                 UINT32_C(0x000011ff)
    2208 
    2209 /** Bit fields for MSR_IA32_VMX_ENTRY_CTLS and VM-entry controls field in the
    2210  *  VMCS. */
    2211 #define VMX_BF_ENTRY_CTLS_UNDEF_0_1_SHIFT                       0
    2212 #define VMX_BF_ENTRY_CTLS_UNDEF_0_1_MASK                        UINT32_C(0x00000003)
    2213 #define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_SHIFT                      2
    2214 #define VMX_BF_ENTRY_CTLS_LOAD_DEBUG_MASK                       UINT32_C(0x00000004)
    2215 #define VMX_BF_ENTRY_CTLS_UNDEF_3_8_SHIFT                       3
    2216 #define VMX_BF_ENTRY_CTLS_UNDEF_3_8_MASK                        UINT32_C(0x000001f8)
    2217 #define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_SHIFT                9
    2218 #define VMX_BF_ENTRY_CTLS_IA32E_MODE_GUEST_MASK                 UINT32_C(0x00000200)
    2219 #define VMX_BF_ENTRY_CTLS_ENTRY_SMM_SHIFT                       10
    2220 #define VMX_BF_ENTRY_CTLS_ENTRY_SMM_MASK                        UINT32_C(0x00000400)
    2221 #define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_SHIFT             11
    2222 #define VMX_BF_ENTRY_CTLS_DEACTIVATE_DUAL_MON_MASK              UINT32_C(0x00000800)
    2223 #define VMX_BF_ENTRY_CTLS_UNDEF_12_SHIFT                        12
    2224 #define VMX_BF_ENTRY_CTLS_UNDEF_12_MASK                         UINT32_C(0x00001000)
    2225 #define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_SHIFT                   13
    2226 #define VMX_BF_ENTRY_CTLS_LOAD_PERF_MSR_MASK                    UINT32_C(0x00002000)
    2227 #define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_SHIFT                    14
    2228 #define VMX_BF_ENTRY_CTLS_LOAD_PAT_MSR_MASK                     UINT32_C(0x00004000)
    2229 #define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_SHIFT                   15
    2230 #define VMX_BF_ENTRY_CTLS_LOAD_EFER_MSR_MASK                    UINT32_C(0x00008000)
    2231 #define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_SHIFT                16
    2232 #define VMX_BF_ENTRY_CTLS_LOAD_BNDCFGS_MSR_MASK                 UINT32_C(0x00010000)
    2233 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_SHIFT                  17
    2234 #define VMX_BF_ENTRY_CTLS_CONCEAL_VMX_PT_MASK                   UINT32_C(0x00020000)
    2235 #define VMX_BF_ENTRY_CTLS_UNDEF_18_31_SHIFT                     18
    2236 #define VMX_BF_ENTRY_CTLS_UNDEF_18_31_MASK                      UINT32_C(0xfffc0000)
    2237 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_CTLS_, UINT32_C(0), UINT32_MAX,
    2238                             (UNDEF_0_1, LOAD_DEBUG, UNDEF_3_8, IA32E_MODE_GUEST, ENTRY_SMM, DEACTIVATE_DUAL_MON, UNDEF_12,
    2239                              LOAD_PERF_MSR, LOAD_PAT_MSR, LOAD_EFER_MSR, LOAD_BNDCFGS_MSR, CONCEAL_VMX_PT, UNDEF_18_31));
    2240 /** @} */
    2241 
    2242 
    2243 /** @name VM-exit controls.
    2244  * @{
    2245  */
    2246 /** Save guest debug controls (dr7 & IA32_DEBUGCTL_MSR) (forced to 1 on the
    2247  *  'first' VT-x capable CPUs; this actually includes the newest Nehalem CPUs) */
    2248 #define VMX_EXIT_CTLS_SAVE_DEBUG                                RT_BIT(2)
    2249 /** Return to long mode after a VM-exit. */
    2250 #define VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE                      RT_BIT(9)
    2251 /** Whether the host IA32_PERF_GLOBAL_CTRL MSR is loaded on VM-exit. */
    2252 #define VMX_EXIT_CTLS_LOAD_PERF_MSR                             RT_BIT(12)
    2253 /** Acknowledge external interrupts with the irq controller if one caused a VM-exit. */
    2254 #define VMX_EXIT_CTLS_ACK_EXT_INT                               RT_BIT(15)
    2255 /** Whether the guest IA32_PAT MSR is saved on VM-exit. */
    2256 #define VMX_EXIT_CTLS_SAVE_PAT_MSR                              RT_BIT(18)
    2257 /** Whether the host IA32_PAT MSR is loaded on VM-exit. */
    2258 #define VMX_EXIT_CTLS_LOAD_PAT_MSR                              RT_BIT(19)
    2259 /** Whether the guest IA32_EFER MSR is saved on VM-exit. */
    2260 #define VMX_EXIT_CTLS_SAVE_EFER_MSR                             RT_BIT(20)
    2261 /** Whether the host IA32_EFER MSR is loaded on VM-exit. */
    2262 #define VMX_EXIT_CTLS_LOAD_EFER_MSR                             RT_BIT(21)
    2263 /** Whether the value of the VMX preemption timer is saved on every VM-exit. */
    2264 #define VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER                        RT_BIT(22)
    2265 /** Whether IA32_BNDCFGS MSR is cleared on VM-exit. */
    2266 #define VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR                         RT_BIT(23)
    2267 /** Default1 class when true-capability MSRs are not supported.  */
    2268 #define VMX_EXIT_CTLS_DEFAULT1                                  UINT32_C(0x00036dff)
    2269 
    2270 /** Bit fields for MSR_IA32_VMX_EXIT_CTLS and VM-exit controls field in the
    2271  *  VMCS. */
    2272 #define VMX_BF_EXIT_CTLS_UNDEF_0_1_SHIFT                        0
    2273 #define VMX_BF_EXIT_CTLS_UNDEF_0_1_MASK                         UINT32_C(0x00000003)
    2274 #define VMX_BF_EXIT_CTLS_SAVE_DEBUG_SHIFT                       2
    2275 #define VMX_BF_EXIT_CTLS_SAVE_DEBUG_MASK                        UINT32_C(0x00000004)
    2276 #define VMX_BF_EXIT_CTLS_UNDEF_3_8_SHIFT                        3
    2277 #define VMX_BF_EXIT_CTLS_UNDEF_3_8_MASK                         UINT32_C(0x000001f8)
    2278 #define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_SHIFT             9
    2279 #define VMX_BF_EXIT_CTLS_HOST_ADDR_SPACE_SIZE_MASK              UINT32_C(0x00000200)
    2280 #define VMX_BF_EXIT_CTLS_UNDEF_10_11_SHIFT                      10
    2281 #define VMX_BF_EXIT_CTLS_UNDEF_10_11_MASK                       UINT32_C(0x00000c00)
    2282 #define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_SHIFT                    12
    2283 #define VMX_BF_EXIT_CTLS_LOAD_PERF_MSR_MASK                     UINT32_C(0x00001000)
    2284 #define VMX_BF_EXIT_CTLS_UNDEF_13_14_SHIFT                      13
    2285 #define VMX_BF_EXIT_CTLS_UNDEF_13_14_MASK                       UINT32_C(0x00006000)
    2286 #define VMX_BF_EXIT_CTLS_ACK_EXT_INT_SHIFT                      15
    2287 #define VMX_BF_EXIT_CTLS_ACK_EXT_INT_MASK                       UINT32_C(0x00008000)
    2288 #define VMX_BF_EXIT_CTLS_UNDEF_16_17_SHIFT                      16
    2289 #define VMX_BF_EXIT_CTLS_UNDEF_16_17_MASK                       UINT32_C(0x00030000)
    2290 #define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_SHIFT                     18
    2291 #define VMX_BF_EXIT_CTLS_SAVE_PAT_MSR_MASK                      UINT32_C(0x00040000)
    2292 #define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_SHIFT                     19
    2293 #define VMX_BF_EXIT_CTLS_LOAD_PAT_MSR_MASK                      UINT32_C(0x00080000)
    2294 #define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_SHIFT                    20
    2295 #define VMX_BF_EXIT_CTLS_SAVE_EFER_MSR_MASK                     UINT32_C(0x00100000)
    2296 #define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_SHIFT                    21
    2297 #define VMX_BF_EXIT_CTLS_LOAD_EFER_MSR_MASK                     UINT32_C(0x00200000)
    2298 #define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_SHIFT               22
    2299 #define VMX_BF_EXIT_CTLS_SAVE_PREEMPT_TIMER_MASK                UINT32_C(0x00400000)
    2300 #define VMX_BF_EXIT_CTLS_UNDEF_23_31_SHIFT                      23
    2301 #define VMX_BF_EXIT_CTLS_UNDEF_23_31_MASK                       UINT32_C(0xff800000)
    2302 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_CTLS_, UINT32_C(0), UINT32_MAX,
    2303                             (UNDEF_0_1, SAVE_DEBUG, UNDEF_3_8, HOST_ADDR_SPACE_SIZE, UNDEF_10_11, LOAD_PERF_MSR, UNDEF_13_14,
    2304                              ACK_EXT_INT, UNDEF_16_17, SAVE_PAT_MSR, LOAD_PAT_MSR, SAVE_EFER_MSR, LOAD_EFER_MSR,
    2305                              SAVE_PREEMPT_TIMER, UNDEF_23_31));
    2306 /** @} */
    2307 
    2308 
    2309 /** @name VM-exit reason.
    2310  * @{
    2311  */
    2312 #define VMX_EXIT_REASON_BASIC(a)                                ((a) & 0xffff)
    2313 #define VMX_EXIT_REASON_HAS_ENTRY_FAILED(a)                     (((a) >> 31) & 1)
    2314 #define VMX_EXIT_REASON_ENTRY_FAILED                            RT_BIT(31)
    2315 
    2316 /** Bit fields for VM-exit reason. */
    2317 /** The exit reason. */
    2318 #define VMX_BF_EXIT_REASON_BASIC_SHIFT                          0
    2319 #define VMX_BF_EXIT_REASON_BASIC_MASK                           UINT32_C(0x0000ffff)
    2320 /** Bits 16:26 are reseved and MBZ. */
    2321 #define VMX_BF_EXIT_REASON_RSVD_16_26_SHIFT                     16
    2322 #define VMX_BF_EXIT_REASON_RSVD_16_26_MASK                      UINT32_C(0x07ff0000)
    2323 /** Whether the VM-exit was incident to enclave mode. */
    2324 #define VMX_BF_EXIT_REASON_ENCLAVE_MODE_SHIFT                   27
    2325 #define VMX_BF_EXIT_REASON_ENCLAVE_MODE_MASK                    UINT32_C(0x08000000)
    2326 /** Pending MTF (Monitor Trap Flag) during VM-exit (only applicable in SMM mode). */
    2327 #define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_SHIFT                28
    2328 #define VMX_BF_EXIT_REASON_SMM_PENDING_MTF_MASK                 UINT32_C(0x10000000)
    2329 /** VM-exit from VMX root operation (only possible with SMM). */
    2330 #define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_SHIFT                  29
    2331 #define VMX_BF_EXIT_REASON_VMX_ROOT_MODE_MASK                   UINT32_C(0x20000000)
    2332 /** Bit 30 is reserved and MBZ. */
    2333 #define VMX_BF_EXIT_REASON_RSVD_30_SHIFT                        30
    2334 #define VMX_BF_EXIT_REASON_RSVD_30_MASK                         UINT32_C(0x40000000)
    2335 /** Whether VM-entry failed (currently only happens during loading guest-state
    2336  *  or MSRs or machine check exceptions). */
    2337 #define VMX_BF_EXIT_REASON_ENTRY_FAILED_SHIFT                   31
    2338 #define VMX_BF_EXIT_REASON_ENTRY_FAILED_MASK                    UINT32_C(0x80000000)
    2339 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_REASON_, UINT32_C(0), UINT32_MAX,
    2340                             (BASIC, RSVD_16_26, ENCLAVE_MODE, SMM_PENDING_MTF, VMX_ROOT_MODE, RSVD_30, ENTRY_FAILED));
    2341 /** @} */
    2342 
    2343 
    2344 /** @name VM-entry interruption information.
    2345  * @{
    2346  */
    2347 #define VMX_ENTRY_INT_INFO_IS_VALID(a)                          (((a) >> 31) & 1)
    2348 #define VMX_ENTRY_INT_INFO_VECTOR(a)                            ((a) & 0xff)
    2349 #define VMX_ENTRY_INT_INFO_TYPE_SHIFT                           8
    2350 #define VMX_ENTRY_INT_INFO_TYPE(a)                              (((a) >> 8) & 7)
    2351 #define VMX_ENTRY_INT_INFO_ERROR_CODE_VALID                     RT_BIT(11)
    2352 #define VMX_ENTRY_INT_INFO_IS_ERROR_CODE_VALID(a)               (((a) >> 11) & 1)
    2353 #define VMX_ENTRY_INT_INFO_NMI_UNBLOCK_IRET                     12
    2354 #define VMX_ENTRY_INT_INFO_IS_NMI_UNBLOCK_IRET(a)               (((a) >> 12) & 1)
    2355 #define VMX_ENTRY_INT_INFO_VALID                                RT_BIT(31)
    2356 #define VMX_ENTRY_INT_INFO_IS_VALID(a)                          (((a) >> 31) & 1)
    2357 /** Construct an VM-entry interruption information field from a VM-exit interruption
    2358  *  info value (same except that bit 12 is reserved). */
    2359 #define VMX_ENTRY_INT_INFO_FROM_EXIT_INT_INFO(a)                ((a) & ~RT_BIT(12))
    2360 /** Construct a VM-entry interruption information field from an IDT-vectoring
    2361  *  information field (same except that bit 12 is reserved). */
    2362 #define VMX_ENTRY_INT_INFO_FROM_EXIT_IDT_INFO(a)                ((a) & ~RT_BIT(12))
    2363 
    2364 /** Bit fields for VM-entry interruption information. */
    2365 /** The VM-entry interruption vector. */
    2366 #define VMX_BF_ENTRY_INT_INFO_VECTOR_SHIFT                      0
    2367 #define VMX_BF_ENTRY_INT_INFO_VECTOR_MASK                       UINT32_C(0x000000ff)
    2368 /** The VM-entry interruption type (see VMX_ENTRY_INT_INFO_TYPE_XXX). */
    2369 #define VMX_BF_ENTRY_INT_INFO_TYPE_SHIFT                        8
    2370 #define VMX_BF_ENTRY_INT_INFO_TYPE_MASK                         UINT32_C(0x00000700)
    2371 /** Whether this event has an error code.   */
    2372 #define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_SHIFT              11
    2373 #define VMX_BF_ENTRY_INT_INFO_ERR_CODE_VALID_MASK               UINT32_C(0x00000800)
    2374 /** Bits 12:30 are reserved and MBZ. */
    2375 #define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_SHIFT                  12
    2376 #define VMX_BF_ENTRY_INT_INFO_RSVD_12_30_MASK                   UINT32_C(0x7ffff000)
    2377 /** Whether this VM-entry interruption info is valid.  */
    2378 #define VMX_BF_ENTRY_INT_INFO_VALID_SHIFT                       31
    2379 #define VMX_BF_ENTRY_INT_INFO_VALID_MASK                        UINT32_C(0x80000000)
    2380 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_ENTRY_INT_INFO_, UINT32_C(0), UINT32_MAX,
    2381                             (VECTOR, TYPE, ERR_CODE_VALID, RSVD_12_30, VALID));
    2382 /** @} */
    2383 
    2384 /** @name VM-entry exception error code.
    2385  * @{ */
    2386 /** Error code valid mask. */
    2387 /** @todo r=ramshankar: Intel spec. 26.2.1.3 "VM-Entry Control Fields" states that
    2388  *        bits 31:15 MBZ. However, Intel spec. 6.13 "Error Code" states "To keep the
    2389  *        stack aligned for doubleword pushes, the upper half of the error code is
    2390  *        reserved" which implies bits 31:16 MBZ (and not 31:15) which is what we
    2391  *        use below. */
    2392 #define VMX_ENTRY_INT_XCPT_ERR_CODE_VALID_MASK                  UINT32_C(0xffff)
    2393 /** @} */
    2394 
    2395 /** @name VM-entry interruption information types.
    2396  * @{
    2397  */
    2398 #define VMX_ENTRY_INT_INFO_TYPE_EXT_INT                         0
    2399 #define VMX_ENTRY_INT_INFO_TYPE_RSVD                            1
    2400 #define VMX_ENTRY_INT_INFO_TYPE_NMI                             2
    2401 #define VMX_ENTRY_INT_INFO_TYPE_HW_XCPT                         3
    2402 #define VMX_ENTRY_INT_INFO_TYPE_SW_INT                          4
    2403 #define VMX_ENTRY_INT_INFO_TYPE_PRIV_SW_XCPT                    5
    2404 #define VMX_ENTRY_INT_INFO_TYPE_SW_XCPT                         6
    2405 #define VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT                     7
    2406 /** @} */
    2407 
    2408 
    2409 /** @name VM-entry interruption information vector types for
    2410  *        VMX_ENTRY_INT_INFO_TYPE_OTHER_EVENT.
    2411  * @{ */
    2412 #define VMX_ENTRY_INT_INFO_VECTOR_MTF                           0
    2413 /** @} */
    2414 
    2415 
    2416 /** @name VM-exit interruption information.
    2417  * @{
    2418  */
    2419 #define VMX_EXIT_INT_INFO_VECTOR(a)                             ((a) & 0xff)
    2420 #define VMX_EXIT_INT_INFO_TYPE_SHIFT                            8
    2421 #define VMX_EXIT_INT_INFO_TYPE(a)                               (((a) >> 8) & 7)
    2422 #define VMX_EXIT_INT_INFO_ERROR_CODE_VALID                      RT_BIT(11)
    2423 #define VMX_EXIT_INT_INFO_IS_ERROR_CODE_VALID(a)                (((a) >> 11) & 1)
    2424 #define VMX_EXIT_INT_INFO_NMI_UNBLOCK_IRET                      12
    2425 #define VMX_EXIT_INT_INFO_IS_NMI_UNBLOCK_IRET(a)                (((a) >> 12) & 1)
    2426 #define VMX_EXIT_INT_INFO_VALID                                 RT_BIT(31)
    2427 #define VMX_EXIT_INT_INFO_IS_VALID(a)                           (((a) >> 31) & 1)
    2428 
    2429 /** Bit fields for VM-exit interruption infomration. */
    2430 /** The VM-exit interruption vector. */
    2431 #define VMX_BF_EXIT_INT_INFO_VECTOR_SHIFT                       0
    2432 #define VMX_BF_EXIT_INT_INFO_VECTOR_MASK                        UINT32_C(0x000000ff)
    2433 /** The VM-exit interruption type (see VMX_EXIT_INT_INFO_TYPE_XXX). */
    2434 #define VMX_BF_EXIT_INT_INFO_TYPE_SHIFT                         8
    2435 #define VMX_BF_EXIT_INT_INFO_TYPE_MASK                          UINT32_C(0x00000700)
    2436 /** Whether this event has an error code. */
    2437 #define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_SHIFT               11
    2438 #define VMX_BF_EXIT_INT_INFO_ERR_CODE_VALID_MASK                UINT32_C(0x00000800)
    2439 /** Whether NMI-unblocking due to IRET is active. */
    2440 #define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_SHIFT             12
    2441 #define VMX_BF_EXIT_INT_INFO_NMI_UNBLOCK_IRET_MASK              UINT32_C(0x00001000)
    2442 /** Bits 13:30 is reserved (MBZ). */
    2443 #define VMX_BF_EXIT_INT_INFO_RSVD_13_30_SHIFT                   13
    2444 #define VMX_BF_EXIT_INT_INFO_RSVD_13_30_MASK                    UINT32_C(0x7fffe000)
    2445 /** Whether this VM-exit interruption info is valid. */
    2446 #define VMX_BF_EXIT_INT_INFO_VALID_SHIFT                        31
    2447 #define VMX_BF_EXIT_INT_INFO_VALID_MASK                         UINT32_C(0x80000000)
    2448 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_INT_INFO_, UINT32_C(0), UINT32_MAX,
    2449                             (VECTOR, TYPE, ERR_CODE_VALID, NMI_UNBLOCK_IRET, RSVD_13_30, VALID));
    2450 /** @} */
    2451 
    2452 
    2453 /** @name VM-exit interruption information types.
    2454  * @{
    2455  */
    2456 #define VMX_EXIT_INT_INFO_TYPE_EXT_INT                          0
    2457 #define VMX_EXIT_INT_INFO_TYPE_NMI                              2
    2458 #define VMX_EXIT_INT_INFO_TYPE_HW_XCPT                          3
    2459 #define VMX_EXIT_INT_INFO_TYPE_SW_INT                           4
    2460 #define VMX_EXIT_INT_INFO_TYPE_PRIV_SW_XCPT                     5
    2461 #define VMX_EXIT_INT_INFO_TYPE_SW_XCPT                          6
    2462 #define VMX_EXIT_INT_INFO_TYPE_UNUSED                           7
    2463 /** @} */
    2464 
    2465 
    2466 /** @name VM-exit instruction identity.
    2467  *
    2468  * These are found in VM-exit instruction information fields for certain
    2469  * instructions.
    2470  * @{ */
    2471 typedef uint32_t VMXINSTRID;
    2472 /** Whether the instruction ID field is valid. */
    2473 #define VMXINSTRID_VALID                                        RT_BIT_32(31)
    2474 /** Whether the instruction's primary operand in the Mod R/M byte (bits 0:3) is a
    2475  *  read or write. */
    2476 #define VMXINSTRID_MODRM_PRIMARY_OP_W                           RT_BIT_32(30)
    2477 /** Gets whether the instruction ID is valid or not.  */
    2478 #define VMXINSTRID_IS_VALID(a)                                  (((a) >> 31) & 1)
    2479 #define VMXINSTRID_IS_MODRM_PRIMARY_OP_W(a)                     (((a) >> 30) & 1)
    2480 /** Gets the instruction ID.  */
    2481 #define VMXINSTRID_GET_ID(a)                                    ((a) & ~(VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W))
    2482 /** No instruction ID info. */
    2483 #define VMXINSTRID_NONE                                         0
    2484 
    2485 /** The OR'd rvalues are from the VT-x spec (valid bit is VBox specific): */
    2486 #define VMXINSTRID_SGDT                                         (0x0 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
    2487 #define VMXINSTRID_SIDT                                         (0x1 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
    2488 #define VMXINSTRID_LGDT                                         (0x2 | VMXINSTRID_VALID)
    2489 #define VMXINSTRID_LIDT                                         (0x3 | VMXINSTRID_VALID)
    2490 
    2491 #define VMXINSTRID_SLDT                                         (0x0 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
    2492 #define VMXINSTRID_STR                                          (0x1 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
    2493 #define VMXINSTRID_LLDT                                         (0x2 | VMXINSTRID_VALID)
    2494 #define VMXINSTRID_LTR                                          (0x3 | VMXINSTRID_VALID)
    2495 
    2496 /** The following IDs are used internally (some for logging, others for conveying
    2497  *  the ModR/M primary operand write bit): */
    2498 #define VMXINSTRID_VMLAUNCH                                     (0x10 | VMXINSTRID_VALID)
    2499 #define VMXINSTRID_VMRESUME                                     (0x11 | VMXINSTRID_VALID)
    2500 #define VMXINSTRID_VMREAD                                       (0x12 | VMXINSTRID_VALID)
    2501 #define VMXINSTRID_VMWRITE                                      (0x13 | VMXINSTRID_VALID | VMXINSTRID_MODRM_PRIMARY_OP_W)
    2502 #define VMXINSTRID_IO_IN                                        (0x14 | VMXINSTRID_VALID)
    2503 #define VMXINSTRID_IO_INS                                       (0x15 | VMXINSTRID_VALID)
    2504 #define VMXINSTRID_IO_OUT                                       (0x16 | VMXINSTRID_VALID)
    2505 #define VMXINSTRID_IO_OUTS                                      (0x17 | VMXINSTRID_VALID)
    2506 #define VMXINSTRID_MOV_TO_DRX                                   (0x18 | VMXINSTRID_VALID)
    2507 #define VMXINSTRID_MOV_FROM_DRX                                 (0x19 | VMXINSTRID_VALID)
    2508 /** @} */
    2509 
    2510 
    2511 /** @name IDT-vectoring information.
    2512  * @{
    2513  */
    2514 #define VMX_IDT_VECTORING_INFO_VECTOR(a)                        ((a) & 0xff)
    2515 #define VMX_IDT_VECTORING_INFO_TYPE(a)                          (((a) >> 8) & 7)
    2516 #define VMX_IDT_VECTORING_INFO_IS_ERROR_CODE_VALID(a)           (((a) >> 11) & 1)
    2517 #define VMX_IDT_VECTORING_INFO_IS_VALID(a)                      (((a) >> 31) & 1)
    2518 
    2519 /** Construct an IDT-vectoring information field from an VM-entry interruption
    2520  *  information field (same except that bit 12 is reserved). */
    2521 #define VMX_EXIT_IDT_INFO_FROM_ENTRY_INT_INFO(a)                ((a) & ~RT_BIT(12))
    2522 
    2523 /** Bit fields for IDT-vectoring information. */
    2524 /** The IDT-vectoring info vector. */
    2525 #define VMX_BF_IDT_VECTORING_INFO_VECTOR_SHIFT                  0
    2526 #define VMX_BF_IDT_VECTORING_INFO_VECTOR_MASK                   UINT32_C(0x000000ff)
    2527 /** The IDT-vectoring info type (see VMX_IDT_VECTORING_INFO_TYPE_XXX). */
    2528 #define VMX_BF_IDT_VECTORING_INFO_TYPE_SHIFT                    8
    2529 #define VMX_BF_IDT_VECTORING_INFO_TYPE_MASK                     UINT32_C(0x00000700)
    2530 /** Whether the event has an error code. */
    2531 #define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_SHIFT          11
    2532 #define VMX_BF_IDT_VECTORING_INFO_ERR_CODE_VALID_MASK           UINT32_C(0x00000800)
    2533 /** Bit 12 is undefined. */
    2534 #define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_SHIFT                12
    2535 #define VMX_BF_IDT_VECTORING_INFO_UNDEF_12_MASK                 UINT32_C(0x00001000)
    2536 /** Bits 13:30 is reserved (MBZ). */
    2537 #define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_SHIFT              13
    2538 #define VMX_BF_IDT_VECTORING_INFO_RSVD_13_30_MASK               UINT32_C(0x7fffe000)
    2539 /** Whether this IDT-vectoring info is valid. */
    2540 #define VMX_BF_IDT_VECTORING_INFO_VALID_SHIFT                   31
    2541 #define VMX_BF_IDT_VECTORING_INFO_VALID_MASK                    UINT32_C(0x80000000)
    2542 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_IDT_VECTORING_INFO_, UINT32_C(0), UINT32_MAX,
    2543                             (VECTOR, TYPE, ERR_CODE_VALID, UNDEF_12, RSVD_13_30, VALID));
    2544 /** @} */
    2545 
    2546 
    2547 /** @name IDT-vectoring information vector types.
    2548  * @{
    2549  */
    2550 #define VMX_IDT_VECTORING_INFO_TYPE_EXT_INT                     0
    2551 #define VMX_IDT_VECTORING_INFO_TYPE_NMI                         2
    2552 #define VMX_IDT_VECTORING_INFO_TYPE_HW_XCPT                     3
    2553 #define VMX_IDT_VECTORING_INFO_TYPE_SW_INT                      4
    2554 #define VMX_IDT_VECTORING_INFO_TYPE_PRIV_SW_XCPT                5
    2555 #define VMX_IDT_VECTORING_INFO_TYPE_SW_XCPT                     6
    2556 #define VMX_IDT_VECTORING_INFO_TYPE_UNUSED                      7
    2557 /** @} */
    2558 
    2559 
    2560 /** @name TPR threshold.
    2561  * @{ */
    2562 /** Mask of the TPR threshold field (bits 31:4 MBZ). */
    2563 #define VMX_TPR_THRESHOLD_MASK                                   UINT32_C(0xf)
    2564 
    2565 /** Bit fields for TPR threshold. */
    2566 #define VMX_BF_TPR_THRESHOLD_TPR_SHIFT                           0
    2567 #define VMX_BF_TPR_THRESHOLD_TPR_MASK                            UINT32_C(0x0000000f)
    2568 #define VMX_BF_TPR_THRESHOLD_RSVD_4_31_SHIFT                     4
    2569 #define VMX_BF_TPR_THRESHOLD_RSVD_4_31_MASK                      UINT32_C(0xfffffff0)
    2570 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_TPR_THRESHOLD_, UINT32_C(0), UINT32_MAX,
    2571                             (TPR, RSVD_4_31));
    2572 /** @} */
    2573 
    2574 
    2575 /** @name Guest-activity states.
    2576  * @{
    2577  */
    2578 /** The logical processor is active. */
    2579 #define VMX_VMCS_GUEST_ACTIVITY_ACTIVE                          0x0
    2580 /** The logical processor is inactive, because it executed a HLT instruction. */
    2581 #define VMX_VMCS_GUEST_ACTIVITY_HLT                             0x1
    2582 /** The logical processor is inactive, because of a triple fault or other serious error. */
    2583 #define VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN                        0x2
    2584 /** The logical processor is inactive, because it's waiting for a startup-IPI */
    2585 #define VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT                       0x3
    2586 /** @} */
    2587 
    2588 
    2589 /** @name Guest-interruptibility states.
    2590  * @{
    2591  */
    2592 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_STI                      RT_BIT(0)
    2593 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_MOVSS                    RT_BIT(1)
    2594 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_SMI                      RT_BIT(2)
    2595 #define VMX_VMCS_GUEST_INT_STATE_BLOCK_NMI                      RT_BIT(3)
    2596 #define VMX_VMCS_GUEST_INT_STATE_ENCLAVE                        RT_BIT(4)
    2597 
    2598 /** Mask of the guest-interruptibility state field (bits 31:5 MBZ). */
    2599 #define VMX_VMCS_GUEST_INT_STATE_MASK                           UINT32_C(0x1f)
    2600 /** @} */
    2601 
    2602 
    2603 /** @name Exit qualification for debug exceptions.
    2604  * @{
    2605  */
    2606 /** Hardware breakpoint 0 was met. */
    2607 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0                       RT_BIT_64(0)
    2608 /** Hardware breakpoint 1 was met. */
    2609 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1                       RT_BIT_64(1)
    2610 /** Hardware breakpoint 2 was met. */
    2611 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2                       RT_BIT_64(2)
    2612 /** Hardware breakpoint 3 was met. */
    2613 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3                       RT_BIT_64(3)
    2614 /** Debug register access detected. */
    2615 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD                        RT_BIT_64(13)
    2616 /** A debug exception would have been triggered by single-step execution mode. */
    2617 #define VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS                        RT_BIT_64(14)
    2618 /** Mask of all valid bits. */
    2619 #define VMX_VMCS_EXIT_QUAL_VALID_MASK                           (  VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP0 \
    2620                                                                  | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP1 \
    2621                                                                  | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP2 \
    2622                                                                  | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BP3 \
    2623                                                                  | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BD  \
    2624                                                                  | VMX_VMCS_EXIT_QUAL_DEBUG_XCPT_BS)
    2625 
    2626 /** Bit fields for Exit qualifications due to debug exceptions. */
    2627 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_SHIFT                   0
    2628 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP0_MASK                    UINT64_C(0x0000000000000001)
    2629 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_SHIFT                   1
    2630 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP1_MASK                    UINT64_C(0x0000000000000002)
    2631 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_SHIFT                   2
    2632 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP2_MASK                    UINT64_C(0x0000000000000004)
    2633 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_SHIFT                   3
    2634 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BP3_MASK                    UINT64_C(0x0000000000000008)
    2635 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_SHIFT             4
    2636 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_4_12_MASK              UINT64_C(0x0000000000001ff0)
    2637 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_SHIFT                    13
    2638 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BD_MASK                     UINT64_C(0x0000000000002000)
    2639 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_SHIFT                    14
    2640 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_BS_MASK                     UINT64_C(0x0000000000004000)
    2641 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_SHIFT            15
    2642 #define VMX_BF_EXIT_QUAL_DEBUG_XCPT_RSVD_15_63_MASK             UINT64_C(0xffffffffffff8000)
    2643 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DEBUG_XCPT_, UINT64_C(0), UINT64_MAX,
    2644                             (BP0, BP1, BP2, BP3, RSVD_4_12, BD, BS, RSVD_15_63));
    2645 /** @} */
    2646 
    2647 /** @name Exit qualification for Mov DRx.
    2648  * @{
    2649  */
    2650 /** 0-2:  Debug register number */
    2651 #define VMX_EXIT_QUAL_DRX_REGISTER(a)                           ((a) & 7)
    2652 /** 3:    Reserved; cleared to 0. */
    2653 #define VMX_EXIT_QUAL_DRX_RES1(a)                               (((a) >> 3) & 1)
    2654 /** 4:    Direction of move (0 = write, 1 = read) */
    2655 #define VMX_EXIT_QUAL_DRX_DIRECTION(a)                          (((a) >> 4) & 1)
    2656 /** 5-7:  Reserved; cleared to 0. */
    2657 #define VMX_EXIT_QUAL_DRX_RES2(a)                               (((a) >> 5) & 7)
    2658 /** 8-11: General purpose register number. */
    2659 #define VMX_EXIT_QUAL_DRX_GENREG(a)                             (((a) >> 8) & 0xf)
    2660 
    2661 /** Bit fields for Exit qualification due to Mov DRx. */
    2662 #define VMX_BF_EXIT_QUAL_DRX_REGISTER_SHIFT                     0
    2663 #define VMX_BF_EXIT_QUAL_DRX_REGISTER_MASK                      UINT64_C(0x0000000000000007)
    2664 #define VMX_BF_EXIT_QUAL_DRX_RSVD_1_SHIFT                       3
    2665 #define VMX_BF_EXIT_QUAL_DRX_RSVD_1_MASK                        UINT64_C(0x0000000000000008)
    2666 #define VMX_BF_EXIT_QUAL_DRX_DIRECTION_SHIFT                    4
    2667 #define VMX_BF_EXIT_QUAL_DRX_DIRECTION_MASK                     UINT64_C(0x0000000000000010)
    2668 #define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_SHIFT                     5
    2669 #define VMX_BF_EXIT_QUAL_DRX_RSVD_5_7_MASK                      UINT64_C(0x00000000000000e0)
    2670 #define VMX_BF_EXIT_QUAL_DRX_GENREG_SHIFT                       8
    2671 #define VMX_BF_EXIT_QUAL_DRX_GENREG_MASK                        UINT64_C(0x0000000000000f00)
    2672 #define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_SHIFT                   12
    2673 #define VMX_BF_EXIT_QUAL_DRX_RSVD_12_63_MASK                    UINT64_C(0xfffffffffffff000)
    2674 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_DRX_, UINT64_C(0), UINT64_MAX,
    2675                             (REGISTER, RSVD_1, DIRECTION, RSVD_5_7, GENREG, RSVD_12_63));
    2676 /** @} */
    2677 
    2678 
    2679 /** @name Exit qualification for debug exceptions types.
    2680  * @{
    2681  */
    2682 #define VMX_EXIT_QUAL_DRX_DIRECTION_WRITE                       0
    2683 #define VMX_EXIT_QUAL_DRX_DIRECTION_READ                        1
    2684 /** @} */
    2685 
    2686 
    2687 /** @name Exit qualification for control-register accesses.
    2688  * @{
    2689  */
    2690 /** 0-3:   Control register number (0 for CLTS & LMSW) */
    2691 #define VMX_EXIT_QUAL_CRX_REGISTER(a)                           ((a) & 0xf)
    2692 /** 4-5:   Access type. */
    2693 #define VMX_EXIT_QUAL_CRX_ACCESS(a)                             (((a) >> 4) & 3)
    2694 /** 6:     LMSW operand type */
    2695 #define VMX_EXIT_QUAL_CRX_LMSW_OP(a)                            (((a) >> 6) & 1)
    2696 /** 7:     Reserved; cleared to 0. */
    2697 #define VMX_EXIT_QUAL_CRX_RES1(a)                               (((a) >> 7) & 1)
    2698 /** 8-11:  General purpose register number (0 for CLTS & LMSW). */
    2699 #define VMX_EXIT_QUAL_CRX_GENREG(a)                             (((a) >> 8) & 0xf)
    2700 /** 12-15: Reserved; cleared to 0. */
    2701 #define VMX_EXIT_QUAL_CRX_RES2(a)                               (((a) >> 12) & 0xf)
    2702 /** 16-31: LMSW source data (else 0). */
    2703 #define VMX_EXIT_QUAL_CRX_LMSW_DATA(a)                          (((a) >> 16) & 0xffff)
    2704 
    2705 /** Bit fields for Exit qualification for control-register accesses. */
    2706 #define VMX_BF_EXIT_QUAL_CRX_REGISTER_SHIFT                     0
    2707 #define VMX_BF_EXIT_QUAL_CRX_REGISTER_MASK                      UINT64_C(0x000000000000000f)
    2708 #define VMX_BF_EXIT_QUAL_CRX_ACCESS_SHIFT                       4
    2709 #define VMX_BF_EXIT_QUAL_CRX_ACCESS_MASK                        UINT64_C(0x0000000000000030)
    2710 #define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_SHIFT                      6
    2711 #define VMX_BF_EXIT_QUAL_CRX_LMSW_OP_MASK                       UINT64_C(0x0000000000000040)
    2712 #define VMX_BF_EXIT_QUAL_CRX_RSVD_7_SHIFT                       7
    2713 #define VMX_BF_EXIT_QUAL_CRX_RSVD_7_MASK                        UINT64_C(0x0000000000000080)
    2714 #define VMX_BF_EXIT_QUAL_CRX_GENREG_SHIFT                       8
    2715 #define VMX_BF_EXIT_QUAL_CRX_GENREG_MASK                        UINT64_C(0x0000000000000f00)
    2716 #define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_SHIFT                   12
    2717 #define VMX_BF_EXIT_QUAL_CRX_RSVD_12_15_MASK                    UINT64_C(0x000000000000f000)
    2718 #define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_SHIFT                    16
    2719 #define VMX_BF_EXIT_QUAL_CRX_LMSW_DATA_MASK                     UINT64_C(0x00000000ffff0000)
    2720 #define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_SHIFT                   32
    2721 #define VMX_BF_EXIT_QUAL_CRX_RSVD_32_63_MASK                    UINT64_C(0xffffffff00000000)
    2722 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_CRX_, UINT64_C(0), UINT64_MAX,
    2723                             (REGISTER, ACCESS, LMSW_OP, RSVD_7, GENREG, RSVD_12_15, LMSW_DATA, RSVD_32_63));
    2724 /** @} */
    2725 
    2726 
    2727 /** @name Exit qualification for control-register access types.
    2728  * @{
    2729  */
    2730 #define VMX_EXIT_QUAL_CRX_ACCESS_WRITE                          0
    2731 #define VMX_EXIT_QUAL_CRX_ACCESS_READ                           1
    2732 #define VMX_EXIT_QUAL_CRX_ACCESS_CLTS                           2
    2733 #define VMX_EXIT_QUAL_CRX_ACCESS_LMSW                           3
    2734 /** @} */
    2735 
    2736 
    2737 /** @name Exit qualification for task switch.
    2738  * @{
    2739  */
    2740 #define VMX_EXIT_QUAL_TASK_SWITCH_SELECTOR(a)                   ((a) & 0xffff)
    2741 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE(a)                       (((a) >> 30) & 0x3)
    2742 /** Task switch caused by a call instruction. */
    2743 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_CALL                     0
    2744 /** Task switch caused by an iret instruction. */
    2745 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IRET                     1
    2746 /** Task switch caused by a jmp instruction. */
    2747 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_JMP                      2
    2748 /** Task switch caused by an interrupt gate. */
    2749 #define VMX_EXIT_QUAL_TASK_SWITCH_TYPE_IDT                      3
    2750 
    2751 /** Bit fields for Exit qualification for task switches. */
    2752 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_SHIFT              0
    2753 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_NEW_TSS_MASK               UINT64_C(0x000000000000ffff)
    2754 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_SHIFT           16
    2755 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_16_29_MASK            UINT64_C(0x000000003fff0000)
    2756 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_SHIFT               30
    2757 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_SOURCE_MASK                UINT64_C(0x00000000c0000000)
    2758 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_SHIFT           32
    2759 #define VMX_BF_EXIT_QUAL_TASK_SWITCH_RSVD_32_63_MASK            UINT64_C(0xffffffff00000000)
    2760 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_TASK_SWITCH_, UINT64_C(0), UINT64_MAX,
    2761                             (NEW_TSS, RSVD_16_29, SOURCE, RSVD_32_63));
    2762 /** @} */
    2763 
    2764 
    2765 /** @name Exit qualification for EPT violations.
    2766  * @{
    2767  */
    2768 /** Set if the violation was caused by a data read. */
    2769 #define VMX_EXIT_QUAL_EPT_DATA_READ                             RT_BIT(0)
    2770 /** Set if the violation was caused by a data write. */
    2771 #define VMX_EXIT_QUAL_EPT_DATA_WRITE                            RT_BIT(1)
    2772 /** Set if the violation was caused by an instruction fetch. */
    2773 #define VMX_EXIT_QUAL_EPT_INSTR_FETCH                           RT_BIT(2)
    2774 /** AND of the present bit of all EPT structures. */
    2775 #define VMX_EXIT_QUAL_EPT_ENTRY_PRESENT                         RT_BIT(3)
    2776 /** AND of the write bit of all EPT structures. */
    2777 #define VMX_EXIT_QUAL_EPT_ENTRY_WRITE                           RT_BIT(4)
    2778 /** AND of the execute bit of all EPT structures. */
    2779 #define VMX_EXIT_QUAL_EPT_ENTRY_EXECUTE                         RT_BIT(5)
    2780 /** Set if the guest linear address field contains the faulting address. */
    2781 #define VMX_EXIT_QUAL_EPT_GUEST_ADDR_VALID                      RT_BIT(7)
    2782 /** If bit 7 is one: (reserved otherwise)
    2783  *  1 - violation due to physical address access.
    2784  *  0 - violation caused by page walk or access/dirty bit updates
    2785  */
    2786 #define VMX_EXIT_QUAL_EPT_TRANSLATED_ACCESS                     RT_BIT(8)
    2787 /** @} */
    2788 
    2789 
    2790 /** @name Exit qualification for I/O instructions.
    2791  * @{
    2792  */
    2793 /** 0-2:   IO operation width. */
    2794 #define VMX_EXIT_QUAL_IO_WIDTH(a)                               ((a) & 7)
    2795 /** 3:     IO operation direction. */
    2796 #define VMX_EXIT_QUAL_IO_DIRECTION(a)                           (((a) >> 3) & 1)
    2797 /** 4:     String IO operation (INS / OUTS). */
    2798 #define VMX_EXIT_QUAL_IO_IS_STRING(a)                           (((a) >> 4) & 1)
    2799 /** 5:     Repeated IO operation. */
    2800 #define VMX_EXIT_QUAL_IO_IS_REP(a)                              (((a) >> 5) & 1)
    2801 /** 6:     Operand encoding. */
    2802 #define VMX_EXIT_QUAL_IO_ENCODING(a)                            (((a) >> 6) & 1)
    2803 /** 16-31: IO Port (0-0xffff). */
    2804 #define VMX_EXIT_QUAL_IO_PORT(a)                                (((a) >> 16) & 0xffff)
    2805 
    2806 /** Bit fields for Exit qualification for I/O instructions. */
    2807 #define VMX_BF_EXIT_QUAL_IO_WIDTH_SHIFT                         0
    2808 #define VMX_BF_EXIT_QUAL_IO_WIDTH_MASK                          UINT64_C(0x0000000000000007)
    2809 #define VMX_BF_EXIT_QUAL_IO_DIRECTION_SHIFT                     3
    2810 #define VMX_BF_EXIT_QUAL_IO_DIRECTION_MASK                      UINT64_C(0x0000000000000008)
    2811 #define VMX_BF_EXIT_QUAL_IO_IS_STRING_SHIFT                     4
    2812 #define VMX_BF_EXIT_QUAL_IO_IS_STRING_MASK                      UINT64_C(0x0000000000000010)
    2813 #define VMX_BF_EXIT_QUAL_IO_IS_REP_SHIFT                        5
    2814 #define VMX_BF_EXIT_QUAL_IO_IS_REP_MASK                         UINT64_C(0x0000000000000020)
    2815 #define VMX_BF_EXIT_QUAL_IO_ENCODING_SHIFT                      6
    2816 #define VMX_BF_EXIT_QUAL_IO_ENCODING_MASK                       UINT64_C(0x0000000000000040)
    2817 #define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_SHIFT                     7
    2818 #define VMX_BF_EXIT_QUAL_IO_RSVD_7_15_MASK                      UINT64_C(0x000000000000ff80)
    2819 #define VMX_BF_EXIT_QUAL_IO_PORT_SHIFT                          16
    2820 #define VMX_BF_EXIT_QUAL_IO_PORT_MASK                           UINT64_C(0x00000000ffff0000)
    2821 #define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_SHIFT                    32
    2822 #define VMX_BF_EXIT_QUAL_IO_RSVD_32_63_MASK                     UINT64_C(0xffffffff00000000)
    2823 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_IO_, UINT64_C(0), UINT64_MAX,
    2824                             (WIDTH, DIRECTION, IS_STRING, IS_REP, ENCODING, RSVD_7_15, PORT, RSVD_32_63));
    2825 /** @} */
    2826 
    2827 
    2828 /** @name Exit qualification for I/O instruction types.
    2829  * @{
    2830  */
    2831 #define VMX_EXIT_QUAL_IO_DIRECTION_OUT                          0
    2832 #define VMX_EXIT_QUAL_IO_DIRECTION_IN                           1
    2833 /** @} */
    2834 
    2835 
    2836 /** @name Exit qualification for I/O instruction encoding.
    2837  * @{
    2838  */
    2839 #define VMX_EXIT_QUAL_IO_ENCODING_DX                            0
    2840 #define VMX_EXIT_QUAL_IO_ENCODING_IMM                           1
    2841 /** @} */
    2842 
    2843 
    2844 /** @name Exit qualification for APIC-access VM-exits from linear and
    2845  *        guest-physical accesses.
    2846  * @{
    2847  */
    2848 /** 0-11: If the APIC-access VM-exit is due to a linear access, the offset of
    2849  *  access within the APIC page. */
    2850 #define VMX_EXIT_QUAL_APIC_ACCESS_OFFSET(a)                     ((a) & 0xfff)
    2851 /** 12-15: Access type. */
    2852 #define VMX_EXIT_QUAL_APIC_ACCESS_TYPE(a)                       (((a) & 0xf000) >> 12)
    2853 /* Rest reserved. */
    2854 
    2855 /** Bit fields for Exit qualification for APIC-access VM-exits. */
    2856 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_SHIFT               0
    2857 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_OFFSET_MASK                UINT64_C(0x0000000000000fff)
    2858 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_SHIFT                 12
    2859 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_TYPE_MASK                  UINT64_C(0x000000000000f000)
    2860 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_SHIFT           16
    2861 #define VMX_BF_EXIT_QUAL_APIC_ACCESS_RSVD_16_63_MASK            UINT64_C(0xffffffffffff0000)
    2862 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_EXIT_QUAL_APIC_ACCESS_, UINT64_C(0), UINT64_MAX,
    2863                             (OFFSET, TYPE, RSVD_16_63));
    2864 /** @} */
    2865 
    2866 
    2867 /** @name Exit qualification for linear address APIC-access types.
    2868  * @{
    2869  */
    2870 /** Linear access for a data read during instruction execution. */
    2871 #define VMX_APIC_ACCESS_TYPE_LINEAR_READ                        0
    2872 /** Linear access for a data write during instruction execution. */
    2873 #define VMX_APIC_ACCESS_TYPE_LINEAR_WRITE                       1
    2874 /** Linear access for an instruction fetch. */
    2875 #define VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH                 2
    2876 /** Linear read/write access during event delivery. */
    2877 #define VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY              3
    2878 /** Physical read/write access during event delivery. */
    2879 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY            10
    2880 /** Physical access for an instruction fetch or during instruction execution. */
    2881 #define VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR                     15
    2882 
    2883 /**
    2884  * APIC-access type.
    2885  */
    2886 typedef enum
    2887 {
    2888     VMXAPICACCESS_LINEAR_READ             = VMX_APIC_ACCESS_TYPE_LINEAR_READ,
    2889     VMXAPICACCESS_LINEAR_WRITE            = VMX_APIC_ACCESS_TYPE_LINEAR_WRITE,
    2890     VMXAPICACCESS_LINEAR_INSTR_FETCH      = VMX_APIC_ACCESS_TYPE_LINEAR_INSTR_FETCH,
    2891     VMXAPICACCESS_LINEAR_EVENT_DELIVERY   = VMX_APIC_ACCESS_TYPE_LINEAR_EVENT_DELIVERY,
    2892     VMXAPICACCESS_PHYSICAL_EVENT_DELIVERY = VMX_APIC_ACCESS_TYPE_PHYSICAL_EVENT_DELIVERY,
    2893     VMXAPICACCESS_PHYSICAL_INSTR          = VMX_APIC_ACCESS_TYPE_PHYSICAL_INSTR
    2894 } VMXAPICACCESS;
    2895 AssertCompileSize(VMXAPICACCESS, 4);
    2896 /** @} */
    2897 
    2898 
    2899 /** @name VMX_BF_XXTR_INSINFO_XXX - VMX_EXIT_XDTR_ACCESS instruction information.
    2900  * Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
    2901  * @{
    2902  */
    2903 /** Address calculation scaling field (powers of two). */
    2904 #define VMX_BF_XDTR_INSINFO_SCALE_SHIFT                         0
    2905 #define VMX_BF_XDTR_INSINFO_SCALE_MASK                          UINT32_C(0x00000003)
    2906 /** Bits 2 thru 6 are undefined. */
    2907 #define VMX_BF_XDTR_INSINFO_UNDEF_2_6_SHIFT                     2
    2908 #define VMX_BF_XDTR_INSINFO_UNDEF_2_6_MASK                      UINT32_C(0x0000007c)
    2909 /** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
    2910  * @remarks anyone's guess why this is a 3 bit field...  */
    2911 #define VMX_BF_XDTR_INSINFO_ADDR_SIZE_SHIFT                     7
    2912 #define VMX_BF_XDTR_INSINFO_ADDR_SIZE_MASK                      UINT32_C(0x00000380)
    2913 /** Bit 10 is defined as zero. */
    2914 #define VMX_BF_XDTR_INSINFO_ZERO_10_SHIFT                       10
    2915 #define VMX_BF_XDTR_INSINFO_ZERO_10_MASK                        UINT32_C(0x00000400)
    2916 /** Operand size, either (1=)32-bit or (0=)16-bit, but get this, it's undefined
    2917  * for exits from 64-bit code as the operand size there is fixed. */
    2918 #define VMX_BF_XDTR_INSINFO_OP_SIZE_SHIFT                       11
    2919 #define VMX_BF_XDTR_INSINFO_OP_SIZE_MASK                        UINT32_C(0x00000800)
    2920 /** Bits 12 thru 14 are undefined. */
    2921 #define VMX_BF_XDTR_INSINFO_UNDEF_12_14_SHIFT                   12
    2922 #define VMX_BF_XDTR_INSINFO_UNDEF_12_14_MASK                    UINT32_C(0x00007000)
    2923 /** Applicable segment register (X86_SREG_XXX values). */
    2924 #define VMX_BF_XDTR_INSINFO_SREG_SHIFT                          15
    2925 #define VMX_BF_XDTR_INSINFO_SREG_MASK                           UINT32_C(0x00038000)
    2926 /** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
    2927 #define VMX_BF_XDTR_INSINFO_INDEX_REG_SHIFT                     18
    2928 #define VMX_BF_XDTR_INSINFO_INDEX_REG_MASK                      UINT32_C(0x003c0000)
    2929 /** Is VMX_BF_XDTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
    2930 #define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_SHIFT                 22
    2931 #define VMX_BF_XDTR_INSINFO_HAS_INDEX_REG_MASK                  UINT32_C(0x00400000)
    2932 /** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
    2933 #define VMX_BF_XDTR_INSINFO_BASE_REG_SHIFT                      23
    2934 #define VMX_BF_XDTR_INSINFO_BASE_REG_MASK                       UINT32_C(0x07800000)
    2935 /** Is VMX_XDTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
    2936 #define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_SHIFT                  27
    2937 #define VMX_BF_XDTR_INSINFO_HAS_BASE_REG_MASK                   UINT32_C(0x08000000)
    2938 /** The instruction identity (VMX_XDTR_INSINFO_II_XXX values). */
    2939 #define VMX_BF_XDTR_INSINFO_INSTR_ID_SHIFT                      28
    2940 #define VMX_BF_XDTR_INSINFO_INSTR_ID_MASK                       UINT32_C(0x30000000)
    2941 #define VMX_XDTR_INSINFO_II_SGDT                                0 /**< Instruction ID: SGDT */
    2942 #define VMX_XDTR_INSINFO_II_SIDT                                1 /**< Instruction ID: SIDT */
    2943 #define VMX_XDTR_INSINFO_II_LGDT                                2 /**< Instruction ID: LGDT */
    2944 #define VMX_XDTR_INSINFO_II_LIDT                                3 /**< Instruction ID: LIDT */
    2945 /** Bits 30 & 31 are undefined. */
    2946 #define VMX_BF_XDTR_INSINFO_UNDEF_30_31_SHIFT                   30
    2947 #define VMX_BF_XDTR_INSINFO_UNDEF_30_31_MASK                    UINT32_C(0xc0000000)
    2948 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_XDTR_INSINFO_, UINT32_C(0), UINT32_MAX,
    2949                             (SCALE, UNDEF_2_6, ADDR_SIZE, ZERO_10, OP_SIZE, UNDEF_12_14, SREG, INDEX_REG, HAS_INDEX_REG,
    2950                              BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
    2951 /** @} */
    2952 
    2953 
    2954 /** @name VMX_BF_YYTR_INSINFO_XXX - VMX_EXIT_TR_ACCESS instruction information.
    2955  * Found in VMX_VMCS32_RO_EXIT_INSTR_INFO.
    2956  * This is similar to VMX_BF_XDTR_INSINFO_XXX.
    2957  * @{
    2958  */
    2959 /** Address calculation scaling field (powers of two). */
    2960 #define VMX_BF_YYTR_INSINFO_SCALE_SHIFT                         0
    2961 #define VMX_BF_YYTR_INSINFO_SCALE_MASK                          UINT32_C(0x00000003)
    2962 /** Bit 2 is undefined. */
    2963 #define VMX_BF_YYTR_INSINFO_UNDEF_2_SHIFT                       2
    2964 #define VMX_BF_YYTR_INSINFO_UNDEF_2_MASK                        UINT32_C(0x00000004)
    2965 /** Register operand 1. Undefined if VMX_YYTR_INSINFO_HAS_REG1 is clear. */
    2966 #define VMX_BF_YYTR_INSINFO_REG1_SHIFT                          3
    2967 #define VMX_BF_YYTR_INSINFO_REG1_MASK                           UINT32_C(0x00000078)
    2968 /** Address size, only 0(=16), 1(=32) and 2(=64) are defined.
    2969  * @remarks anyone's guess why this is a 3 bit field...  */
    2970 #define VMX_BF_YYTR_INSINFO_ADDR_SIZE_SHIFT                     7
    2971 #define VMX_BF_YYTR_INSINFO_ADDR_SIZE_MASK                      UINT32_C(0x00000380)
    2972 /** Is VMX_YYTR_INSINFO_REG1_XXX valid (=1) or not (=0). */
    2973 #define VMX_BF_YYTR_INSINFO_HAS_REG1_SHIFT                      10
    2974 #define VMX_BF_YYTR_INSINFO_HAS_REG1_MASK                       UINT32_C(0x00000400)
    2975 /** Bits 11 thru 14 are undefined. */
    2976 #define VMX_BF_YYTR_INSINFO_UNDEF_11_14_SHIFT                   11
    2977 #define VMX_BF_YYTR_INSINFO_UNDEF_11_14_MASK                    UINT32_C(0x00007800)
    2978 /** Applicable segment register (X86_SREG_XXX values). */
    2979 #define VMX_BF_YYTR_INSINFO_SREG_SHIFT                          15
    2980 #define VMX_BF_YYTR_INSINFO_SREG_MASK                           UINT32_C(0x00038000)
    2981 /** Index register (X86_GREG_XXX values). Undefined if HAS_INDEX_REG is clear. */
    2982 #define VMX_BF_YYTR_INSINFO_INDEX_REG_SHIFT                     18
    2983 #define VMX_BF_YYTR_INSINFO_INDEX_REG_MASK                      UINT32_C(0x003c0000)
    2984 /** Is VMX_YYTR_INSINFO_INDEX_REG_XXX valid (=1) or not (=0). */
    2985 #define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_SHIFT                 22
    2986 #define VMX_BF_YYTR_INSINFO_HAS_INDEX_REG_MASK                  UINT32_C(0x00400000)
    2987 /** Base register (X86_GREG_XXX values). Undefined if HAS_BASE_REG is clear. */
    2988 #define VMX_BF_YYTR_INSINFO_BASE_REG_SHIFT                      23
    2989 #define VMX_BF_YYTR_INSINFO_BASE_REG_MASK                       UINT32_C(0x07800000)
    2990 /** Is VMX_YYTR_INSINFO_BASE_REG_XXX valid (=1) or not (=0). */
    2991 #define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_SHIFT                  27
    2992 #define VMX_BF_YYTR_INSINFO_HAS_BASE_REG_MASK                   UINT32_C(0x08000000)
    2993 /** The instruction identity (VMX_YYTR_INSINFO_II_XXX values) */
    2994 #define VMX_BF_YYTR_INSINFO_INSTR_ID_SHIFT                      28
    2995 #define VMX_BF_YYTR_INSINFO_INSTR_ID_MASK                       UINT32_C(0x30000000)
    2996 #define VMX_YYTR_INSINFO_II_SLDT                                0 /**< Instruction ID: SLDT */
    2997 #define VMX_YYTR_INSINFO_II_STR                                 1 /**< Instruction ID: STR */
    2998 #define VMX_YYTR_INSINFO_II_LLDT                                2 /**< Instruction ID: LLDT */
    2999 #define VMX_YYTR_INSINFO_II_LTR                                 3 /**< Instruction ID: LTR */
    3000 /** Bits 30 & 31 are undefined. */
    3001 #define VMX_BF_YYTR_INSINFO_UNDEF_30_31_SHIFT                   30
    3002 #define VMX_BF_YYTR_INSINFO_UNDEF_30_31_MASK                    UINT32_C(0xc0000000)
    3003 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_YYTR_INSINFO_, UINT32_C(0), UINT32_MAX,
    3004                             (SCALE, UNDEF_2, REG1, ADDR_SIZE, HAS_REG1, UNDEF_11_14, SREG, INDEX_REG, HAS_INDEX_REG,
    3005                              BASE_REG, HAS_BASE_REG, INSTR_ID, UNDEF_30_31));
    3006 /** @} */
    3007 
    3008 
    3009 /** @name Format of Pending-Debug-Exceptions.
    3010  * Bits 4-11, 13, 15 and 17-63 are reserved.
    3011  * Similar to DR6 except bit 12 (breakpoint enabled) and bit 16 (RTM) are both
    3012  * possibly valid here but not in DR6.
    3013  * @{
    3014  */
    3015 /** Hardware breakpoint 0 was met. */
    3016 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0                   RT_BIT_64(0)
    3017 /** Hardware breakpoint 1 was met. */
    3018 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1                   RT_BIT_64(1)
    3019 /** Hardware breakpoint 2 was met. */
    3020 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2                   RT_BIT_64(2)
    3021 /** Hardware breakpoint 3 was met. */
    3022 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3                   RT_BIT_64(3)
    3023 /** At least one data or IO breakpoint was hit. */
    3024 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP                 RT_BIT_64(12)
    3025 /** A debug exception would have been triggered by single-step execution mode. */
    3026 #define VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS                    RT_BIT_64(14)
    3027 /** A debug exception occurred inside an RTM region.   */
    3028 #define VMX_VMCS_GUEST_PENDING_DEBUG_RTM                        RT_BIT_64(16)
    3029 /** Mask of valid bits. */
    3030 #define VMX_VMCS_GUEST_PENDING_DEBUG_VALID_MASK                 (  VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 \
    3031                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1 \
    3032                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP2 \
    3033                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP3 \
    3034                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
    3035                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
    3036                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
    3037 #define VMX_VMCS_GUEST_PENDING_DEBUG_RTM_MASK                   (  VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_EN_BP \
    3038                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BS \
    3039                                                                  | VMX_VMCS_GUEST_PENDING_DEBUG_RTM)
    3040 /** Bit fields for Pending debug exceptions. */
    3041 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_SHIFT                  0
    3042 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP0_MASK                   UINT64_C(0x0000000000000001)
    3043 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_SHIFT                  1
    3044 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP1_MASK                   UINT64_C(0x0000000000000002)
    3045 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_SHIFT                  2
    3046 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP2_MASK                   UINT64_C(0x0000000000000004)
    3047 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_SHIFT                  3
    3048 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BP3_MASK                   UINT64_C(0x0000000000000008)
    3049 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_SHIFT            4
    3050 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_4_11_MASK             UINT64_C(0x0000000000000ff0)
    3051 #define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_SHIFT                12
    3052 #define VMX_BF_VMCS_PENDING_DBG_XCPT_EN_BP_MASK                 UINT64_C(0x0000000000001000)
    3053 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_SHIFT              13
    3054 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_13_MASK               UINT64_C(0x0000000000002000)
    3055 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_SHIFT                   14
    3056 #define VMX_BF_VMCS_PENDING_DBG_XCPT_BS_MASK                    UINT64_C(0x0000000000004000)
    3057 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_SHIFT              15
    3058 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_15_MASK               UINT64_C(0x0000000000008000)
    3059 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_SHIFT                  16
    3060 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RTM_MASK                   UINT64_C(0x0000000000010000)
    3061 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_SHIFT           17
    3062 #define VMX_BF_VMCS_PENDING_DBG_XCPT_RSVD_17_63_MASK            UINT64_C(0xfffffffffffe0000)
    3063 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_PENDING_DBG_XCPT_, UINT64_C(0), UINT64_MAX,
    3064                             (BP0, BP1, BP2, BP3, RSVD_4_11, EN_BP, RSVD_13, BS, RSVD_15, RTM, RSVD_17_63));
    3065 /** @} */
    3066 
    3067 
    3068 /** @name VMCS field encoding.
    3069  * @{ */
    3070 typedef union
    3071 {
    3072     struct
    3073     {
    3074         /** The access type; 0=full, 1=high of 64-bit fields. */
    3075         uint32_t    fAccessType  : 1;
    3076         /** The index. */
    3077         uint32_t    u8Index      : 8;
    3078         /** The type; 0=control, 1=VM-exit info, 2=guest-state, 3=host-state.  */
    3079         uint32_t    u2Type       : 2;
    3080         /** Reserved (MBZ). */
    3081         uint32_t    u1Reserved0  : 1;
    3082         /** The width; 0=16-bit, 1=64-bit, 2=32-bit, 3=natural-width. */
    3083         uint32_t    u2Width      : 2;
    3084         /** Reserved (MBZ). */
    3085         uint32_t    u18Reserved0 : 18;
    3086     } n;
    3087     /* The unsigned integer view. */
    3088     uint32_t    u;
    3089 } VMXVMCSFIELDENC;
    3090 AssertCompileSize(VMXVMCSFIELDENC, 4);
    3091 /** Pointer to a VMCS field encoding. */
    3092 typedef VMXVMCSFIELDENC *PVMXVMCSFIELDENC;
    3093 /** Pointer to a const VMCS field encoding. */
    3094 typedef const VMXVMCSFIELDENC *PCVMXVMCSFIELDENC;
    3095 
    3096 /** VMCS field encoding type: Full. */
    3097 #define VMX_VMCS_ENC_ACCESS_TYPE_FULL                           0
    3098 /** VMCS field encoding type: High. */
    3099 #define VMX_VMCS_ENC_ACCESS_TYPE_HIGH                           1
    3100 
    3101 /** VMCS field encoding type: Control. */
    3102 #define VMX_VMCS_ENC_TYPE_CONTROL                               0
    3103 /** VMCS field encoding type: VM-exit information / read-only fields. */
    3104 #define VMX_VMCS_ENC_TYPE_VMEXIT_INFO                           1
    3105 /** VMCS field encoding type: Guest-state. */
    3106 #define VMX_VMCS_ENC_TYPE_GUEST_STATE                           2
    3107 /** VMCS field encoding type: Host-state. */
    3108 #define VMX_VMCS_ENC_TYPE_HOST_STATE                            3
    3109 
    3110 /** VMCS field encoding width: 16-bit. */
    3111 #define VMX_VMCS_ENC_WIDTH_16BIT                                0
    3112 /** VMCS field encoding width: 64-bit. */
    3113 #define VMX_VMCS_ENC_WIDTH_64BIT                                1
    3114 /** VMCS field encoding width: 32-bit. */
    3115 #define VMX_VMCS_ENC_WIDTH_32BIT                                2
    3116 /** VMCS field encoding width: Natural width. */
    3117 #define VMX_VMCS_ENC_WIDTH_NATURAL                              3
    3118 
    3119 /** VMCS field encoding: Mask of reserved bits (bits 63:15 MBZ), bit 12 is
    3120  *  not included! */
    3121 #define VMX_VMCS_ENC_RSVD_MASK                                  UINT64_C(0xffffffffffff8000)
    3122 
    3123 /** Bits fields for VMCS field encoding. */
    3124 #define VMX_BF_VMCS_ENC_ACCESS_TYPE_SHIFT                       0
    3125 #define VMX_BF_VMCS_ENC_ACCESS_TYPE_MASK                        UINT32_C(0x00000001)
    3126 #define VMX_BF_VMCS_ENC_INDEX_SHIFT                             1
    3127 #define VMX_BF_VMCS_ENC_INDEX_MASK                              UINT32_C(0x000003fe)
    3128 #define VMX_BF_VMCS_ENC_TYPE_SHIFT                              10
    3129 #define VMX_BF_VMCS_ENC_TYPE_MASK                               UINT32_C(0x00000c00)
    3130 #define VMX_BF_VMCS_ENC_RSVD_12_SHIFT                           12
    3131 #define VMX_BF_VMCS_ENC_RSVD_12_MASK                            UINT32_C(0x00001000)
    3132 #define VMX_BF_VMCS_ENC_WIDTH_SHIFT                             13
    3133 #define VMX_BF_VMCS_ENC_WIDTH_MASK                              UINT32_C(0x00006000)
    3134 #define VMX_BF_VMCS_ENC_RSVD_15_31_SHIFT                        15
    3135 #define VMX_BF_VMCS_ENC_RSVD_15_31_MASK                         UINT32_C(0xffff8000)
    3136 RT_BF_ASSERT_COMPILE_CHECKS(VMX_BF_VMCS_ENC_, UINT32_C(0), UINT32_MAX,
    3137                             (ACCESS_TYPE, INDEX, TYPE, RSVD_12, WIDTH, RSVD_15_31));
    3138 /** @} */
    3139 
    3140 
    3141 /** @defgroup grp_hm_vmx_virt    VMX virtualization.
    3142  * @{
    3143  */
    3144 
    3145 /** @name Virtual VMX MSR - Miscellaneous data.
    3146  * @{ */
    3147 /** Number of CR3-target values supported. */
    3148 #define VMX_V_CR3_TARGET_COUNT                                  4
    3149 /** Activity states supported. */
    3150 #define VMX_V_GUEST_ACTIVITY_STATE_MASK                         (VMX_VMCS_GUEST_ACTIVITY_HLT | VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN)
    3151 /** VMX preemption-timer shift (Core i7-2600 taken as reference). */
    3152 #define VMX_V_PREEMPT_TIMER_SHIFT                               5
    3153 /** Maximum number of MSRs in the auto-load/store MSR areas, (n+1) * 512. */
    3154 #define VMX_V_AUTOMSR_COUNT_MAX                                 0
    3155 /** SMM MSEG revision ID. */
    3156 #define VMX_V_MSEG_REV_ID                                       0
    3157 /** @} */
    3158 
    3159 /** @name VMX_V_VMCS_STATE_XXX - Virtual VMCS state.
    3160  * @{ */
    3161 /** VMCS state clear. */
    3162 #define VMX_V_VMCS_STATE_CLEAR          RT_BIT(1)
    3163 /** VMCS state launched. */
    3164 #define VMX_V_VMCS_STATE_LAUNCHED       RT_BIT(2)
    3165 /** @} */
    3166 
    3167 /** CR0 bits set here must always be set when in VMX operation. */
    3168 #define VMX_V_CR0_FIXED0                                        (X86_CR0_PE | X86_CR0_NE | X86_CR0_PG)
    3169 /** VMX_V_CR0_FIXED0 when unrestricted-guest execution is supported for the guest. */
    3170 #define VMX_V_CR0_FIXED0_UX                                     (VMX_V_CR0_FIXED0 & ~(X86_CR0_PE | X86_CR0_PG))
    3171 /** CR4 bits set here must always be set when in VMX operation. */
    3172 #define VMX_V_CR4_FIXED0                                        (X86_CR4_VMXE)
    3173 
    3174 /** Virtual VMCS revision ID. Bump this arbitarily chosen identifier if incompatible
    3175  *  changes to the layout of VMXVVMCS is done.  Bit 31 MBZ.  */
    3176 #define VMX_V_VMCS_REVISION_ID                                  UINT32_C(0x1d000001)
    3177 AssertCompile(!(VMX_V_VMCS_REVISION_ID & RT_BIT(31)));
    3178 
    3179 /** The size of the virtual VMCS region (we use the maximum allowed size to avoid
    3180  *  complications when teleporation may be implemented). */
    3181 #define VMX_V_VMCS_SIZE                                         X86_PAGE_4K_SIZE
    3182 /** The size of the virtual VMCS region (in pages). */
    3183 #define VMX_V_VMCS_PAGES                                        1
    3184 
    3185 /** The size of the Virtual-APIC page (in bytes).  */
    3186 #define VMX_V_VIRT_APIC_SIZE                                    X86_PAGE_4K_SIZE
    3187 /** The size of the Virtual-APIC page (in pages). */
    3188 #define VMX_V_VIRT_APIC_PAGES                                   1
    3189 
    3190 /** Virtual X2APIC MSR range start. */
    3191 #define VMX_V_VIRT_APIC_MSR_START                               0x800
    3192 /** Virtual X2APIC MSR range end. */
    3193 #define VMX_V_VIRT_APIC_MSR_END                                 0x8ff
    3194 
    3195 /** The size of the VMREAD/VMWRITE bitmap (in bytes). */
    3196 #define VMX_V_VMREAD_VMWRITE_BITMAP_SIZE                        X86_PAGE_4K_SIZE
    3197 /** The size of the VMREAD/VMWRITE-bitmap (in pages). */
    3198 #define VMX_V_VMREAD_VMWRITE_BITMAP_PAGES                       1
    3199 
    3200 /** The size of the MSR bitmap (in bytes). */
    3201 #define VMX_V_MSR_BITMAP_SIZE                                   X86_PAGE_4K_SIZE
    3202 /** The size of the MSR bitmap (in pages). */
    3203 #define VMX_V_MSR_BITMAP_PAGES                                  1
    3204 
    3205 /** The size of I/O bitmap A (in bytes). */
    3206 #define VMX_V_IO_BITMAP_A_SIZE                                  X86_PAGE_4K_SIZE
    3207 /** The size of I/O bitmap A (in pages). */
    3208 #define VMX_V_IO_BITMAP_A_PAGES                                 1
    3209 
    3210 /** The size of I/O bitmap B (in bytes). */
    3211 #define VMX_V_IO_BITMAP_B_SIZE                                  X86_PAGE_4K_SIZE
    3212 /** The size of I/O bitmap B (in pages). */
    3213 #define VMX_V_IO_BITMAP_B_PAGES                                 1
    3214 
    3215 /** The size of the auto-load/store MSR area (in bytes). */
    3216 #define VMX_V_AUTOMSR_AREA_SIZE                                 ((512 * (VMX_V_AUTOMSR_COUNT_MAX + 1)) * sizeof(VMXAUTOMSR))
    3217 /* Assert that the size is page aligned or adjust the VMX_V_AUTOMSR_AREA_PAGES macro below. */
    3218 AssertCompile(RT_ALIGN_Z(VMX_V_AUTOMSR_AREA_SIZE, X86_PAGE_4K_SIZE) == VMX_V_AUTOMSR_AREA_SIZE);
    3219 /** The size of the auto-load/store MSR area (in pages). */
    3220 #define VMX_V_AUTOMSR_AREA_PAGES                                ((VMX_V_AUTOMSR_AREA_SIZE) >> X86_PAGE_4K_SHIFT)
    3221 
    3222 /** The highest index value used for supported virtual VMCS field encoding. */
    3223 #define VMX_V_VMCS_MAX_INDEX                                    RT_BF_GET(VMX_VMCS64_CTRL_TSC_MULTIPLIER_HIGH, VMX_BF_VMCS_ENC_INDEX)
    3224 
    3225 /**
    3226  * Virtual VM-Exit information.
    3227  *
    3228  * This is a convenience structure that bundles some VM-exit information related
    3229  * fields together.
    3230  */
    3231 typedef struct
    3232 {
    3233     /** The VM-exit reason. */
    3234     uint32_t                uReason;
    3235     /** The VM-exit instruction length. */
    3236     uint32_t                cbInstr;
    3237     /** The VM-exit instruction information. */
    3238     VMXEXITINSTRINFO        InstrInfo;
    3239     /** The VM-exit instruction ID. */
    3240     VMXINSTRID              uInstrId;
    3241 
    3242     /** The VM-exit qualification field. */
    3243     uint64_t                u64Qual;
    3244     /** The guest-linear address field. */
    3245     uint64_t                u64GuestLinearAddr;
    3246     /** The guest-physical address field. */
    3247     uint64_t                u64GuestPhysAddr;
    3248     /** The effective guest-linear address if @a InstrInfo indicates a memory-based
    3249      *  instruction VM-exit. */
    3250     RTGCPTR                 GCPtrEffAddr;
    3251 } VMXVEXITINFO;
    3252 /** Pointer to the VMXVEXITINFO struct. */
    3253 typedef VMXVEXITINFO *PVMXVEXITINFO;
    3254 /** Pointer to a const VMXVEXITINFO struct. */
    3255 typedef const VMXVEXITINFO *PCVMXVEXITINFO;
    3256 AssertCompileMemberAlignment(VMXVEXITINFO, u64Qual, 8);
    3257 
    3258 /**
    3259  * Virtual VMCS.
    3260  * This is our custom format and merged into the actual VMCS (/shadow) when we
    3261  * execute nested-guest code using hardware-assisted VMX.
    3262  *
    3263  * The first 8 bytes are as per Intel spec. 24.2 "Format of the VMCS Region".
    3264  *
    3265  * The offset and size of the VMCS state field (fVmcsState) is also fixed (not by
    3266  * Intel but for our own requirements) as we use it to offset into guest memory.
    3267  *
    3268  * Although the guest is supposed to access the VMCS only through the execution of
    3269  * VMX instructions (VMREAD, VMWRITE etc.), since the VMCS may reside in guest
    3270  * memory (e.g, active but not current VMCS), for saved-states compatibility, and
    3271  * for teleportation purposes, any newly added fields should be added to the
    3272  * appropriate reserved sections or at the end of the structure.
    3273  *
    3274  * We always treat natural-width fields as 64-bit in our implementation since
    3275  * it's easier, allows for teleporation in the future and does not affect guest
    3276  * software.
    3277  */
    3278 #pragma pack(1)
    3279 typedef struct
    3280 {
    3281     /** 0x0 - VMX VMCS revision identifier.  */
    3282     VMXVMCSREVID    u32VmcsRevId;
    3283     /** 0x4 - VMX-abort indicator. */
    3284     uint32_t        u32VmxAbortId;
    3285     /** 0x8 - VMCS state, see VMX_V_VMCS_STATE_XXX. */
    3286     uint8_t         fVmcsState;
    3287     /** 0x9 - Reserved for future. */
    3288     uint8_t         au8Padding0[3];
    3289     /** 0xc - Reserved for future. */
    3290     uint32_t        au32Reserved0[7];
    3291 
    3292     /** @name 16-bit control fields.
    3293      * @{ */
    3294     /** 0x28 - Virtual processor ID. */
    3295     uint16_t        u16Vpid;
    3296     /** 0x2a - Posted interrupt notify vector. */
    3297     uint16_t        u16PostIntNotifyVector;
    3298     /** 0x2c - EPTP index. */
    3299     uint16_t        u16EptpIndex;
    3300     /** 0x2e - Reserved for future. */
    3301     uint16_t        au16Reserved0[8];
    3302     /** @} */
    3303 
    3304     /** @name 16-bit Guest-state fields.
    3305      * Order of [ES..GS] is important, must match X86_SREG_XXX.
    3306      * @{ */
    3307     /** 0x3e - Guest ES selector. */
    3308     RTSEL           GuestEs;
    3309     /** 0x40 - Guest ES selector. */
    3310     RTSEL           GuestCs;
    3311     /** 0x42 - Guest ES selector. */
    3312     RTSEL           GuestSs;
    3313     /** 0x44 - Guest ES selector. */
    3314     RTSEL           GuestDs;
    3315     /** 0x46 - Guest ES selector. */
    3316     RTSEL           GuestFs;
    3317     /** 0x48 - Guest ES selector. */
    3318     RTSEL           GuestGs;
    3319     /** 0x4a - Guest LDTR selector. */
    3320     RTSEL           GuestLdtr;
    3321     /** 0x4c - Guest TR selector. */
    3322     RTSEL           GuestTr;
    3323     /** 0x4e - Guest interrupt status (virtual-interrupt delivery). */
    3324     uint16_t        u16GuestIntStatus;
    3325     /** 0x50 - PML index. */
    3326     uint16_t        u16PmlIndex;
    3327     /** 0x52 - Reserved for future. */
    3328     uint16_t        au16Reserved1[8];
    3329     /** @} */
    3330 
    3331     /** @name 16-bit Host-state fields.
    3332      * @{ */
    3333     /** 0x62 - Host ES selector. */
    3334     RTSEL           HostEs;
    3335     /** 0x64 - Host CS selector. */
    3336     RTSEL           HostCs;
    3337     /** 0x66 - Host SS selector. */
    3338     RTSEL           HostSs;
    3339     /** 0x68 - Host DS selector. */
    3340     RTSEL           HostDs;
    3341     /** 0x6a - Host FS selector. */
    3342     RTSEL           HostFs;
    3343     /** 0x6c - Host GS selector. */
    3344     RTSEL           HostGs;
    3345     /** 0x6e - Host TR selector. */
    3346     RTSEL           HostTr;
    3347     /** 0x70 - Reserved for future. */
    3348     uint16_t        au16Reserved2[10];
    3349     /** @} */
    3350 
    3351     /** @name 32-bit Control fields.
    3352      * @{ */
    3353     /** 0x84 - Pin-based VM-execution controls. */
    3354     uint32_t        u32PinCtls;
    3355     /** 0x88 - Processor-based VM-execution controls. */
    3356     uint32_t        u32ProcCtls;
    3357     /** 0x8c - Exception bitmap. */
    3358     uint32_t        u32XcptBitmap;
    3359     /** 0x90 - Page-fault exception error mask. */
    3360     uint32_t        u32XcptPFMask;
    3361     /** 0x94 - Page-fault exception error match. */
    3362     uint32_t        u32XcptPFMatch;
    3363     /** 0x98 - CR3-target count. */
    3364     uint32_t        u32Cr3TargetCount;
    3365     /** 0x9c - VM-exit controls. */
    3366     uint32_t        u32ExitCtls;
    3367     /** 0xa0 - VM-exit MSR store count. */
    3368     uint32_t        u32ExitMsrStoreCount;
    3369     /** 0xa4 - VM-exit MSR load count. */
    3370     uint32_t        u32ExitMsrLoadCount;
    3371     /** 0xa8 - VM-entry controls. */
    3372     uint32_t        u32EntryCtls;
    3373     /** 0xac - VM-entry MSR load count. */
    3374     uint32_t        u32EntryMsrLoadCount;
    3375     /** 0xb0 - VM-entry interruption information. */
    3376     uint32_t        u32EntryIntInfo;
    3377     /** 0xb4 - VM-entry exception error code. */
    3378     uint32_t        u32EntryXcptErrCode;
    3379     /** 0xb8 - VM-entry instruction length. */
    3380     uint32_t        u32EntryInstrLen;
    3381     /** 0xbc - TPR-threshold. */
    3382     uint32_t        u32TprThreshold;
    3383     /** 0xc0 - Secondary-processor based VM-execution controls. */
    3384     uint32_t        u32ProcCtls2;
    3385     /** 0xc4 - Pause-loop exiting Gap. */
    3386     uint32_t        u32PleGap;
    3387     /** 0xc8 - Pause-loop exiting Window. */
    3388     uint32_t        u32PleWindow;
    3389     /** 0xcc - Reserved for future. */
    3390     uint32_t        au32Reserved1[8];
    3391     /** @} */
    3392 
    3393     /** @name 32-bit Read-only Data fields.
    3394      * @{ */
    3395     /** 0xec - VM-instruction error.  */
    3396     uint32_t        u32RoVmInstrError;
    3397     /** 0xf0 - VM-exit reason. */
    3398     uint32_t        u32RoExitReason;
    3399     /** 0xf4 - VM-exit interruption information. */
    3400     uint32_t        u32RoExitIntInfo;
    3401     /** 0xf8 - VM-exit interruption error code. */
    3402     uint32_t        u32RoExitIntErrCode;
    3403     /** 0xfc - IDT-vectoring information. */
    3404     uint32_t        u32RoIdtVectoringInfo;
    3405     /** 0x100 - IDT-vectoring error code. */
    3406     uint32_t        u32RoIdtVectoringErrCode;
    3407     /** 0x104 - VM-exit instruction length. */
    3408     uint32_t        u32RoExitInstrLen;
    3409     /** 0x108 - VM-exit instruction information. */
    3410     uint32_t        u32RoExitInstrInfo;
    3411     /** 0x10c - Reserved for future. */
    3412     uint32_t        au32RoReserved2[8];
    3413     /** @} */
    3414 
    3415     /** @name 32-bit Guest-state fields.
    3416      * Order of [ES..GS] limit and attributes are important, must match X86_SREG_XXX.
    3417      * @{ */
    3418     /** 0x12c - Guest ES limit. */
    3419     uint32_t        u32GuestEsLimit;
    3420     /** 0x130 - Guest CS limit. */
    3421     uint32_t        u32GuestCsLimit;
    3422     /** 0x134 - Guest SS limit. */
    3423     uint32_t        u32GuestSsLimit;
    3424     /** 0x138 - Guest DS limit. */
    3425     uint32_t        u32GuestDsLimit;
    3426     /** 0x13c - Guest FS limit. */
    3427     uint32_t        u32GuestFsLimit;
    3428     /** 0x140 - Guest GS limit. */
    3429     uint32_t        u32GuestGsLimit;
    3430     /** 0x144 - Guest LDTR limit. */
    3431     uint32_t        u32GuestLdtrLimit;
    3432     /** 0x148 - Guest TR limit. */
    3433     uint32_t        u32GuestTrLimit;
    3434     /** 0x14c - Guest GDTR limit. */
    3435     uint32_t        u32GuestGdtrLimit;
    3436     /** 0x150 - Guest IDTR limit. */
    3437     uint32_t        u32GuestIdtrLimit;
    3438     /** 0x154 - Guest ES attributes. */
    3439     uint32_t        u32GuestEsAttr;
    3440     /** 0x158 - Guest CS attributes. */
    3441     uint32_t        u32GuestCsAttr;
    3442     /** 0x15c - Guest SS attributes. */
    3443     uint32_t        u32GuestSsAttr;
    3444     /** 0x160 - Guest DS attributes. */
    3445     uint32_t        u32GuestDsAttr;
    3446     /** 0x164 - Guest FS attributes. */
    3447     uint32_t        u32GuestFsAttr;
    3448     /** 0x168 - Guest GS attributes. */
    3449     uint32_t        u32GuestGsAttr;
    3450     /** 0x16c - Guest LDTR attributes. */
    3451     uint32_t        u32GuestLdtrAttr;
    3452     /** 0x170 - Guest TR attributes. */
    3453     uint32_t        u32GuestTrAttr;
    3454     /** 0x174 - Guest interruptibility state. */
    3455     uint32_t        u32GuestIntrState;
    3456     /** 0x178 - Guest activity state. */
    3457     uint32_t        u32GuestActivityState;
    3458     /** 0x17c - Guest SMBASE. */
    3459     uint32_t        u32GuestSmBase;
    3460     /** 0x180 - Guest SYSENTER CS. */
    3461     uint32_t        u32GuestSysenterCS;
    3462     /** 0x184 - Preemption timer value. */
    3463     uint32_t        u32PreemptTimer;
    3464     /** 0x188 - Reserved for future. */
    3465     uint32_t        au32Reserved3[8];
    3466     /** @} */
    3467 
    3468     /** @name 32-bit Host-state fields.
    3469      * @{ */
    3470     /** 0x1a8 - Host SYSENTER CS. */
    3471     uint32_t        u32HostSysenterCs;
    3472     /** 0x1ac - Reserved for future. */
    3473     uint32_t        au32Reserved4[11];
    3474     /** @} */
    3475 
    3476     /** @name 64-bit Control fields.
    3477      * @{ */
    3478     /** 0x1d8 - I/O bitmap A address. */
    3479     RTUINT64U       u64AddrIoBitmapA;
    3480     /** 0x1e0 - I/O bitmap B address. */
    3481     RTUINT64U       u64AddrIoBitmapB;
    3482     /** 0x1e8 - MSR bitmap address. */
    3483     RTUINT64U       u64AddrMsrBitmap;
    3484     /** 0x1f0 - VM-exit MSR-store area address. */
    3485     RTUINT64U       u64AddrExitMsrStore;
    3486     /** 0x1f8 - VM-exit MSR-load area address. */
    3487     RTUINT64U       u64AddrExitMsrLoad;
    3488     /** 0x200 - VM-entry MSR-load area address. */
    3489     RTUINT64U       u64AddrEntryMsrLoad;
    3490     /** 0x208 - Executive-VMCS pointer. */
    3491     RTUINT64U       u64ExecVmcsPtr;
    3492     /** 0x210 - PML address. */
    3493     RTUINT64U       u64AddrPml;
    3494     /** 0x218 - TSC offset. */
    3495     RTUINT64U       u64TscOffset;
    3496     /** 0x220 - Virtual-APIC address. */
    3497     RTUINT64U       u64AddrVirtApic;
    3498     /** 0x228 - APIC-access address. */
    3499     RTUINT64U       u64AddrApicAccess;
    3500     /** 0x230 - Posted-interrupt descriptor address.  */
    3501     RTUINT64U       u64AddrPostedIntDesc;
    3502     /** 0x238 - VM-functions control.  */
    3503     RTUINT64U       u64VmFuncCtls;
    3504     /** 0x240 - EPTP pointer.  */
    3505     RTUINT64U       u64EptpPtr;
    3506     /** 0x248 - EOI-exit bitmap 0.  */
    3507     RTUINT64U       u64EoiExitBitmap0;
    3508     /** 0x250 - EOI-exit bitmap 1.  */
    3509     RTUINT64U       u64EoiExitBitmap1;
    3510     /** 0x258 - EOI-exit bitmap 2.  */
    3511     RTUINT64U       u64EoiExitBitmap2;
    3512     /** 0x260 - EOI-exit bitmap 3.  */
    3513     RTUINT64U       u64EoiExitBitmap3;
    3514     /** 0x268 - EPTP-list address.  */
    3515     RTUINT64U       u64AddrEptpList;
    3516     /** 0x270 - VMREAD-bitmap address.  */
    3517     RTUINT64U       u64AddrVmreadBitmap;
    3518     /** 0x278 - VMWRITE-bitmap address.  */
    3519     RTUINT64U       u64AddrVmwriteBitmap;
    3520     /** 0x280 - Virtualization-exception information address.  */
    3521     RTUINT64U       u64AddrXcptVeInfo;
    3522     /** 0x288 - XSS-exiting bitmap.  */
    3523     RTUINT64U       u64XssBitmap;
    3524     /** 0x290 - ENCLS-exiting bitmap address.  */
    3525     RTUINT64U       u64AddrEnclsBitmap;
    3526     /** 0x298 - TSC multiplier.  */
    3527     RTUINT64U       u64TscMultiplier;
    3528     /** 0x2a0 - Reserved for future. */
    3529     RTUINT64U       au64Reserved0[16];
    3530     /** @} */
    3531 
    3532     /** @name 64-bit Read-only Data fields.
    3533      * @{ */
    3534     /** 0x320 - Guest-physical address. */
    3535     RTUINT64U       u64RoGuestPhysAddr;
    3536     /** 0x328 - Reserved for future. */
    3537     RTUINT64U       au64Reserved1[8];
    3538     /** @} */
    3539 
    3540     /** @name 64-bit Guest-state fields.
    3541      * @{ */
    3542     /** 0x368 - VMCS link pointer. */
    3543     RTUINT64U       u64VmcsLinkPtr;
    3544     /** 0x370 - Guest debug-control MSR. */
    3545     RTUINT64U       u64GuestDebugCtlMsr;
    3546     /** 0x378 - Guest PAT MSR. */
    3547     RTUINT64U       u64GuestPatMsr;
    3548     /** 0x380 - Guest EFER MSR. */
    3549     RTUINT64U       u64GuestEferMsr;
    3550     /** 0x388 - Guest global performance-control MSR. */
    3551     RTUINT64U       u64GuestPerfGlobalCtlMsr;
    3552     /** 0x390 - Guest PDPTE 0. */
    3553     RTUINT64U       u64GuestPdpte0;
    3554     /** 0x398 - Guest PDPTE 0. */
    3555     RTUINT64U       u64GuestPdpte1;
    3556     /** 0x3a0 - Guest PDPTE 1. */
    3557     RTUINT64U       u64GuestPdpte2;
    3558     /** 0x3a8 - Guest PDPTE 2. */
    3559     RTUINT64U       u64GuestPdpte3;
    3560     /** 0x3b0 - Guest Bounds-config MSR (Intel MPX - Memory Protection Extensions). */
    3561     RTUINT64U       u64GuestBndcfgsMsr;
    3562     /** 0x3b8 - Reserved for future. */
    3563     RTUINT64U       au64Reserved2[16];
    3564     /** @} */
    3565 
    3566     /** @name 64-bit Host-state Fields.
    3567      * @{ */
    3568     /** 0x438 - Host PAT MSR. */
    3569     RTUINT64U       u64HostPatMsr;
    3570     /** 0x440 - Host EFER MSR. */
    3571     RTUINT64U       u64HostEferMsr;
    3572     /** 0x448 - Host global performance-control MSR. */
    3573     RTUINT64U       u64HostPerfGlobalCtlMsr;
    3574     /** 0x450 - Reserved for future. */
    3575     RTUINT64U       au64Reserved3[16];
    3576     /** @} */
    3577 
    3578     /** @name Natural-width Control fields.
    3579      * @{ */
    3580     /** 0x4d0 - CR0 guest/host Mask. */
    3581     RTUINT64U       u64Cr0Mask;
    3582     /** 0x4d8 - CR4 guest/host Mask. */
    3583     RTUINT64U       u64Cr4Mask;
    3584     /** 0x4e0 - CR0 read shadow. */
    3585     RTUINT64U       u64Cr0ReadShadow;
    3586     /** 0x4e8 - CR4 read shadow. */
    3587     RTUINT64U       u64Cr4ReadShadow;
    3588     /** 0x4f0 - CR3-target value 0. */
    3589     RTUINT64U       u64Cr3Target0;
    3590     /** 0x4f8 - CR3-target value 1. */
    3591     RTUINT64U       u64Cr3Target1;
    3592     /** 0x500 - CR3-target value 2. */
    3593     RTUINT64U       u64Cr3Target2;
    3594     /** 0x508 - CR3-target value 3. */
    3595     RTUINT64U       u64Cr3Target3;
    3596     /** 0x510 - Reserved for future. */
    3597     RTUINT64U       au64Reserved4[32];
    3598     /** @} */
    3599 
    3600     /** @name Natural-width Read-only Data fields. */
    3601     /** 0x610 - Exit qualification. */
    3602     RTUINT64U       u64RoExitQual;
    3603     /** 0x618 - I/O RCX. */
    3604     RTUINT64U       u64RoIoRcx;
    3605     /** 0x620 - I/O RSI. */
    3606     RTUINT64U       u64RoIoRsi;
    3607     /** 0x628 - I/O RDI. */
    3608     RTUINT64U       u64RoIoRdi;
    3609     /** 0x630 - I/O RIP. */
    3610     RTUINT64U       u64RoIoRip;
    3611     /** 0x638 - Guest-linear address. */
    3612     RTUINT64U       u64RoGuestLinearAddr;
    3613     /** 0x640 - Reserved for future. */
    3614     RTUINT64U       au64Reserved5[16];
    3615     /** @} */
    3616 
    3617     /** @name Natural-width Guest-state Fields.
    3618      * Order of [ES..GS] base is important, must match X86_SREG_XXX.
    3619      * @{ */
    3620     /** 0x6c0 - Guest CR0. */
    3621     RTUINT64U       u64GuestCr0;
    3622     /** 0x6c8 - Guest CR3. */
    3623     RTUINT64U       u64GuestCr3;
    3624     /** 0x6d0 - Guest CR4. */
    3625     RTUINT64U       u64GuestCr4;
    3626     /** 0x6d8 - Guest ES base. */
    3627     RTUINT64U       u64GuestEsBase;
    3628     /** 0x6e0 - Guest CS base. */
    3629     RTUINT64U       u64GuestCsBase;
    3630     /** 0x6e8 - Guest SS base. */
    3631     RTUINT64U       u64GuestSsBase;
    3632     /** 0x6f0 - Guest DS base. */
    3633     RTUINT64U       u64GuestDsBase;
    3634     /** 0x6f8 - Guest FS base. */
    3635     RTUINT64U       u64GuestFsBase;
    3636     /** 0x700 - Guest GS base. */
    3637     RTUINT64U       u64GuestGsBase;
    3638     /** 0x708 - Guest LDTR base. */
    3639     RTUINT64U       u64GuestLdtrBase;
    3640     /** 0x710 - Guest TR base. */
    3641     RTUINT64U       u64GuestTrBase;
    3642     /** 0x718 - Guest GDTR base.  */
    3643     RTUINT64U       u64GuestGdtrBase;
    3644     /** 0x720 - Guest IDTR base.  */
    3645     RTUINT64U       u64GuestIdtrBase;
    3646     /** 0x728 - Guest DR7.  */
    3647     RTUINT64U       u64GuestDr7;
    3648     /** 0x730 - Guest RSP.  */
    3649     RTUINT64U       u64GuestRsp;
    3650     /** 0x738 - Guest RIP.  */
    3651     RTUINT64U       u64GuestRip;
    3652     /** 0x740 - Guest RFLAGS.  */
    3653     RTUINT64U       u64GuestRFlags;
    3654     /** 0x748 - Guest pending debug exception.  */
    3655     RTUINT64U       u64GuestPendingDbgXcpt;
    3656     /** 0x750 - Guest SYSENTER ESP.  */
    3657     RTUINT64U       u64GuestSysenterEsp;
    3658     /** 0x758 - Guest SYSENTER EIP.  */
    3659     RTUINT64U       u64GuestSysenterEip;
    3660     /** 0x760 - Reserved for future. */
    3661     RTUINT64U       au64Reserved6[32];
    3662     /** @} */
    3663 
    3664     /** @name Natural-width Host-state fields.
    3665      * @{ */
    3666     /** 0x860 - Host CR0. */
    3667     RTUINT64U       u64HostCr0;
    3668     /** 0x868 - Host CR3. */
    3669     RTUINT64U       u64HostCr3;
    3670     /** 0x870 - Host CR4. */
    3671     RTUINT64U       u64HostCr4;
    3672     /** 0x878 - Host FS base. */
    3673     RTUINT64U       u64HostFsBase;
    3674     /** 0x880 - Host GS base. */
    3675     RTUINT64U       u64HostGsBase;
    3676     /** 0x888 - Host TR base. */
    3677     RTUINT64U       u64HostTrBase;
    3678     /** 0x890 - Host GDTR base. */
    3679     RTUINT64U       u64HostGdtrBase;
    3680     /** 0x898 - Host IDTR base. */
    3681     RTUINT64U       u64HostIdtrBase;
    3682     /** 0x8a0 - Host SYSENTER ESP base. */
    3683     RTUINT64U       u64HostSysenterEsp;
    3684     /** 0x8a8 - Host SYSENTER ESP base. */
    3685     RTUINT64U       u64HostSysenterEip;
    3686     /** 0x8b0 - Host RSP. */
    3687     RTUINT64U       u64HostRsp;
    3688     /** 0x8b8 - Host RIP. */
    3689     RTUINT64U       u64HostRip;
    3690     /** 0x8c0 - Reserved for future. */
    3691     RTUINT64U       au64Reserved7[32];
    3692     /** @} */
    3693 
    3694     /** 0x9c0 - Padding. */
    3695     uint8_t         abPadding[X86_PAGE_4K_SIZE - 0x9c0];
    3696 } VMXVVMCS;
    3697 #pragma pack()
    3698 /** Pointer to the VMXVVMCS struct. */
    3699 typedef VMXVVMCS *PVMXVVMCS;
    3700 /** Pointer to a const VMXVVMCS struct. */
    3701 typedef const VMXVVMCS *PCVMXVVMCS;
    3702 AssertCompileSize(VMXVVMCS, X86_PAGE_4K_SIZE);
    3703 AssertCompileMemberSize(VMXVVMCS, fVmcsState, sizeof(uint8_t));
    3704 AssertCompileMemberOffset(VMXVVMCS, u32VmxAbortId,      0x004);
    3705 AssertCompileMemberOffset(VMXVVMCS, fVmcsState,         0x008);
    3706 AssertCompileMemberOffset(VMXVVMCS, u16Vpid,            0x028);
    3707 AssertCompileMemberOffset(VMXVVMCS, GuestEs,            0x03e);
    3708 AssertCompileMemberOffset(VMXVVMCS, HostEs,             0x062);
    3709 AssertCompileMemberOffset(VMXVVMCS, u32PinCtls,         0x084);
    3710 AssertCompileMemberOffset(VMXVVMCS, u32RoVmInstrError,  0x0ec);
    3711 AssertCompileMemberOffset(VMXVVMCS, u32GuestEsLimit,    0x12c);
    3712 AssertCompileMemberOffset(VMXVVMCS, u32HostSysenterCs,  0x1a8);
    3713 AssertCompileMemberOffset(VMXVVMCS, u64AddrIoBitmapA,   0x1d8);
    3714 AssertCompileMemberOffset(VMXVVMCS, u64RoGuestPhysAddr, 0x320);
    3715 AssertCompileMemberOffset(VMXVVMCS, u64VmcsLinkPtr,     0x368);
    3716 AssertCompileMemberOffset(VMXVVMCS, u64HostPatMsr,      0x438);
    3717 AssertCompileMemberOffset(VMXVVMCS, u64Cr0Mask,         0x4d0);
    3718 AssertCompileMemberOffset(VMXVVMCS, u64RoExitQual,      0x610);
    3719 AssertCompileMemberOffset(VMXVVMCS, u64GuestCr0,        0x6c0);
    3720 AssertCompileMemberOffset(VMXVVMCS, u64HostCr0,         0x860);
    3721 /** @} */
    3722 
    3723 /**
    3724  * Virtual VMX-instruction and VM-exit diagnostics.
    3725  *
    3726  * These are not the same as VM instruction errors that are enumerated in the Intel
    3727  * spec. These are purely internal, fine-grained definitions used for diagnostic
    3728  * purposes and are not reported to guest software under the VM-instruction error
    3729  * field in its VMCS.
    3730  *
    3731  * @note Members of this enum are used as array indices, so no gaps are allowed.
    3732  *       Please update g_apszVmxInstrDiagDesc when you add new fields to this
    3733  *       enum.
    3734  */
    3735 typedef enum
    3736 {
    3737     /* Internal processing errors. */
    3738     kVmxVDiag_None = 0,
    3739     kVmxVDiag_Ipe_1,
    3740     kVmxVDiag_Ipe_2,
    3741     kVmxVDiag_Ipe_3,
    3742     kVmxVDiag_Ipe_4,
    3743     kVmxVDiag_Ipe_5,
    3744     kVmxVDiag_Ipe_6,
    3745     kVmxVDiag_Ipe_7,
    3746     kVmxVDiag_Ipe_8,
    3747     kVmxVDiag_Ipe_9,
    3748     kVmxVDiag_Ipe_10,
    3749     kVmxVDiag_Ipe_11,
    3750     kVmxVDiag_Ipe_12,
    3751     kVmxVDiag_Ipe_13,
    3752     kVmxVDiag_Ipe_14,
    3753     kVmxVDiag_Ipe_15,
    3754     kVmxVDiag_Ipe_16,
    3755     /* VMXON. */
    3756     kVmxVDiag_Vmxon_A20M,
    3757     kVmxVDiag_Vmxon_Cpl,
    3758     kVmxVDiag_Vmxon_Cr0Fixed0,
    3759     kVmxVDiag_Vmxon_Cr0Fixed1,
    3760     kVmxVDiag_Vmxon_Cr4Fixed0,
    3761     kVmxVDiag_Vmxon_Cr4Fixed1,
    3762     kVmxVDiag_Vmxon_Intercept,
    3763     kVmxVDiag_Vmxon_LongModeCS,
    3764     kVmxVDiag_Vmxon_MsrFeatCtl,
    3765     kVmxVDiag_Vmxon_PtrAbnormal,
    3766     kVmxVDiag_Vmxon_PtrAlign,
    3767     kVmxVDiag_Vmxon_PtrMap,
    3768     kVmxVDiag_Vmxon_PtrReadPhys,
    3769     kVmxVDiag_Vmxon_PtrWidth,
    3770     kVmxVDiag_Vmxon_RealOrV86Mode,
    3771     kVmxVDiag_Vmxon_ShadowVmcs,
    3772     kVmxVDiag_Vmxon_VmxAlreadyRoot,
    3773     kVmxVDiag_Vmxon_Vmxe,
    3774     kVmxVDiag_Vmxon_VmcsRevId,
    3775     kVmxVDiag_Vmxon_VmxRootCpl,
    3776     /* VMXOFF. */
    3777     kVmxVDiag_Vmxoff_Cpl,
    3778     kVmxVDiag_Vmxoff_Intercept,
    3779     kVmxVDiag_Vmxoff_LongModeCS,
    3780     kVmxVDiag_Vmxoff_RealOrV86Mode,
    3781     kVmxVDiag_Vmxoff_Vmxe,
    3782     kVmxVDiag_Vmxoff_VmxRoot,
    3783     /* VMPTRLD. */
    3784     kVmxVDiag_Vmptrld_Cpl,
    3785     kVmxVDiag_Vmptrld_LongModeCS,
    3786     kVmxVDiag_Vmptrld_PtrAbnormal,
    3787     kVmxVDiag_Vmptrld_PtrAlign,
    3788     kVmxVDiag_Vmptrld_PtrMap,
    3789     kVmxVDiag_Vmptrld_PtrReadPhys,
    3790     kVmxVDiag_Vmptrld_PtrVmxon,
    3791     kVmxVDiag_Vmptrld_PtrWidth,
    3792     kVmxVDiag_Vmptrld_RealOrV86Mode,
    3793     kVmxVDiag_Vmptrld_ShadowVmcs,
    3794     kVmxVDiag_Vmptrld_VmcsRevId,
    3795     kVmxVDiag_Vmptrld_VmxRoot,
    3796     /* VMPTRST. */
    3797     kVmxVDiag_Vmptrst_Cpl,
    3798     kVmxVDiag_Vmptrst_LongModeCS,
    3799     kVmxVDiag_Vmptrst_PtrMap,
    3800     kVmxVDiag_Vmptrst_RealOrV86Mode,
    3801     kVmxVDiag_Vmptrst_VmxRoot,
    3802     /* VMCLEAR. */
    3803     kVmxVDiag_Vmclear_Cpl,
    3804     kVmxVDiag_Vmclear_LongModeCS,
    3805     kVmxVDiag_Vmclear_PtrAbnormal,
    3806     kVmxVDiag_Vmclear_PtrAlign,
    3807     kVmxVDiag_Vmclear_PtrMap,
    3808     kVmxVDiag_Vmclear_PtrReadPhys,
    3809     kVmxVDiag_Vmclear_PtrVmxon,
    3810     kVmxVDiag_Vmclear_PtrWidth,
    3811     kVmxVDiag_Vmclear_RealOrV86Mode,
    3812     kVmxVDiag_Vmclear_VmxRoot,
    3813     /* VMWRITE. */
    3814     kVmxVDiag_Vmwrite_Cpl,
    3815     kVmxVDiag_Vmwrite_FieldInvalid,
    3816     kVmxVDiag_Vmwrite_FieldRo,
    3817     kVmxVDiag_Vmwrite_LinkPtrInvalid,
    3818     kVmxVDiag_Vmwrite_LongModeCS,
    3819     kVmxVDiag_Vmwrite_PtrInvalid,
    3820     kVmxVDiag_Vmwrite_PtrMap,
    3821     kVmxVDiag_Vmwrite_RealOrV86Mode,
    3822     kVmxVDiag_Vmwrite_VmxRoot,
    3823     /* VMREAD. */
    3824     kVmxVDiag_Vmread_Cpl,
    3825     kVmxVDiag_Vmread_FieldInvalid,
    3826     kVmxVDiag_Vmread_LinkPtrInvalid,
    3827     kVmxVDiag_Vmread_LongModeCS,
    3828     kVmxVDiag_Vmread_PtrInvalid,
    3829     kVmxVDiag_Vmread_PtrMap,
    3830     kVmxVDiag_Vmread_RealOrV86Mode,
    3831     kVmxVDiag_Vmread_VmxRoot,
    3832     /* VMLAUNCH/VMRESUME. */
    3833     kVmxVDiag_Vmentry_AddrApicAccess,
    3834     kVmxVDiag_Vmentry_AddrApicAccessEqVirtApic,
    3835     kVmxVDiag_Vmentry_AddrApicAccessHandlerReg,
    3836     kVmxVDiag_Vmentry_AddrEntryMsrLoad,
    3837     kVmxVDiag_Vmentry_AddrExitMsrLoad,
    3838     kVmxVDiag_Vmentry_AddrExitMsrStore,
    3839     kVmxVDiag_Vmentry_AddrIoBitmapA,
    3840     kVmxVDiag_Vmentry_AddrIoBitmapB,
    3841     kVmxVDiag_Vmentry_AddrMsrBitmap,
    3842     kVmxVDiag_Vmentry_AddrVirtApicPage,
    3843     kVmxVDiag_Vmentry_AddrVmcsLinkPtr,
    3844     kVmxVDiag_Vmentry_AddrVmreadBitmap,
    3845     kVmxVDiag_Vmentry_AddrVmwriteBitmap,
    3846     kVmxVDiag_Vmentry_ApicRegVirt,
    3847     kVmxVDiag_Vmentry_BlocKMovSS,
    3848     kVmxVDiag_Vmentry_Cpl,
    3849     kVmxVDiag_Vmentry_Cr3TargetCount,
    3850     kVmxVDiag_Vmentry_EntryCtlsAllowed1,
    3851     kVmxVDiag_Vmentry_EntryCtlsDisallowed0,
    3852     kVmxVDiag_Vmentry_EntryInstrLen,
    3853     kVmxVDiag_Vmentry_EntryInstrLenZero,
    3854     kVmxVDiag_Vmentry_EntryIntInfoErrCodePe,
    3855     kVmxVDiag_Vmentry_EntryIntInfoErrCodeVec,
    3856     kVmxVDiag_Vmentry_EntryIntInfoTypeVecRsvd,
    3857     kVmxVDiag_Vmentry_EntryXcptErrCodeRsvd,
    3858     kVmxVDiag_Vmentry_ExitCtlsAllowed1,
    3859     kVmxVDiag_Vmentry_ExitCtlsDisallowed0,
    3860     kVmxVDiag_Vmentry_GuestActStateHlt,
    3861     kVmxVDiag_Vmentry_GuestActStateRsvd,
    3862     kVmxVDiag_Vmentry_GuestActStateShutdown,
    3863     kVmxVDiag_Vmentry_GuestActStateSsDpl,
    3864     kVmxVDiag_Vmentry_GuestActStateStiMovSs,
    3865     kVmxVDiag_Vmentry_GuestCr0Fixed0,
    3866     kVmxVDiag_Vmentry_GuestCr0Fixed1,
    3867     kVmxVDiag_Vmentry_GuestCr0PgPe,
    3868     kVmxVDiag_Vmentry_GuestCr3,
    3869     kVmxVDiag_Vmentry_GuestCr4Fixed0,
    3870     kVmxVDiag_Vmentry_GuestCr4Fixed1,
    3871     kVmxVDiag_Vmentry_GuestDebugCtl,
    3872     kVmxVDiag_Vmentry_GuestDr7,
    3873     kVmxVDiag_Vmentry_GuestEferMsr,
    3874     kVmxVDiag_Vmentry_GuestEferMsrRsvd,
    3875     kVmxVDiag_Vmentry_GuestGdtrBase,
    3876     kVmxVDiag_Vmentry_GuestGdtrLimit,
    3877     kVmxVDiag_Vmentry_GuestIdtrBase,
    3878     kVmxVDiag_Vmentry_GuestIdtrLimit,
    3879     kVmxVDiag_Vmentry_GuestIntStateEnclave,
    3880     kVmxVDiag_Vmentry_GuestIntStateExtInt,
    3881     kVmxVDiag_Vmentry_GuestIntStateNmi,
    3882     kVmxVDiag_Vmentry_GuestIntStateRFlagsSti,
    3883     kVmxVDiag_Vmentry_GuestIntStateRsvd,
    3884     kVmxVDiag_Vmentry_GuestIntStateSmi,
    3885     kVmxVDiag_Vmentry_GuestIntStateStiMovSs,
    3886     kVmxVDiag_Vmentry_GuestIntStateVirtNmi,
    3887     kVmxVDiag_Vmentry_GuestPae,
    3888     kVmxVDiag_Vmentry_GuestPatMsr,
    3889     kVmxVDiag_Vmentry_GuestPcide,
    3890     kVmxVDiag_Vmentry_GuestPdpteCr3ReadPhys,
    3891     kVmxVDiag_Vmentry_GuestPdpte0Rsvd,
    3892     kVmxVDiag_Vmentry_GuestPdpte1Rsvd,
    3893     kVmxVDiag_Vmentry_GuestPdpte2Rsvd,
    3894     kVmxVDiag_Vmentry_GuestPdpte3Rsvd,
    3895     kVmxVDiag_Vmentry_GuestPndDbgXcptBsNoTf,
    3896     kVmxVDiag_Vmentry_GuestPndDbgXcptBsTf,
    3897     kVmxVDiag_Vmentry_GuestPndDbgXcptRsvd,
    3898     kVmxVDiag_Vmentry_GuestPndDbgXcptRtm,
    3899     kVmxVDiag_Vmentry_GuestRip,
    3900     kVmxVDiag_Vmentry_GuestRipRsvd,
    3901     kVmxVDiag_Vmentry_GuestRFlagsIf,
    3902     kVmxVDiag_Vmentry_GuestRFlagsRsvd,
    3903     kVmxVDiag_Vmentry_GuestRFlagsVm,
    3904     kVmxVDiag_Vmentry_GuestSegAttrCsDefBig,
    3905     kVmxVDiag_Vmentry_GuestSegAttrCsDplEqSs,
    3906     kVmxVDiag_Vmentry_GuestSegAttrCsDplLtSs,
    3907     kVmxVDiag_Vmentry_GuestSegAttrCsDplZero,
    3908     kVmxVDiag_Vmentry_GuestSegAttrCsType,
    3909     kVmxVDiag_Vmentry_GuestSegAttrCsTypeRead,
    3910     kVmxVDiag_Vmentry_GuestSegAttrDescTypeCs,
    3911     kVmxVDiag_Vmentry_GuestSegAttrDescTypeDs,
    3912     kVmxVDiag_Vmentry_GuestSegAttrDescTypeEs,
    3913     kVmxVDiag_Vmentry_GuestSegAttrDescTypeFs,
    3914     kVmxVDiag_Vmentry_GuestSegAttrDescTypeGs,
    3915     kVmxVDiag_Vmentry_GuestSegAttrDescTypeSs,
    3916     kVmxVDiag_Vmentry_GuestSegAttrDplRplCs,
    3917     kVmxVDiag_Vmentry_GuestSegAttrDplRplDs,
    3918     kVmxVDiag_Vmentry_GuestSegAttrDplRplEs,
    3919     kVmxVDiag_Vmentry_GuestSegAttrDplRplFs,
    3920     kVmxVDiag_Vmentry_GuestSegAttrDplRplGs,
    3921     kVmxVDiag_Vmentry_GuestSegAttrDplRplSs,
    3922     kVmxVDiag_Vmentry_GuestSegAttrGranCs,
    3923     kVmxVDiag_Vmentry_GuestSegAttrGranDs,
    3924     kVmxVDiag_Vmentry_GuestSegAttrGranEs,
    3925     kVmxVDiag_Vmentry_GuestSegAttrGranFs,
    3926     kVmxVDiag_Vmentry_GuestSegAttrGranGs,
    3927     kVmxVDiag_Vmentry_GuestSegAttrGranSs,
    3928     kVmxVDiag_Vmentry_GuestSegAttrLdtrDescType,
    3929     kVmxVDiag_Vmentry_GuestSegAttrLdtrGran,
    3930     kVmxVDiag_Vmentry_GuestSegAttrLdtrPresent,
    3931     kVmxVDiag_Vmentry_GuestSegAttrLdtrRsvd,
    3932     kVmxVDiag_Vmentry_GuestSegAttrLdtrType,
    3933     kVmxVDiag_Vmentry_GuestSegAttrPresentCs,
    3934     kVmxVDiag_Vmentry_GuestSegAttrPresentDs,
    3935     kVmxVDiag_Vmentry_GuestSegAttrPresentEs,
    3936     kVmxVDiag_Vmentry_GuestSegAttrPresentFs,
    3937     kVmxVDiag_Vmentry_GuestSegAttrPresentGs,
    3938     kVmxVDiag_Vmentry_GuestSegAttrPresentSs,
    3939     kVmxVDiag_Vmentry_GuestSegAttrRsvdCs,
    3940     kVmxVDiag_Vmentry_GuestSegAttrRsvdDs,
    3941     kVmxVDiag_Vmentry_GuestSegAttrRsvdEs,
    3942     kVmxVDiag_Vmentry_GuestSegAttrRsvdFs,
    3943     kVmxVDiag_Vmentry_GuestSegAttrRsvdGs,
    3944     kVmxVDiag_Vmentry_GuestSegAttrRsvdSs,
    3945     kVmxVDiag_Vmentry_GuestSegAttrSsDplEqRpl,
    3946     kVmxVDiag_Vmentry_GuestSegAttrSsDplZero,
    3947     kVmxVDiag_Vmentry_GuestSegAttrSsType,
    3948     kVmxVDiag_Vmentry_GuestSegAttrTrDescType,
    3949     kVmxVDiag_Vmentry_GuestSegAttrTrGran,
    3950     kVmxVDiag_Vmentry_GuestSegAttrTrPresent,
    3951     kVmxVDiag_Vmentry_GuestSegAttrTrRsvd,
    3952     kVmxVDiag_Vmentry_GuestSegAttrTrType,
    3953     kVmxVDiag_Vmentry_GuestSegAttrTrUnusable,
    3954     kVmxVDiag_Vmentry_GuestSegAttrTypeAccCs,
    3955     kVmxVDiag_Vmentry_GuestSegAttrTypeAccDs,
    3956     kVmxVDiag_Vmentry_GuestSegAttrTypeAccEs,
    3957     kVmxVDiag_Vmentry_GuestSegAttrTypeAccFs,
    3958     kVmxVDiag_Vmentry_GuestSegAttrTypeAccGs,
    3959     kVmxVDiag_Vmentry_GuestSegAttrTypeAccSs,
    3960     kVmxVDiag_Vmentry_GuestSegAttrV86Cs,
    3961     kVmxVDiag_Vmentry_GuestSegAttrV86Ds,
    3962     kVmxVDiag_Vmentry_GuestSegAttrV86Es,
    3963     kVmxVDiag_Vmentry_GuestSegAttrV86Fs,
    3964     kVmxVDiag_Vmentry_GuestSegAttrV86Gs,
    3965     kVmxVDiag_Vmentry_GuestSegAttrV86Ss,
    3966     kVmxVDiag_Vmentry_GuestSegBaseCs,
    3967     kVmxVDiag_Vmentry_GuestSegBaseDs,
    3968     kVmxVDiag_Vmentry_GuestSegBaseEs,
    3969     kVmxVDiag_Vmentry_GuestSegBaseFs,
    3970     kVmxVDiag_Vmentry_GuestSegBaseGs,
    3971     kVmxVDiag_Vmentry_GuestSegBaseLdtr,
    3972     kVmxVDiag_Vmentry_GuestSegBaseSs,
    3973     kVmxVDiag_Vmentry_GuestSegBaseTr,
    3974     kVmxVDiag_Vmentry_GuestSegBaseV86Cs,
    3975     kVmxVDiag_Vmentry_GuestSegBaseV86Ds,
    3976     kVmxVDiag_Vmentry_GuestSegBaseV86Es,
    3977     kVmxVDiag_Vmentry_GuestSegBaseV86Fs,
    3978     kVmxVDiag_Vmentry_GuestSegBaseV86Gs,
    3979     kVmxVDiag_Vmentry_GuestSegBaseV86Ss,
    3980     kVmxVDiag_Vmentry_GuestSegLimitV86Cs,
    3981     kVmxVDiag_Vmentry_GuestSegLimitV86Ds,
    3982     kVmxVDiag_Vmentry_GuestSegLimitV86Es,
    3983     kVmxVDiag_Vmentry_GuestSegLimitV86Fs,
    3984     kVmxVDiag_Vmentry_GuestSegLimitV86Gs,
    3985     kVmxVDiag_Vmentry_GuestSegLimitV86Ss,
    3986     kVmxVDiag_Vmentry_GuestSegSelCsSsRpl,
    3987     kVmxVDiag_Vmentry_GuestSegSelLdtr,
    3988     kVmxVDiag_Vmentry_GuestSegSelTr,
    3989     kVmxVDiag_Vmentry_GuestSysenterEspEip,
    3990     kVmxVDiag_Vmentry_VmcsLinkPtrCurVmcs,
    3991     kVmxVDiag_Vmentry_VmcsLinkPtrReadPhys,
    3992     kVmxVDiag_Vmentry_VmcsLinkPtrRevId,
    3993     kVmxVDiag_Vmentry_VmcsLinkPtrShadow,
    3994     kVmxVDiag_Vmentry_HostCr0Fixed0,
    3995     kVmxVDiag_Vmentry_HostCr0Fixed1,
    3996     kVmxVDiag_Vmentry_HostCr3,
    3997     kVmxVDiag_Vmentry_HostCr4Fixed0,
    3998     kVmxVDiag_Vmentry_HostCr4Fixed1,
    3999     kVmxVDiag_Vmentry_HostCr4Pae,
    4000     kVmxVDiag_Vmentry_HostCr4Pcide,
    4001     kVmxVDiag_Vmentry_HostCsTr,
    4002     kVmxVDiag_Vmentry_HostEferMsr,
    4003     kVmxVDiag_Vmentry_HostEferMsrRsvd,
    4004     kVmxVDiag_Vmentry_HostGuestLongMode,
    4005     kVmxVDiag_Vmentry_HostGuestLongModeNoCpu,
    4006     kVmxVDiag_Vmentry_HostLongMode,
    4007     kVmxVDiag_Vmentry_HostPatMsr,
    4008     kVmxVDiag_Vmentry_HostRip,
    4009     kVmxVDiag_Vmentry_HostRipRsvd,
    4010     kVmxVDiag_Vmentry_HostSel,
    4011     kVmxVDiag_Vmentry_HostSegBase,
    4012     kVmxVDiag_Vmentry_HostSs,
    4013     kVmxVDiag_Vmentry_HostSysenterEspEip,
    4014     kVmxVDiag_Vmentry_LongModeCS,
    4015     kVmxVDiag_Vmentry_MsrBitmapPtrReadPhys,
    4016     kVmxVDiag_Vmentry_MsrLoad,
    4017     kVmxVDiag_Vmentry_MsrLoadCount,
    4018     kVmxVDiag_Vmentry_MsrLoadPtrReadPhys,
    4019     kVmxVDiag_Vmentry_MsrLoadRing3,
    4020     kVmxVDiag_Vmentry_MsrLoadRsvd,
    4021     kVmxVDiag_Vmentry_NmiWindowExit,
    4022     kVmxVDiag_Vmentry_PinCtlsAllowed1,
    4023     kVmxVDiag_Vmentry_PinCtlsDisallowed0,
    4024     kVmxVDiag_Vmentry_ProcCtlsAllowed1,
    4025     kVmxVDiag_Vmentry_ProcCtlsDisallowed0,
    4026     kVmxVDiag_Vmentry_ProcCtls2Allowed1,
    4027     kVmxVDiag_Vmentry_ProcCtls2Disallowed0,
    4028     kVmxVDiag_Vmentry_PtrInvalid,
    4029     kVmxVDiag_Vmentry_PtrReadPhys,
    4030     kVmxVDiag_Vmentry_RealOrV86Mode,
    4031     kVmxVDiag_Vmentry_SavePreemptTimer,
    4032     kVmxVDiag_Vmentry_TprThresholdRsvd,
    4033     kVmxVDiag_Vmentry_TprThresholdVTpr,
    4034     kVmxVDiag_Vmentry_VirtApicPagePtrReadPhys,
    4035     kVmxVDiag_Vmentry_VirtIntDelivery,
    4036     kVmxVDiag_Vmentry_VirtNmi,
    4037     kVmxVDiag_Vmentry_VirtX2ApicTprShadow,
    4038     kVmxVDiag_Vmentry_VirtX2ApicVirtApic,
    4039     kVmxVDiag_Vmentry_VmcsClear,
    4040     kVmxVDiag_Vmentry_VmcsLaunch,
    4041     kVmxVDiag_Vmentry_VmreadBitmapPtrReadPhys,
    4042     kVmxVDiag_Vmentry_VmwriteBitmapPtrReadPhys,
    4043     kVmxVDiag_Vmentry_VmxRoot,
    4044     kVmxVDiag_Vmentry_Vpid,
    4045     kVmxVDiag_Vmexit_HostPdpteCr3ReadPhys,
    4046     kVmxVDiag_Vmexit_HostPdpte0Rsvd,
    4047     kVmxVDiag_Vmexit_HostPdpte1Rsvd,
    4048     kVmxVDiag_Vmexit_HostPdpte2Rsvd,
    4049     kVmxVDiag_Vmexit_HostPdpte3Rsvd,
    4050     kVmxVDiag_Vmexit_MsrLoad,
    4051     kVmxVDiag_Vmexit_MsrLoadCount,
    4052     kVmxVDiag_Vmexit_MsrLoadPtrReadPhys,
    4053     kVmxVDiag_Vmexit_MsrLoadRing3,
    4054     kVmxVDiag_Vmexit_MsrLoadRsvd,
    4055     kVmxVDiag_Vmexit_MsrStore,
    4056     kVmxVDiag_Vmexit_MsrStoreCount,
    4057     kVmxVDiag_Vmexit_MsrStorePtrWritePhys,
    4058     kVmxVDiag_Vmexit_MsrStoreRing3,
    4059     kVmxVDiag_Vmexit_MsrStoreRsvd,
    4060     /* Last member for determining array index limit. */
    4061     kVmxVDiag_End
    4062 } VMXVDIAG;
    4063 AssertCompileSize(VMXVDIAG, 4);
    4064 
    4065 
    406653/** @defgroup grp_hm_vmx_inline    VMX Inline Helpers
     54 * @ingroup grp_hm_vmx
    406755 * @{
    406856 */
    … …  
    4229217    return false;
    4230218}
    4231 /** @} */
    4232 
    4233 
    4234 /** @defgroup grp_hm_vmx_c    VMX Assembly Helpers
    4235  *
    4236  * These are functions that strictly only implement VT-x functionality that is in
    4237  * accordance to the VT-X spec. and thus fit to use by IEM/REM/HM.
    4238  *
    4239  * These are not HM all-context API functions, those are to be placed in hm.h.
    4240  * @{
    4241  */
    4242 VMM_INT_DECL(int)   HMVmxGetMsrPermission(void const *pvMsrBitmap, uint32_t idMsr, PVMXMSREXITREAD penmRead,
    4243                                           PVMXMSREXITWRITE penmWrite);
    4244 VMM_INT_DECL(bool)  HMVmxGetIoBitmapPermission(void const *pvIoBitmapA, void const *pvIoBitmapB, uint16_t uPort,
    4245                                                uint8_t cbAccess);
    4246219/** @} */
    4247220
    … …  
    4764737/** @} */
    4765738
    4766 /** @} */
    4767 
    4768 #endif
    4769 
     739#endif
     740

  • trunk/src/VBox/VMM/VMMAll/HMVMXAll.cpp

    r76222 r76397  
    2525#include <VBox/vmm/vm.h>
    2626#include <VBox/vmm/pdmapi.h>
     27#include <VBox/err.h>
    2728
    2829

  • trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

    r69111 r76397  
    2222#include "IEMInternal.h"
    2323#include <VBox/vmm/vm.h>
     24#include <VBox/err.h>
    2425#include <iprt/x86.h>
    2526#include <iprt/uint128.h>

  • trunk/src/VBox/VMM/VMMAll/NEMAll.cpp

    r72917 r76397  
    2424#include "NEMInternal.h"
    2525#include <VBox/vmm/vm.h>
     26#include <VBox/err.h>
    2627
    2728

  • trunk/src/VBox/VMM/VMMR0/HMR0.cpp

    r76290 r76397  
    2727#include <VBox/vmm/vm.h>
    2828#include <VBox/vmm/hm_vmx.h>
     29#include <VBox/vmm/hmvmxinline.h>
    2930#include <VBox/vmm/hm_svm.h>
    3031#include <VBox/err.h>

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r76198 r76397  
    4040#include "HMInternal.h"
    4141#include <VBox/vmm/vm.h>
     42#include <VBox/vmm/hmvmxinline.h>
    4243#include "HMVMXR0.h"
    4344#include "dtrace/VBoxVMM.h"

  • trunk/src/VBox/VMM/VMMR3/EMHM.cpp

    r74795 r76397  
    4747#include <VBox/dis.h>
    4848#include <VBox/disopcode.h>
     49#include <VBox/err.h>
    4950#include <VBox/vmm/dbgf.h>
    5051#include "VMMTracing.h"

  • trunk/src/VBox/VMM/VMMR3/EMR3Nem.cpp

    r74798 r76397  
    4747#include <VBox/dis.h>
    4848#include <VBox/disopcode.h>
     49#include <VBox/err.h>
    4950#include <VBox/vmm/dbgf.h>
    5051#include "VMMTracing.h"

  • trunk/src/VBox/VMM/VMMR3/EMRaw.cpp

    r74795 r76397  
    5151#include "VMMTracing.h"
    5252
     53#include <VBox/err.h>
    5354#include <VBox/log.h>
    5455#include <iprt/asm.h>

  • trunk/src/VBox/VMM/VMMR3/GIMKvm.cpp

    r73340 r76397  
    3131
    3232#include <VBox/disopcode.h>
     33#include <VBox/err.h>
    3334#include <VBox/version.h>
    3435
    3536#include <iprt/asm-math.h>
    3637#include <iprt/assert.h>
    37 #include <iprt/err.h>
    3838#include <iprt/string.h>
    3939#include <iprt/mem.h>

  • trunk/src/VBox/VMM/VMMR3/NEMR3.cpp

    r72924 r76397  
    3636#include <VBox/vmm/vm.h>
    3737#include <VBox/vmm/uvm.h>
     38#include <VBox/err.h>
    3839
    3940#include <iprt/asm.h>

  • trunk/src/VBox/VMM/include/IOMInline.h

    r69111 r76397  
    1818#ifndef ___IOMInline_h
    1919#define ___IOMInline_h
     20
     21#include <iprt/errcore.h>
    2022
    2123/** @addtogroup grp_iom_int   Internals

  • trunk/src/recompiler/exec.c

    r69465 r76397  
    4949# include <iprt/param.h>
    5050# include <VBox/vmm/pgm.h> /* PGM_DYNAMIC_RAM_ALLOC */
     51# include <VBox/err.h>
    5152#endif /* VBOX */
    5253

  • trunk/src/recompiler/target-i386/op_helper.c

    r69465 r76397  
    3636# include <math.h>
    3737# include "tcg.h"
     38# include <VBox/err.h>
    3839#endif /* VBOX */
    3940
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