Index: trunk/include/VBox/vmm/hm_svm.h
===================================================================
--- trunk/include/VBox/vmm/hm_svm.h	(revision 76432)
+++ trunk/include/VBox/vmm/hm_svm.h	(revision 76438)
@@ -662,7 +662,7 @@
     struct
     {
-        uint64_t    u12Reserved0        : 12;
-        uint64_t    u40Addr             : 40;
-        uint64_t    u12Reserved1        : 12;
+        RT_GCC_EXTENSION uint64_t u12Reserved0        : 12;
+        RT_GCC_EXTENSION uint64_t u40Addr             : 40;
+        RT_GCC_EXTENSION uint64_t u12Reserved1        : 12;
     } n;
     uint64_t    u;
@@ -677,8 +677,8 @@
     struct
     {
-        uint64_t    u8LastGuestCoreId   : 8;
-        uint64_t    u4Reserved          : 4;
-        uint64_t    u40Addr             : 40;
-        uint64_t    u12Reserved         : 12;
+        RT_GCC_EXTENSION uint64_t u8LastGuestCoreId   : 8;
+        RT_GCC_EXTENSION uint64_t u4Reserved          : 4;
+        RT_GCC_EXTENSION uint64_t u40Addr             : 40;
+        RT_GCC_EXTENSION uint64_t u12Reserved         : 12;
     } n;
     uint64_t    u;
Index: trunk/include/VBox/vmm/hm_vmx.h
===================================================================
--- trunk/include/VBox/vmm/hm_vmx.h	(revision 76432)
+++ trunk/include/VBox/vmm/hm_vmx.h	(revision 76438)
@@ -469,17 +469,17 @@
 {
     /** Present bit. */
-    uint64_t    u1Present       : 1;
+    RT_GCC_EXTENSION uint64_t u1Present       : 1;
     /** Writable bit. */
-    uint64_t    u1Write         : 1;
+    RT_GCC_EXTENSION uint64_t u1Write         : 1;
     /** Executable bit. */
-    uint64_t    u1Execute       : 1;
+    RT_GCC_EXTENSION uint64_t u1Execute       : 1;
     /** Reserved (must be 0). */
-    uint64_t    u5Reserved      : 5;
+    RT_GCC_EXTENSION uint64_t u5Reserved      : 5;
     /** Available for software. */
-    uint64_t    u4Available     : 4;
+    RT_GCC_EXTENSION uint64_t u4Available     : 4;
     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
-    uint64_t    u40PhysAddr     : 40;
+    RT_GCC_EXTENSION uint64_t u40PhysAddr     : 40;
     /** Available for software. */
-    uint64_t    u12Available    : 12;
+    RT_GCC_EXTENSION uint64_t u12Available    : 12;
 } EPTPML4EBITS;
 AssertCompileSize(EPTPML4EBITS, 8);
@@ -531,17 +531,17 @@
 {
     /** Present bit. */
-    uint64_t    u1Present       : 1;
+    RT_GCC_EXTENSION uint64_t u1Present       : 1;
     /** Writable bit. */
-    uint64_t    u1Write         : 1;
+    RT_GCC_EXTENSION uint64_t u1Write         : 1;
     /** Executable bit. */
-    uint64_t    u1Execute       : 1;
+    RT_GCC_EXTENSION uint64_t u1Execute       : 1;
     /** Reserved (must be 0). */
-    uint64_t    u5Reserved      : 5;
+    RT_GCC_EXTENSION uint64_t u5Reserved      : 5;
     /** Available for software. */
-    uint64_t    u4Available     : 4;
+    RT_GCC_EXTENSION uint64_t u4Available     : 4;
     /** Physical address of the next level (PD). Restricted by maximum physical address width of the cpu. */
-    uint64_t    u40PhysAddr     : 40;
+    RT_GCC_EXTENSION uint64_t u40PhysAddr     : 40;
     /** Available for software. */
-    uint64_t    u12Available    : 12;
+    RT_GCC_EXTENSION uint64_t u12Available    : 12;
 } EPTPDPTEBITS;
 AssertCompileSize(EPTPDPTEBITS, 8);
@@ -593,19 +593,19 @@
 {
     /** Present bit. */
-    uint64_t    u1Present       : 1;
+    RT_GCC_EXTENSION uint64_t u1Present       : 1;
     /** Writable bit. */
-    uint64_t    u1Write         : 1;
+    RT_GCC_EXTENSION uint64_t u1Write         : 1;
     /** Executable bit. */
-    uint64_t    u1Execute       : 1;
+    RT_GCC_EXTENSION uint64_t u1Execute       : 1;
     /** Reserved (must be 0). */
-    uint64_t    u4Reserved      : 4;
+    RT_GCC_EXTENSION uint64_t u4Reserved      : 4;
     /** Big page (must be 0 here). */
-    uint64_t    u1Size          : 1;
+    RT_GCC_EXTENSION uint64_t u1Size          : 1;
     /** Available for software. */
-    uint64_t    u4Available     : 4;
+    RT_GCC_EXTENSION uint64_t u4Available     : 4;
     /** Physical address of page table. Restricted by maximum physical address width of the cpu. */
-    uint64_t    u40PhysAddr     : 40;
+    RT_GCC_EXTENSION uint64_t u40PhysAddr     : 40;
     /** Available for software. */
-    uint64_t    u12Available    : 12;
+    RT_GCC_EXTENSION uint64_t u12Available    : 12;
 } EPTPDEBITS;
 AssertCompileSize(EPTPDEBITS, 8);
@@ -624,23 +624,23 @@
 {
     /** Present bit. */
-    uint64_t    u1Present       : 1;
+    RT_GCC_EXTENSION uint64_t u1Present       : 1;
     /** Writable bit. */
-    uint64_t    u1Write         : 1;
+    RT_GCC_EXTENSION uint64_t u1Write         : 1;
     /** Executable bit. */
-    uint64_t    u1Execute       : 1;
+    RT_GCC_EXTENSION uint64_t u1Execute       : 1;
     /** EPT Table Memory Type. MBZ for non-leaf nodes. */
-    uint64_t    u3EMT           : 3;
+    RT_GCC_EXTENSION uint64_t u3EMT           : 3;
     /** Ignore PAT memory type */
-    uint64_t    u1IgnorePAT     : 1;
+    RT_GCC_EXTENSION uint64_t u1IgnorePAT     : 1;
     /** Big page (must be 1 here). */
-    uint64_t    u1Size          : 1;
+    RT_GCC_EXTENSION uint64_t u1Size          : 1;
     /** Available for software. */
-    uint64_t    u4Available     : 4;
+    RT_GCC_EXTENSION uint64_t u4Available     : 4;
     /** Reserved (must be 0). */
-    uint64_t    u9Reserved      : 9;
+    RT_GCC_EXTENSION uint64_t u9Reserved      : 9;
     /** Physical address of the 2MB page. Restricted by maximum physical address width of the cpu. */
-    uint64_t    u31PhysAddr     : 31;
+    RT_GCC_EXTENSION uint64_t u31PhysAddr     : 31;
     /** Available for software. */
-    uint64_t    u12Available    : 12;
+    RT_GCC_EXTENSION uint64_t u12Available    : 12;
 } EPTPDE2MBITS;
 AssertCompileSize(EPTPDE2MBITS, 8);
@@ -694,20 +694,20 @@
      *          as present.  Since all our valid entries will have this bit set, it can
      *          be used as a present indicator and allow some code sharing. */
-    uint64_t    u1Present       : 1;
+    RT_GCC_EXTENSION uint64_t u1Present       : 1;
     /** 1 - Writable bit. */
-    uint64_t    u1Write         : 1;
+    RT_GCC_EXTENSION uint64_t u1Write         : 1;
     /** 2 - Executable bit. */
-    uint64_t    u1Execute       : 1;
+    RT_GCC_EXTENSION uint64_t u1Execute       : 1;
     /** 5:3 - EPT Memory Type. MBZ for non-leaf nodes. */
-    uint64_t    u3EMT           : 3;
+    RT_GCC_EXTENSION uint64_t u3EMT           : 3;
     /** 6 - Ignore PAT memory type */
-    uint64_t    u1IgnorePAT     : 1;
+    RT_GCC_EXTENSION uint64_t u1IgnorePAT     : 1;
     /** 11:7 - Available for software. */
-    uint64_t    u5Available     : 5;
+    RT_GCC_EXTENSION uint64_t u5Available     : 5;
     /** 51:12 - Physical address of page. Restricted by maximum physical
      *  address width of the cpu. */
-    uint64_t    u40PhysAddr     : 40;
+    RT_GCC_EXTENSION uint64_t u40PhysAddr     : 40;
     /** 63:52 - Available for software. */
-    uint64_t    u12Available    : 12;
+    RT_GCC_EXTENSION uint64_t u12Available    : 12;
 } EPTPTEBITS;
 AssertCompileSize(EPTPTEBITS, 8);
