Changeset 7655 in vbox

Timestamp:

Mar 31, 2008 1:19:56 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

29165

Message:

PAE fixes & changes

Location:

trunk

Files:

• include/VBox/x86.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/PGMAllBth.h (modified) (8 diffs)
• src/VBox/VMM/VMMAll/PGMAllGst.h (modified) (5 diffs)
• src/VBox/VMM/VMMAll/PGMAllPhys.cpp (modified) (2 diffs)

trunk/include/VBox/x86.h

@@ -1210 +1210 @@
 #define X86_PDE4M_PG_HIGH_SHIFT             19
 
-/** Bits 12-51 - - PAE - Physical Page number. */
-#define X86_PDE4M_PAE_PG_MASK               ( 0x000fffffffc00000ULL )
+/** Bits 21-36 - - PAE - Physical Page number. */
+#define X86_PDE2M_PAE_PG_MASK               ( 0x000fffffffe00000ULL )
 /** Bits 63 - NX - PAE - No execution flag. */
-#define X86_PDE4M_PAE_NX                    RT_BIT_64(63)
+#define X86_PDE2M_PAE_NX                    RT_BIT_64(63)
 
 /**

trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

@@ -829 +829 @@
              */
             Assert(pgmMapAreMappingsEnabled(&pVM->pgm.s));
+            Assert(PGMGetGuestMode(pVM) <= PGMMODE_32_BIT);
             rc = PGM_BTH_NAME(SyncPT)(pVM, iPDSrc, pPDSrc, GCPtrPage);
         }
@@ -1242 +1243 @@
      * Assert preconditions.
      */
-# if GC_ARCH_BITS != 32
-    Assert(GCPtrPage < _4G); //???
-# endif
     STAM_COUNTER_INC(&pVM->pgm.s.StatGCSyncPagePD[(GCPtrPage >> X86_PD_SHIFT) & GST_PD_MASK]);
     Assert(PdeSrc.n.u1Present);
@@ -1390 +1388 @@
                  */
                 /* Calculate the GC physical address of this 4KB shadow page. */
-                RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PAE_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
+                RTGCPHYS GCPhys = (PdeSrc.u & X86_PDE4M_PG_MASK) | ((RTGCUINTPTR)GCPtrPage & GST_BIG_PAGE_OFFSET_MASK);
                 /* Find ram range. */
                 PPGMPAGE pPage;
@@ -1442 +1440 @@
                     }
 #  if PGM_SHW_TYPE == PGM_TYPE_32BIT
-                    pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst]        = PdeDst;
+                    pVM->pgm.s.CTXMID(p,32BitPD)->a[iPDDst]    = PdeDst;
 #  else /* PAE */
                     pVM->pgm.s.CTXMID(ap,PaePDs)[0]->a[iPDDst] = PdeDst;
@@ -2568 +2566 @@
     Assert(pPDSrc);
 #ifndef IN_GC
-    Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & X86_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
+    Assert(MMPhysGCPhys2HCVirt(pVM, (RTGCPHYS)(cr3 & GST_CR3_PAGE_MASK), sizeof(*pPDSrc)) == pPDSrc);
 #endif
 
@@ -2891 +2889 @@
      * Check that the Guest CR3 and all it's mappings are correct.
      */
-    AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & X86_CR3_PAGE_MASK),
+    AssertMsgReturn(pPGM->GCPhysCR3 == (cr3 & GST_CR3_PAGE_MASK),
                     ("Invalid GCPhysCR3=%VGp cr3=%VGp\n", pPGM->GCPhysCR3, (RTGCPHYS)cr3),
                     false);
@@ -2897 +2895 @@
     AssertRCReturn(rc, 1);
     HCPhys = NIL_RTHCPHYS;
-    rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & X86_CR3_PAGE_MASK, &HCPhys);
+    rc = pgmRamGCPhys2HCPhys(pPGM, cr3 & GST_CR3_PAGE_MASK, &HCPhys);
     AssertMsgReturn(HCPhys == HCPhysShw, ("HCPhys=%VHp HCPhyswShw=%VHp (cr3)\n", HCPhys, HCPhysShw), false);
 # ifdef IN_RING3
@@ -2903 +2901 @@
     rc = PGMR3DbgHCPtr2GCPhys(pVM, pPGM->pGuestPDHC, &GCPhys);
     AssertRCReturn(rc, 1);
-    AssertMsgReturn((cr3 & X86_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
+    AssertMsgReturn((cr3 & GST_CR3_PAGE_MASK) == GCPhys, ("GCPhys=%VGp cr3=%VGp\n", GCPhys, (RTGCPHYS)cr3), false);
 # endif
     const X86PD *pPDSrc = CTXSUFF(pPGM->pGuestPD);

trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

@@ -38 +38 @@
 #undef GST_PT_MASK
 #undef GST_TOTAL_PD_ENTRIES
+#undef GST_CR3_PAGE_MASK
 
 #if PGM_GST_TYPE == PGM_TYPE_32BIT
@@ -58 +59 @@
 # define GST_PT_SHIFT               X86_PT_SHIFT
 # define GST_PT_MASK                X86_PT_MASK
+# define GST_CR3_PAGE_MASK          X86_CR3_PAGE_MASK
 #else
 # define GSTPT                      X86PTPAE
@@ -70 +72 @@
 # define GST_BIG_PAGE_OFFSET_MASK   X86_PAGE_2M_OFFSET_MASK
 # define GST_PDE_PG_MASK            X86_PDE_PAE_PG_MASK
-# define GST_PDE4M_PG_MASK          X86_PDE4M_PAE_PG_MASK
+# define GST_PDE4M_PG_MASK          X86_PDE2M_PAE_PG_MASK
 # define GST_PD_SHIFT               X86_PD_PAE_SHIFT
 # define GST_PD_MASK                X86_PD_PAE_MASK
@@ -77 +79 @@
 # define GST_PT_SHIFT               X86_PT_PAE_SHIFT
 # define GST_PT_MASK                X86_PT_PAE_MASK
+# define GST_CR3_PAGE_MASK          X86_CR3_PAE_PAGE_MASK
 #endif
 
@@ -286 +289 @@
              * 4MB Page table
              */
-            Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | X86_PDE4M_PAE_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
+            Pde.u = (Pde.u & (fMask | ((fMask & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT) | GST_PDE4M_PG_MASK | X86_PDE4M_PS)) /** @todo pse36 */
                   | (fFlags & ~GST_PTE_PG_MASK)
                   | ((fFlags & X86_PTE_PAT) << X86_PDE4M_PAT_SHIFT);

trunk/src/VBox/VMM/VMMAll/PGMAllPhys.cpp

@@ -1018 +1018 @@
     {
         /** @todo long mode! */
+        Assert(PGMGetGuestMode(pVM) < PGMMODE_AMD64);
+
         PX86PDPTR pPdptr;
         rc = PGM_GCPHYS_2_PTR(pVM, cr3 & X86_CR3_PAE_PAGE_MASK, &pPdptr);
@@ -1034 +1036 @@
                         if ((fFlags & X86_CR4_PSE) && Pde.b.u1Size)
                         {   /* (big page) */
-                            rc = PGMPhysGCPhys2HCPtr(pVM, (Pde.u & X86_PDE4M_PAE_PG_MASK) | ((RTGCUINTPTR)GCPtr & X86_PAGE_4M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
+                            rc = PGMPhysGCPhys2HCPtr(pVM, (Pde.u & X86_PDE2M_PAE_PG_MASK) | ((RTGCUINTPTR)GCPtr & X86_PAGE_2M_OFFSET_MASK), 1 /* we always stay within one page */, pHCPtr);
                         }
                         else