VirtualBox

Changeset 76678 in vbox for trunk/include/iprt


Ignore:
Timestamp:
Jan 7, 2019 1:48:16 PM (6 years ago)
Author:
vboxsync
Message:

Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)

Location:
trunk
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0:104445,104938,104943,104950,104952-104953,104987-104988,104990,106453
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
        10 /branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,125768,125779-125780,125812
         10/branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
        1111/branches/andy/draganddrop:90781-91268
        1212/branches/andy/guestctrl20:78916,78930

  • trunk/include/iprt/x86.h

    r76585 r76678  
    619619/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
    620620#define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
    621 
     621/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
     622#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD         RT_BIT_32(28)
    622623/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
    623624#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
    … …  
    12421243#define MSR_IA32_MTRR_CAP                   0xFE
    12431244
    1244 /** Architecture capabilities (bugfixes).
    1245  * @note May move  */
     1245/** Architecture capabilities (bugfixes). */
    12461246#define MSR_IA32_ARCH_CAPABILITIES          UINT32_C(0x10a)
    1247 /** CPU is no subject to spectre problems. */
    1248 #define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
     1247/** CPU is no subject to meltdown problems. */
     1248#define MSR_IA32_ARCH_CAP_F_RDCL_NO         RT_BIT_32(0)
    12491249/** CPU has better IBRS and you can leave it on all the time. */
    1250 #define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
     1250#define MSR_IA32_ARCH_CAP_F_IBRS_ALL        RT_BIT_32(1)
     1251/** CPU has return stack buffer (RSB) override. */
     1252#define MSR_IA32_ARCH_CAP_F_RSBO            RT_BIT_32(2)
     1253/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
     1254 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
     1255#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
     1256
     1257/** Flush command register. */
     1258#define MSR_IA32_FLUSH_CMD                  UINT32_C(0x10b)
     1259/** Flush the level 1 data cache when this bit is written. */
     1260#define MSR_IA32_FLUSH_CMD_F_L1D            RT_BIT_32(0)
    12511261
    12521262/** Cache control/info. */

  • trunk/include/iprt/x86.mac

    r76557 r76678  
    185185%define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT_32(26)
    186186%define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
     187%define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD         RT_BIT_32(28)
    187188%define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
    188189%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF     RT_BIT_32(0)
    … …  
    432433%define MSR_IA32_MTRR_CAP                   0xFE
    433434%define MSR_IA32_ARCH_CAPABILITIES          0x10a
    434 %define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
    435 %define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
     435%define MSR_IA32_ARCH_CAP_F_RDCL_NO         RT_BIT_32(0)
     436%define MSR_IA32_ARCH_CAP_F_IBRS_ALL        RT_BIT_32(1)
     437%define MSR_IA32_ARCH_CAP_F_RSBO            RT_BIT_32(2)
     438%define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
     439%define MSR_IA32_FLUSH_CMD                  0x10b
     440%define MSR_IA32_FLUSH_CMD_F_L1D            RT_BIT_32(0)
    436441%define MSR_BBL_CR_CTL3                     0x11e
    437442%ifndef MSR_IA32_SYSENTER_CS
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