Index: trunk/include/VBox/settings.h
===================================================================
--- trunk/include/VBox/settings.h	(revision 76665)
+++ trunk/include/VBox/settings.h	(revision 76678)
@@ -1032,4 +1032,6 @@
     bool                fSpecCtrl;              //< added out of cycle, after 1.16 was out.
     bool                fSpecCtrlByHost;        //< added out of cycle, after 1.16 was out.
+    bool                fL1DFlushOnSched ;      //< added out of cycle, after 1.16 was out.
+    bool                fL1DFlushOnVMEntry ;    //< added out of cycle, after 1.16 was out.
     bool                fNestedHWVirt;          //< requires settings version 1.17 (VirtualBox 6.0)
     typedef enum LongModeType { LongMode_Enabled, LongMode_Disabled, LongMode_Legacy } LongModeType;
Index: trunk/include/VBox/vmm/cpum.h
===================================================================
--- trunk/include/VBox/vmm/cpum.h	(revision 76665)
+++ trunk/include/VBox/vmm/cpum.h	(revision 76678)
@@ -733,4 +733,5 @@
     kCpumMsrWrFn_Ia32SpecCtrl,
     kCpumMsrWrFn_Ia32PredCmd,
+    kCpumMsrWrFn_Ia32FlushCmd,
 
     kCpumMsrWrFn_Amd64Efer,
@@ -1061,4 +1062,6 @@
     /** Supports IA32_SPEC_CTRL.STIBP. */
     uint32_t        fStibp : 1;
+    /** Supports IA32_FLUSH_CMD. */
+    uint32_t        fFlushCmd : 1;
     /** Supports IA32_ARCH_CAP. */
     uint32_t        fArchCap : 1;
@@ -1101,11 +1104,24 @@
     uint32_t        fVmx : 1;
 
-    /** Indicates that speculative execution control CPUID bits and
-     *  MSRs are exposed. The details are different for Intel and
-     * AMD but both have similar functionality. */
+    /** Indicates that speculative execution control CPUID bits and MSRs are exposed.
+     * The details are different for Intel and AMD but both have similar
+     * functionality. */
     uint32_t        fSpeculationControl : 1;
 
+    /** MSR_IA32_ARCH_CAPABILITIES: RDCL_NO (bit 0).
+     * @remarks Only safe use after CPUM ring-0 init! */
+    uint32_t        fArchRdclNo : 1;
+    /** MSR_IA32_ARCH_CAPABILITIES: IBRS_ALL (bit 1).
+     * @remarks Only safe use after CPUM ring-0 init! */
+    uint32_t        fArchIbrsAll : 1;
+    /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 2).
+     * @remarks Only safe use after CPUM ring-0 init! */
+    uint32_t        fArchRsbOverride : 1;
+    /** MSR_IA32_ARCH_CAPABILITIES: RSB Override (bit 3).
+     * @remarks Only safe use after CPUM ring-0 init! */
+    uint32_t        fArchVmmNeedNotFlushL1d : 1;
+
     /** Alignment padding / reserved for future use. */
-    uint32_t        fPadding : 15;
+    uint32_t        fPadding : 10;
 
     /** SVM: Supports Nested-paging. */
Index: trunk/include/VBox/vmm/cpum.mac
===================================================================
--- trunk/include/VBox/vmm/cpum.mac	(revision 76665)
+++ trunk/include/VBox/vmm/cpum.mac	(revision 76678)
@@ -290,4 +290,6 @@
 %define CPUMCTX_WSF_IBPB_EXIT           RT_BIT_32(0)
 %define CPUMCTX_WSF_IBPB_ENTRY          RT_BIT_32(1)
+%define CPUMCTX_WSF_L1D_ENTRY           RT_BIT_32(2)
+
 
 %define CPUMSELREG_FLAGS_VALID      0x0001
Index: trunk/include/VBox/vmm/cpumctx.h
===================================================================
--- trunk/include/VBox/vmm/cpumctx.h	(revision 76665)
+++ trunk/include/VBox/vmm/cpumctx.h	(revision 76678)
@@ -943,4 +943,6 @@
 /** Touch IA32_PRED_CMD.IBPB on VM entry. */
 #define CPUMCTX_WSF_IBPB_ENTRY          RT_BIT_32(1)
+/** Touch IA32_FLUSH_CMD.L1D on VM entry. */
+#define CPUMCTX_WSF_L1D_ENTRY           RT_BIT_32(2)
 /** @} */
 
Index: trunk/include/iprt/x86.h
===================================================================
--- trunk/include/iprt/x86.h	(revision 76665)
+++ trunk/include/iprt/x86.h	(revision 76678)
@@ -619,5 +619,6 @@
 /** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
 #define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
-
+/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
+#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD         RT_BIT_32(28)
 /** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
 #define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
@@ -1242,11 +1243,20 @@
 #define MSR_IA32_MTRR_CAP                   0xFE
 
-/** Architecture capabilities (bugfixes).
- * @note May move  */
+/** Architecture capabilities (bugfixes). */
 #define MSR_IA32_ARCH_CAPABILITIES          UINT32_C(0x10a)
-/** CPU is no subject to spectre problems. */
-#define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
+/** CPU is no subject to meltdown problems. */
+#define MSR_IA32_ARCH_CAP_F_RDCL_NO         RT_BIT_32(0)
 /** CPU has better IBRS and you can leave it on all the time. */
-#define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
+#define MSR_IA32_ARCH_CAP_F_IBRS_ALL        RT_BIT_32(1)
+/** CPU has return stack buffer (RSB) override. */
+#define MSR_IA32_ARCH_CAP_F_RSBO            RT_BIT_32(2)
+/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
+ * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
+#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
+
+/** Flush command register. */
+#define MSR_IA32_FLUSH_CMD                  UINT32_C(0x10b)
+/** Flush the level 1 data cache when this bit is written. */
+#define MSR_IA32_FLUSH_CMD_F_L1D            RT_BIT_32(0)
 
 /** Cache control/info. */
Index: trunk/include/iprt/x86.mac
===================================================================
--- trunk/include/iprt/x86.mac	(revision 76665)
+++ trunk/include/iprt/x86.mac	(revision 76678)
@@ -185,4 +185,5 @@
 %define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT_32(26)
 %define X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT_32(27)
+%define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD         RT_BIT_32(28)
 %define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT_32(29)
 %define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF     RT_BIT_32(0)
@@ -432,6 +433,10 @@
 %define MSR_IA32_MTRR_CAP                   0xFE
 %define MSR_IA32_ARCH_CAPABILITIES          0x10a
-%define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX     RT_BIT_32(0)
-%define MSR_IA32_ARCH_CAP_F_BETTER_IBRS     RT_BIT_32(1)
+%define MSR_IA32_ARCH_CAP_F_RDCL_NO         RT_BIT_32(0)
+%define MSR_IA32_ARCH_CAP_F_IBRS_ALL        RT_BIT_32(1)
+%define MSR_IA32_ARCH_CAP_F_RSBO            RT_BIT_32(2)
+%define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
+%define MSR_IA32_FLUSH_CMD                  0x10b
+%define MSR_IA32_FLUSH_CMD_F_L1D            RT_BIT_32(0)
 %define MSR_BBL_CR_CTL3                     0x11e
 %ifndef MSR_IA32_SYSENTER_CS
