VirtualBox

Changeset 76678 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
Jan 7, 2019 1:48:16 PM (6 years ago)
Author:
vboxsync
Message:

Port r124260, r124263, r124271, r124273, r124277, r124278, r124279, r124284, r124285, r124286, r124287, r124288, r124289 and r124290 (Ported fixes over from 5.2, see bugref:9179 for more information)

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0:104445,104938,104943,104950,104952-104953,104987-104988,104990,106453
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
        10 /branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,125768,125779-125780,125812
         10/branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
        1111/branches/andy/draganddrop:90781-91268
        1212/branches/andy/guestctrl20:78916,78930

  • trunk/src/VBox

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-5.0/src/VBox:104938,104943,104950,104987-104988,104990,106453
        99/branches/VBox-5.1/src/VBox:112367,116543,116550,116568,116573
        10 /branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,125768,125779-125780,125812
         10/branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124263,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
        1111/branches/andy/draganddrop/src/VBox:90781-91268
        1212/branches/andy/guestctrl20/src/VBox:78916,78930

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r76553 r76678  
    18701870            pFeatures->fIbrs                = pFeatures->fIbpb;
    18711871            pFeatures->fStibp               = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_STIBP);
    1872 #if 0   // Disabled until IA32_ARCH_CAPABILITIES support can be tested
     1872            pFeatures->fFlushCmd            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
    18731873            pFeatures->fArchCap             = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
    1874 #endif
    18751874        }
    18761875
    … …  
    18781877        PCCPUMCPUIDLEAF const pMWaitLeaf = cpumR3CpuIdFindLeaf(paLeaves, cLeaves, 5);
    18791878        if (pMWaitLeaf)
    1880         {
    18811879            pFeatures->fMWaitExtensions = (pMWaitLeaf->uEcx & (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0))
    1882                                                            == (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
    1883         }
     1880                                        ==                    (X86_CPUID_MWAIT_ECX_EXT | X86_CPUID_MWAIT_ECX_BREAKIRQIF0);
    18841881
    18851882        /* Extended features. */
    … …  
    24732470    CPUMISAEXTCFG   enmPcid;
    24742471    CPUMISAEXTCFG   enmInvpcid;
     2472    CPUMISAEXTCFG   enmFlushCmdMsr;
    24752473
    24762474    CPUMISAEXTCFG   enmAbm;
    … …  
    32743272                               //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT(26)
    32753273                               //| X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT(27)
     3274                               | (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
    32763275                               //| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT(29)
    32773276                               ;
    … …  
    33023301                    PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEbx, SHA,        X86_CPUID_STEXT_FEATURE_EBX_SHA);
    33033302                    PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
     3303                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD,  X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
    33043304                }
    33053305
    … …  
    33153315                if (pConfig->enmInvpcid == CPUMISAEXTCFG_ENABLED_ALWAYS)
    33163316                    pCurLeaf->uEbx |= X86_CPUID_STEXT_FEATURE_EBX_INVPCID;
     3317                if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
     3318                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
    33173319                break;
    33183320            }
    … …  
    41224124                                  "|PCID"
    41234125                                  "|INVPCID"
     4126                                  "|FlushCmdMsr"
    41244127                                  "|ABM"
    41254128                                  "|SSE4A"
    … …  
    42774280    AssertLogRelRCReturn(rc, rc);
    42784281
     4282    /** @cfgm{/CPUM/IsaExts/FlushCmdMsr, isaextcfg, true}
     4283     * Whether to expose the IA32_FLUSH_CMD MSR to the guest.
     4284     */
     4285    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "FlushCmdMsr", &pConfig->enmFlushCmdMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     4286    AssertLogRelRCReturn(rc, rc);
     4287
    42794288
    42804289    /* AMD: */
    … …  
    44194428    }
    44204429
     4430    /*
     4431     * Setup MSRs introduced in microcode updates or that are otherwise not in
     4432     * the CPU profile, but are advertised in the CPUID info we just sanitized.
     4433     */
     4434    if (RT_SUCCESS(rc))
     4435        rc = cpumR3MsrReconcileWithCpuId(pVM);
    44214436    /*
    44224437     * MSR fudging.
    … …  
    48314846                    if (!pMsrRange)
    48324847                    {
     4848                        /** @todo incorrect fWrGpMask. */
    48334849                        static CPUMMSRRANGE const s_SpecCtrl =
    48344850                        {
    … …  
    48444860                }
    48454861
    4846                 if (pVM->cpum.s.HostFeatures.fArchCap) {
     4862                if (pVM->cpum.s.HostFeatures.fArchCap)
     4863                {
    48474864                    pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
    48484865
    … …  
    50255042            pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
    50265043            if (pLeaf)
    5027                 /*pVM->cpum.s.aGuestCpuIdPatmStd[7].uEdx =*/ pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP | X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
     5044                pLeaf->uEdx &= ~(  X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP
     5045                                 | X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
    50285046            pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
    50295047            Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
    … …  
    63426360    DBGFREGSUBFIELD_RO("IBRS_IBPB\0"    "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB",   26, 1, 0),
    63436361    DBGFREGSUBFIELD_RO("STIBP\0"        "Supports IA32_SPEC_CTRL.STIBP",                27, 1, 0),
     6362    DBGFREGSUBFIELD_RO("FLUSH_CMD\0"    "Supports IA32_FLUSH_CMD",                      28, 1, 0),
    63446363    DBGFREGSUBFIELD_RO("ARCHCAP\0"      "Supports IA32_ARCH_CAP",                       29, 1, 0),
    63456364    DBGFREGSUBFIELD_TERMINATOR()

  • trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

    r76561 r76678  
    595595
    596596/**
     597 * Reconciles CPUID info with MSRs (selected ones).
     598 *
     599 * @returns VBox status code.
     600 * @param   pVM                 The cross context VM structure.
     601 */
     602int cpumR3MsrReconcileWithCpuId(PVM pVM)
     603{
     604    PCCPUMMSRRANGE papToAdd[10];
     605    uint32_t      cToAdd = 0;
     606
     607    /*
     608     * The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
     609     */
     610    if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
     611    {
     612        static CPUMMSRRANGE const s_FlushCmd =
     613        {
     614            /*.uFirst =*/       MSR_IA32_FLUSH_CMD,
     615            /*.uLast =*/        MSR_IA32_FLUSH_CMD,
     616            /*.enmRdFn =*/      kCpumMsrRdFn_WriteOnly,
     617            /*.enmWrFn =*/      kCpumMsrWrFn_Ia32FlushCmd,
     618            /*.offCpumCpu =*/   UINT16_MAX,
     619            /*.fReserved =*/    0,
     620            /*.uValue =*/       0,
     621            /*.fWrIgnMask =*/   0,
     622            /*.fWrGpMask =*/    ~MSR_IA32_FLUSH_CMD_F_L1D,
     623            /*.szName = */      "IA32_FLUSH_CMD"
     624        };
     625        papToAdd[cToAdd++] = &s_FlushCmd;
     626    }
     627
     628    /*
     629     * Do the adding.
     630     */
     631    for (uint32_t i = 0; i < cToAdd; i++)
     632    {
     633        PCCPUMMSRRANGE pRange = papToAdd[i];
     634        LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
     635        int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
     636                                       pRange);
     637        if (RT_FAILURE(rc))
     638            return rc;
     639    }
     640    return VINF_SUCCESS;
     641}
     642
     643
     644/**
    597645 * Worker for cpumR3MsrApplyFudge that applies one table.
    598646 *

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r76553 r76678  
    485485                              "|IBPBOnVMEntry"
    486486                              "|SpecCtrlByHost"
     487                              "|L1DFlushOnSched"
     488                              "|L1DFlushOnVMEntry"
    487489                              "|TPRPatchingEnabled"
    488490                              "|64bitEnabled"
    … …  
    675677    rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
    676678    AssertLogRelRCReturn(rc, rc);
     679
     680    /** @cfgm{/HM/L1DFlushOnSched, bool, true}
     681     * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     682    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
     683    AssertLogRelRCReturn(rc, rc);
     684
     685    /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
     686     * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     687    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
     688    AssertLogRelRCReturn(rc, rc);
     689
     690    /* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
     691    if (pVM->hm.s.fL1dFlushOnVmEntry)
     692        pVM->hm.s.fL1dFlushOnSched = false;
    677693
    678694    /** @cfgm{/HM/SpecCtrlByHost, bool}
    … …  
    12931309
    12941310    /*
     1311     * Check if L1D flush is needed/possible.
     1312     */
     1313    if (   !pVM->cpum.ro.HostFeatures.fFlushCmd
     1314        || pVM->cpum.ro.HostFeatures.enmMicroarch <  kCpumMicroarch_Intel_Core7_Nehalem
     1315        || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
     1316        || pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
     1317        || pVM->cpum.ro.HostFeatures.fArchRdclNo)
     1318        pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
     1319
     1320    /*
    12951321     * Sync options.
    12961322     */
    … …  
    13091335                pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
    13101336        }
     1337        if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
     1338            pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_L1D_ENTRY;
    13111339        if (iCpu == 0)
    1312             LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
    1313                     pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
     1340            LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool\n",
     1341                    pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
     1342                    pVM->hm.s.fL1dFlushOnSched));
    13141343    }
    13151344
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