Changeset 76764 in vbox
- Timestamp:
- Jan 11, 2019 7:46:37 AM (6 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/Devices/Network/DevPCNet.cpp
r76749 r76764 238 238 #define CSR_VERSION_LOW_79C973 0x5003 /* the lower two bits are always 11b for AMD (JEDEC) */ 239 239 #define CSR_VERSION_LOW_79C970A 0x1003 240 #define CSR_VERSION_LOW_79C960 0x 0003240 #define CSR_VERSION_LOW_79C960 0x3003 241 241 #define CSR_VERSION_HIGH 0x0262 242 242 /** @} */ … … 257 257 DEV_AM79C970A = 0, /* PCnet-PCI II (PCI, 10 Mbps). */ 258 258 DEV_AM79C973 = 1, /* PCnet-FAST III (PCI, 10/100 Mbps). */ 259 DEV_AM79C960 = 2 /* PCnet-ISA (ISA, 10 Mbps, NE2100/NE1500T compatible) */ 259 DEV_AM79C960 = 2, /* PCnet-ISA (ISA, 10 Mbps, NE2100/NE1500T compatible) */ 260 DEV_AM79C960_EB = 3 /* PCnet-ISA (ISA, 10 Mbps, Racal InterLan EtherBlaster compatible) */ 260 261 }; 261 262 262 263 #define PCNET_IS_PCI(pcnet) ((pcnet->uDevType == DEV_AM79C970A) || (pcnet->uDevType == DEV_AM79C973)) 263 #define PCNET_IS_ISA(pcnet) ( pcnet->uDevType == DEV_AM79C960)264 #define PCNET_IS_ISA(pcnet) ((pcnet->uDevType == DEV_AM79C960) || (pcnet->uDevType == DEV_AM79C960_EB)) 264 265 265 266 /* … … 292 293 * There were also non-busmastering LANCE adapters, such as the BICC 4110-1, DEC DEPCA, 293 294 * or NTI 16. Those are uninteresting. 295 * 296 * Newer adapters based on the integrated PCnet-ISA (Am79C960) and later have a fixed 297 * register layout compatible with the NE2100. However, they may still require different 298 * drivers. At least two different incompatible drivers exist for PCnet-based cards: 299 * Those from AMD and those from Racal InterLan for their EtherBlaster cards. The PROM 300 * on EtherBlaster cards uses a different signature ('RD' instead of 'WW') and Racal's 301 * drivers insist on the MAC address having the Racal-Datacom OUI (02 07 01). 294 302 */ 295 303 … … 406 414 RTGCPHYS32 MMIOBase; 407 415 408 /** Base port of the I/O space region (PCI). */416 /** Base port of the I/O space region. */ 409 417 RTIOPORT IOPortBase; 410 418 /** If set the link is currently up. */ … … 417 425 /** The configured MAC address. */ 418 426 RTMAC MacConfigured; 419 /** Base port of the I/O space region (ISA). */420 RTIOPORT IOPortBaseISA;427 /** Alignment padding. */ 428 uint8_t Alignment3[2]; 421 429 422 430 /** The LED. */ … … 1307 1315 break; 1308 1316 case DEV_AM79C960: 1317 case DEV_AM79C960_EB: 1309 1318 pThis->aCSR[88] = CSR_VERSION_LOW_79C960; 1310 1319 pThis->aCSR[89] = 0x0000; … … 3350 3359 pThis->aPROM[ 8] = 0x00; 3351 3360 pThis->aPROM[12] = pThis->aPROM[13] = 0x00; 3352 pThis->aPROM[14] = pThis->aPROM[15] = 0x57; /* NE2100 'WW' signature. */ 3361 if (pThis->uDevType == DEV_AM79C960_EB) 3362 { 3363 pThis->aPROM[14] = 0x52; 3364 pThis->aPROM[15] = 0x44; /* NI6510 EtherBlaster 'RD' signature. */ 3365 } 3366 else 3367 pThis->aPROM[14] = pThis->aPROM[15] = 0x57; /* NE2100 'WW' signature. */ 3368 3353 3369 /* 0x00/0xFF=ISA, 0x01=PnP, 0x10=VLB, 0x11=PCI */ 3354 switch (pThis->uDevType) 3355 { 3356 default: 3357 case DEV_AM79C970A: 3358 case DEV_AM79C973: pThis->aPROM[ 9] = 0x11; break; 3359 case DEV_AM79C960: pThis->aPROM[ 9] = 0x00; break; 3360 } 3370 if (PCNET_IS_PCI(pThis)) 3371 pThis->aPROM[ 9] = 0x11; 3372 else 3373 pThis->aPROM[ 9] = 0x00; 3361 3374 3362 3375 for (i = 0, checksum = 0; i < 16; i++) … … 4059 4072 bool fRcvRing = false; 4060 4073 bool fXmtRing = false; 4074 bool fAPROM = false; 4061 4075 4062 4076 /* … … 4067 4081 fRcvRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "rcv"); 4068 4082 fXmtRing = strstr(pszArgs, "verbose") || strstr(pszArgs, "xmt"); 4083 fAPROM = strstr(pszArgs, "verbose") || strstr(pszArgs, "aprom"); 4069 4084 } 4070 4085 … … 4075 4090 switch (pThis->uDevType) 4076 4091 { 4077 case DEV_AM79C970A: pcszModel = "AM79C970A"; break; 4078 case DEV_AM79C973: pcszModel = "AM79C973"; break; 4079 case DEV_AM79C960: pcszModel = "AM79C960"; break; 4080 default: pcszModel = "Unknown"; break; 4092 case DEV_AM79C970A: pcszModel = "AM79C970A"; break; 4093 case DEV_AM79C973: pcszModel = "AM79C973"; break; 4094 case DEV_AM79C960: pcszModel = "AM79C960/NE2100"; break; 4095 case DEV_AM79C960_EB: pcszModel = "AM79C960/EtherBlaster"; break; 4096 default: pcszModel = "Unknown"; break; 4081 4097 } 4082 4098 pHlp->pfnPrintf(pHlp, … … 4280 4296 } 4281 4297 4298 /* Dump the Addres PROM (APROM). */ 4299 if (fAPROM) 4300 { 4301 pHlp->pfnPrintf(pHlp, 4302 "Address PROM:\n %Rhxs\n", pThis->aPROM); 4303 4304 4305 } 4306 4282 4307 PDMCritSectLeave(&pThis->CritSect); 4283 4308 } … … 5026 5051 else if (!strcmp(szChipType, "Am79C960")) 5027 5052 pThis->uDevType = DEV_AM79C960; /* 10 Mbps PCnet-ISA, NE2100/Am2100 compatible. */ 5053 else if (!strcmp(szChipType, "Am79C960_EB")) 5054 { 5055 pThis->uDevType = DEV_AM79C960_EB; /* 10 Mbps PCnet-ISA, Racal InterLink NI6510 EtherBlaster compatible. */ 5056 /* NI6510 drivers (at least Racal's and Linux) require the OUI to be InterLan's (Racal-Datacom). 5057 * Refuse loading if OUI doesn't match, because otherwise drivers won't load in the guest. 5058 */ 5059 if (memcmp(&pThis->MacConfigured, "\x02\x07\x01", 3)) 5060 return PDMDevHlpVMSetError(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES, RT_SRC_POS, 5061 N_("Configuration error: MAC address OUI for EtherBlaster must be 02 07 01"), 5062 szChipType); 5063 } 5028 5064 else 5029 5065 { … … 5048 5084 * Process ISA configuration options. The defaults are chosen to be NE2100/Am2100 compatible. 5049 5085 */ 5050 rc = CFGMR3QueryPortDef(pCfg, "Port", &pThis->IOPortBase ISA, 0x300);5086 rc = CFGMR3QueryPortDef(pCfg, "Port", &pThis->IOPortBase, 0x300); 5051 5087 if (RT_FAILURE(rc)) 5052 5088 return PDMDEV_SET_ERROR(pDevIns, rc, … … 5176 5212 if (PCNET_IS_ISA(pThis)) 5177 5213 { 5178 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase ISA, 0x10, 0, pcnetIOPortAPromWrite,5214 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase, 0x10, 0, pcnetIOPortAPromWrite, 5179 5215 pcnetIOPortAPromRead, NULL, NULL, "PCnet APROM"); 5180 5216 if (RT_FAILURE(rc)) 5181 5217 return rc; 5182 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase ISA+ 0x10, 0x10, 0, pcnetIOPortWrite,5218 rc = PDMDevHlpIOPortRegister(pDevIns, pThis->IOPortBase + 0x10, 0x10, 0, pcnetIOPortWrite, 5183 5219 pcnetIOPortRead, NULL, NULL, "PCnet"); 5184 5220 if (RT_FAILURE(rc)) … … 5187 5223 if (pThis->fGCEnabled) 5188 5224 { 5189 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase ISA, 0x10, 0, "pcnetIOPortAPromWrite",5225 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase, 0x10, 0, "pcnetIOPortAPromWrite", 5190 5226 "pcnetIOPortAPromRead", NULL, NULL, "PCnet APROM"); 5191 5227 if (RT_FAILURE(rc)) 5192 5228 return rc; 5193 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase ISA+ 0x10, 0x10, 0, "pcnetIOPortWrite",5229 rc = PDMDevHlpIOPortRegisterRC(pDevIns, pThis->IOPortBase + 0x10, 0x10, 0, "pcnetIOPortWrite", 5194 5230 "pcnetIOPortRead", NULL, NULL, "PCnet"); 5195 5231 if (RT_FAILURE(rc)) … … 5198 5234 if (pThis->fR0Enabled) 5199 5235 { 5200 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase ISA, 0x10, 0, "pcnetIOPortAPromWrite",5236 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase, 0x10, 0, "pcnetIOPortAPromWrite", 5201 5237 "pcnetIOPortAPromRead", NULL, NULL, "PCnet APROM"); 5202 5238 if (RT_FAILURE(rc)) 5203 5239 return rc; 5204 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase ISA+ 0x10, 0x10, 0, "pcnetIOPortWrite",5240 rc = PDMDevHlpIOPortRegisterR0(pDevIns, pThis->IOPortBase + 0x10, 0x10, 0, "pcnetIOPortWrite", 5205 5241 "pcnetIOPortRead", NULL, NULL, "PCnet"); 5206 5242 if (RT_FAILURE(rc))
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