Changeset 76985 in vbox for trunk/src/VBox/Devices
- Timestamp:
- Jan 25, 2019 11:42:07 AM (6 years ago)
- svn:sync-xref-src-repo-rev:
- 128394
- Location:
- trunk/src/VBox/Devices
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Bus/DevPCI.cpp
r76553 r76985 495 495 goto default_map; 496 496 /* VGA: map frame buffer to default Bochs VBE address */ 497 int iRegion = devpciR3GetWord(pPciDev, VBOX_PCI_SUBSYSTEM_VENDOR_ID) == 0x15ad ? 1 : 0; 498 devpciR3BiosInitSetRegionAddress(pBus, pPciDev, iRegion, 0xe0000000); 497 devpciR3BiosInitSetRegionAddress(pBus, pPciDev, 0, 0xe0000000); 499 498 /* 500 499 * Legacy VGA I/O ports are implicitly decoded by a VGA class device. But -
trunk/src/VBox/Devices/Graphics/DevVGA-SVGA.cpp
r76951 r76985 5022 5022 if (enmType == PCI_ADDRESS_SPACE_IO) 5023 5023 { 5024 AssertReturn(iRegion == 0, VERR_INTERNAL_ERROR);5024 AssertReturn(iRegion == pThis->pciRegions.iIO, VERR_INTERNAL_ERROR); 5025 5025 rc = PDMDevHlpIOPortRegister(pDevIns, (RTIOPORT)GCPhysAddress, cb, 0, 5026 5026 vmsvgaIOWrite, vmsvgaIORead, NULL /* OutStr */, NULL /* InStr */, "VMSVGA"); … … 5047 5047 else 5048 5048 { 5049 AssertReturn(iRegion == 2&& enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR);5049 AssertReturn(iRegion == pThis->pciRegions.iFIFO && enmType == PCI_ADDRESS_SPACE_MEM, VERR_INTERNAL_ERROR); 5050 5050 if (GCPhysAddress != NIL_RTGCPHYS) 5051 5051 { -
trunk/src/VBox/Devices/Graphics/DevVGA.cpp
r76553 r76985 5469 5469 Log(("vgaR3IORegionMap: iRegion=%d GCPhysAddress=%RGp cb=%RGp enmType=%d\n", iRegion, GCPhysAddress, cb, enmType)); 5470 5470 #ifdef VBOX_WITH_VMSVGA 5471 AssertReturn( iRegion == (pThis->fVMSVGAEnabled ? 1U : 0U)5471 AssertReturn( iRegion == pThis->pciRegions.iVRAM 5472 5472 && enmType == (pThis->fVMSVGAEnabled ? PCI_ADDRESS_SPACE_MEM : PCI_ADDRESS_SPACE_MEM_PREFETCH), 5473 5473 VERR_INTERNAL_ERROR); 5474 5474 #else 5475 AssertReturn(iRegion == 0&& enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR);5475 AssertReturn(iRegion == pThis->pciRegions.iVRAM && enmType == PCI_ADDRESS_SPACE_MEM_PREFETCH, VERR_INTERNAL_ERROR); 5476 5476 #endif 5477 5477 … … 5546 5546 if (pThis->fVMSVGAEnabled) 5547 5547 { 5548 if (iRegion == 2 /*FIFO*/)5548 if (iRegion == pThis->pciRegions.iFIFO) 5549 5549 { 5550 5550 /* Make sure it's still 32-bit memory. Ignore fluxtuations in the prefetch flag */ … … 5575 5575 else if (iRegion == UINT32_MAX) 5576 5576 { 5577 int rc = vgaR3PciRegionLoadChangeHook(pDevIns, pPciDev, 2, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM, NULL);5577 int rc = vgaR3PciRegionLoadChangeHook(pDevIns, pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM, NULL); 5578 5578 if (RT_SUCCESS(rc)) 5579 rc = pfnOldSetter(pPciDev, 2, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM);5579 rc = pfnOldSetter(pPciDev, pThis->pciRegions.iFIFO, VMSVGA_FIFO_SIZE_OLD, PCI_ADDRESS_SPACE_MEM); 5580 5580 return rc; 5581 5581 } … … 6190 6190 "VMSVGAEnabled\0" 6191 6191 "VMSVGAPciId\0" 6192 "VMSVGAPciBarLayout\0" 6192 6193 "VMSVGAFifoSize\0" 6193 6194 #endif … … 6239 6240 Log(("VMSVGA: VMSVGAPciId = %d\n", pThis->fVMSVGAPciId)); 6240 6241 6242 rc = CFGMR3QueryBoolDef(pCfg, "VMSVGAPciBarLayout", &pThis->fVMSVGAPciBarLayout, false); 6243 AssertLogRelRCReturn(rc, rc); 6244 Log(("VMSVGA: VMSVGAPciBarLayout = %d\n", pThis->fVMSVGAPciBarLayout)); 6245 6241 6246 rc = CFGMR3QueryU32Def(pCfg, "VMSVGAFifoSize", &pThis->svga.cbFIFO, VMSVGA_FIFO_SIZE); 6242 6247 AssertLogRelRCReturn(rc, rc); … … 6251 6256 AssertLogRelRCReturn(rc, rc); 6252 6257 Log(("VMSVGA: VMSVGA3dEnabled = %d\n", pThis->svga.f3DEnabled)); 6258 #endif 6259 6260 6261 #ifdef VBOX_WITH_VMSVGA 6262 if (pThis->fVMSVGAPciBarLayout) 6263 { 6264 pThis->pciRegions.iIO = 0; 6265 pThis->pciRegions.iVRAM = 1; 6266 pThis->pciRegions.iFIFO = 2; 6267 } 6268 else 6269 { 6270 pThis->pciRegions.iVRAM = 0; 6271 pThis->pciRegions.iIO = 1; 6272 pThis->pciRegions.iFIFO = 2; 6273 } 6274 #else 6275 pThis->pciRegions.iVRAM = 0; 6253 6276 #endif 6254 6277 … … 6360 6383 { 6361 6384 /* Register the io command ports. */ 6362 rc = PDMDevHlpPCIIORegionRegister (pDevIns, 0 /* iRegion */, 0x10, PCI_ADDRESS_SPACE_IO, vmsvgaR3IORegionMap);6385 rc = PDMDevHlpPCIIORegionRegister (pDevIns, pThis->pciRegions.iIO, 0x10, PCI_ADDRESS_SPACE_IO, vmsvgaR3IORegionMap); 6363 6386 if (RT_FAILURE (rc)) 6364 6387 return rc; 6365 6388 /* VMware's MetalKit doesn't like PCI_ADDRESS_SPACE_MEM_PREFETCH */ 6366 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 1 /* iRegion */, pThis->vram_size,6389 rc = PDMDevHlpPCIIORegionRegister(pDevIns, pThis->pciRegions.iVRAM, pThis->vram_size, 6367 6390 PCI_ADDRESS_SPACE_MEM /* PCI_ADDRESS_SPACE_MEM_PREFETCH */, vgaR3IORegionMap); 6368 6391 if (RT_FAILURE(rc)) 6369 6392 return rc; 6370 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 2 /* iRegion */, pThis->svga.cbFIFO,6393 rc = PDMDevHlpPCIIORegionRegister(pDevIns, pThis->pciRegions.iFIFO, pThis->svga.cbFIFO, 6371 6394 PCI_ADDRESS_SPACE_MEM /* PCI_ADDRESS_SPACE_MEM_PREFETCH */, vmsvgaR3IORegionMap); 6372 6395 if (RT_FAILURE(rc)) … … 6377 6400 #endif /* VBOX_WITH_VMSVGA */ 6378 6401 { 6379 #ifdef VBOX_WITH_VMSVGA 6380 int iPCIRegionVRAM = (pThis->fVMSVGAEnabled) ? 1 : 0; 6381 #else 6382 int iPCIRegionVRAM = 0; 6383 #endif 6384 rc = PDMDevHlpPCIIORegionRegister(pDevIns, iPCIRegionVRAM, pThis->vram_size, 6402 rc = PDMDevHlpPCIIORegionRegister(pDevIns, pThis->pciRegions.iVRAM, pThis->vram_size, 6385 6403 PCI_ADDRESS_SPACE_MEM_PREFETCH, vgaR3IORegionMap); 6386 6404 if (RT_FAILURE(rc)) … … 6392 6410 */ 6393 6411 #ifdef VBOX_WITH_VMSVGA 6394 int iPCIRegionVRAM = (pThis->fVMSVGAEnabled) ? 1 : 0;6395 6396 6412 if (pThis->fVMSVGAEnabled) 6397 6413 { … … 6399 6415 * Allocate and initialize the FIFO MMIO2 memory. 6400 6416 */ 6401 rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->Dev, 2 /*iRegion*/, pThis->svga.cbFIFO,6417 rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->Dev, pThis->pciRegions.iFIFO, pThis->svga.cbFIFO, 6402 6418 0 /*fFlags*/, (void **)&pThis->svga.pFIFOR3, "VMSVGA-FIFO"); 6403 6419 if (RT_FAILURE(rc)) … … 6406 6422 pThis->svga.pFIFOR0 = (RTR0PTR)pThis->svga.pFIFOR3; 6407 6423 } 6408 #else 6409 int iPCIRegionVRAM = 0; 6410 #endif 6411 rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->Dev, iPCIRegionVRAM, pThis->vram_size, 0, (void **)&pThis->vram_ptrR3, "VRam"); 6424 #endif 6425 rc = PDMDevHlpMMIO2Register(pDevIns, &pThis->Dev, pThis->pciRegions.iVRAM, pThis->vram_size, 0, (void **)&pThis->vram_ptrR3, "VRam"); 6412 6426 AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMMIO2Register(%#x,) -> %Rrc\n", pThis->vram_size, rc), rc); 6413 6427 pThis->vram_ptrR0 = (RTR0PTR)pThis->vram_ptrR3; /** @todo @bugref{1865} Map parts into R0 or just use PGM access (Mac only). */ … … 6416 6430 { 6417 6431 RTRCPTR pRCMapping = 0; 6418 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, &pThis->Dev, iPCIRegionVRAM, 0 /* off */, VGA_MAPPING_SIZE,6432 rc = PDMDevHlpMMHyperMapMMIO2(pDevIns, &pThis->Dev, pThis->pciRegions.iVRAM, 0 /* off */, VGA_MAPPING_SIZE, 6419 6433 "VGA VRam", &pRCMapping); 6420 6434 AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMMHyperMapMMIO2(%#x,) -> %Rrc\n", VGA_MAPPING_SIZE, rc), rc); … … 6436 6450 { 6437 6451 RTR0PTR pR0Mapping = 0; 6438 rc = PDMDevHlpMMIO2MapKernel(pDevIns, 2 /* iRegion */, 0 /* off */, pThis->svga.cbFIFO, "VMSVGA-FIFO", &pR0Mapping);6452 rc = PDMDevHlpMMIO2MapKernel(pDevIns, pThis->pciRegions.iFIFO, 0 /* off */, pThis->svga.cbFIFO, "VMSVGA-FIFO", &pR0Mapping); 6439 6453 AssertLogRelMsgRCReturn(rc, ("PDMDevHlpMapMMIO2IntoR0(%#x,) -> %Rrc\n", pThis->svga.cbFIFO, rc), rc); 6440 6454 pThis->svga.pFIFOR0 = pR0Mapping; -
trunk/src/VBox/Devices/Graphics/DevVGA.h
r76565 r76985 350 350 bool fVMSVGAEnabled; 351 351 bool fVMSVGAPciId; 352 bool Padding4[0+3]; 352 bool fVMSVGAPciBarLayout; 353 bool Padding4[0+2]; 353 354 # else 354 355 bool Padding4[1+4]; 355 356 # endif 357 358 struct { 359 uint32_t u32Padding1; 360 uint32_t iVRAM; 361 # ifdef VBOX_WITH_VMSVGA 362 uint32_t iIO; 363 uint32_t iFIFO; 364 # endif 365 } pciRegions; 356 366 357 367 /** Physical access type for the linear frame buffer dirty page tracking. */
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