- Timestamp:
- Apr 2, 2008 3:04:09 PM (17 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Devices/Network/DevPCNet.cpp
r7693 r7701 2694 2694 else 2695 2695 pData->GCRDRA = (pData->GCRDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); 2696 Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, 2697 u32RAP, val, pData->GCRDRA)); 2696 Log(("#%d: WRITE CSR%d, %#06x => GCRDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pData->GCRDRA)); 2698 2697 break; 2699 2698 … … 2713 2712 else 2714 2713 pData->GCTDRA = (pData->GCTDRA & 0x0000ffff) | ((val & 0x0000ffff) << 16); 2715 Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, 2716 u32RAP, val, pData->GCTDRA)); 2714 Log(("#%d: WRITE CSR%d, %#06x => GCTDRA=%08x (alt init)\n", PCNET_INST_NR, u32RAP, val, pData->GCTDRA)); 2717 2715 break; 2718 2716 … … 2794 2792 } 2795 2793 #ifdef PCNET_DEBUG_CSR 2796 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, 2797 u32RAP, val)); 2794 Log(("#%d pcnetCSRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val)); 2798 2795 #endif 2799 2796 return val; … … 2805 2802 u32RAP &= 0x7f; 2806 2803 #ifdef PCNET_DEBUG_BCR 2807 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, 2808 u32RAP, val)); 2804 Log2(("#%d pcnetBCRWriteU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val)); 2809 2805 #endif 2810 2806 switch (u32RAP) … … 2863 2859 pData->aMII[pData->aBCR[BCR_MIIADDR] & 0x1f] = val; 2864 2860 #ifdef PCNET_DEBUG_MII 2865 Log(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, 2866 pData->aBCR[BCR_MIIADDR] & 0x1f, val)); 2861 Log(("#%d pcnet: mii write %d <- %#x\n", PCNET_INST_NR, pData->aBCR[BCR_MIIADDR] & 0x1f, val)); 2867 2862 #endif 2868 2863 break; … … 2983 2978 2984 2979 #ifdef PCNET_DEBUG_MII 2985 Log(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, 2986 miiaddr, val)); 2980 Log(("#%d pcnet: mii read %d -> %#x\n", PCNET_INST_NR, miiaddr, val)); 2987 2981 #endif 2988 2982 return val; … … 3025 3019 } 3026 3020 #ifdef PCNET_DEBUG_BCR 3027 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, 3028 u32RAP, val)); 3021 Log2(("#%d pcnetBCRReadU16: rap=%d val=%#06x\n", PCNET_INST_NR, u32RAP, val)); 3029 3022 #endif 3030 3023 return val; … … 3077 3070 addr &= 0x0f; 3078 3071 val &= 0xff; 3079 Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3080 addr, val)); 3072 Log(("#%d pcnetAPROMWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val)); 3081 3073 /* Check APROMWE bit to enable write access */ 3082 3074 if (pcnetBCRReadU16(pData, 2) & 0x80) … … 3087 3079 { 3088 3080 uint32_t val = pData->aPROM[addr &= 0x0f]; 3089 Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3090 addr, val)); 3081 Log(("#%d pcnetAPROMReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val)); 3091 3082 return val; 3092 3083 } … … 3244 3235 skip_update_irq: 3245 3236 #ifdef PCNET_DEBUG_IO 3246 Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3247 addr, val)); 3237 Log2(("#%d pcnetIoportReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val)); 3248 3238 #endif 3249 3239 return val; … … 3253 3243 { 3254 3244 #ifdef PCNET_DEBUG_IO 3255 Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3256 addr, val)); 3245 Log2(("#%d pcnetMMIOWriteU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val)); 3257 3246 #endif 3258 3247 if (!(addr & 0x10)) … … 3266 3255 val = pcnetAPROMReadU8(pData, addr); 3267 3256 #ifdef PCNET_DEBUG_IO 3268 Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, 3269 addr, val & 0xff)); 3257 Log2(("#%d pcnetMMIOReadU8: addr=%#010x val=%#04x\n", PCNET_INST_NR, addr, val & 0xff)); 3270 3258 #endif 3271 3259 return val; … … 3275 3263 { 3276 3264 #ifdef PCNET_DEBUG_IO 3277 Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, 3278 addr, val)); 3265 Log2(("#%d pcnetMMIOWriteU16: addr=%#010x val=%#06x\n", PCNET_INST_NR, addr, val)); 3279 3266 #endif 3280 3267 if (addr & 0x10) … … 3301 3288 } 3302 3289 #ifdef PCNET_DEBUG_IO 3303 Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, 3304 addr, val & 0xffff)); 3290 Log2(("#%d pcnetMMIOReadU16: addr=%#010x val = %#06x\n", PCNET_INST_NR, addr, val & 0xffff)); 3305 3291 #endif 3306 3292 return val; … … 3310 3296 { 3311 3297 #ifdef PCNET_DEBUG_IO 3312 Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3313 addr, val)); 3298 Log2(("#%d pcnetMMIOWriteU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val)); 3314 3299 #endif 3315 3300 if (addr & 0x10) … … 3342 3327 } 3343 3328 #ifdef PCNET_DEBUG_IO 3344 Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, 3345 addr, val)); 3329 Log2(("#%d pcnetMMIOReadU32: addr=%#010x val=%#010x\n", PCNET_INST_NR, addr, val)); 3346 3330 #endif 3347 3331 return val; … … 3390 3374 } 3391 3375 STAM_PROFILE_ADV_STOP(&pData->StatAPROMRead, a); 3392 LogFlow(("#%d pcnetIOPortAPromRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", 3393 PCNET_INST_NR, Port, *pu32, cb, rc)); 3376 LogFlow(("#%d pcnetIOPortAPromRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, *pu32, cb, rc)); 3394 3377 return rc; 3395 3378 } … … 3429 3412 rc = VINF_SUCCESS; 3430 3413 } 3431 LogFlow(("#%d pcnetIOPortAPromWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", 3432 PCNET_INST_NR, Port, u32, cb, rc)); 3414 LogFlow(("#%d pcnetIOPortAPromWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, u32, cb, rc)); 3433 3415 #ifdef LOG_ENABLED 3434 3416 if (rc == VINF_IOM_HC_IOPORT_WRITE) … … 3471 3453 } 3472 3454 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIORead), a); 3473 LogFlow(("#%d pcnetIOPortRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", 3474 PCNET_INST_NR, Port, *pu32, cb, rc)); 3455 Log2(("#%d pcnetIOPortRead: Port=%RTiop *pu32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, *pu32, cb, rc)); 3475 3456 #ifdef LOG_ENABLED 3476 3457 if (rc == VINF_IOM_HC_IOPORT_READ) … … 3514 3495 } 3515 3496 STAM_PROFILE_ADV_STOP(&pData->CTXSUFF(StatIOWrite), a); 3516 LogFlow(("#%d pcnetIOPortWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", 3517 PCNET_INST_NR, Port, u32, cb, rc)); 3497 Log2(("#%d pcnetIOPortWrite: Port=%RTiop u32=%#RX32 cb=%d rc=%Vrc\n", PCNET_INST_NR, Port, u32, cb, rc)); 3518 3498 #ifdef LOG_ENABLED 3519 3499 if (rc == VINF_IOM_HC_IOPORT_WRITE)
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