Changeset 77569 in vbox

Timestamp:

Mar 6, 2019 8:18:51 AM (6 years ago)

Author:

vboxsync

Message:

VMM/IEM: Nested VMX: bugref:9180 On-demand importing of externally kept guest-CPU state for VM-exits and tightening of importing externally kept guest-CPU state on VMLAUNCH/VMRESUME.

Location:

trunk

Files:

• include/VBox/vmm/iem.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAll.cpp (modified) (10 diffs)
• src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h (modified) (11 diffs)

trunk/include/VBox/vmm/iem.h

@@ -225 +225 @@
 
 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX
-/** @todo NSTVMX: Refine this mask later (probably some MSRs are not required). */
-# define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK         CPUMCTX_EXTRN_ABSOLUTELY_ALL
-# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK        IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK
+# define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK        (  IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \
+                                                    | CPUMCTX_EXTRN_HWVIRT )
 #endif
 

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -15746 +15746 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPU pVCpu, uint32_t idMsr, uint64_t *pu64Value, bool fWrite)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
     Assert(pu64Value);
 
@@ -15780 +15779 @@
                                                        bool fWrite)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     Assert(pvData);
 
@@ -15804 +15802 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPU pVCpu)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
-
     VBOXSTRICTRC rcStrict = iemVmxApicWriteEmulation(pVCpu);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15822 +15818 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPU pVCpu)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitPreemptTimer(pVCpu);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15843 +15838 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPU pVCpu, uint8_t uVector, bool fIntPending)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitExtInt(pVCpu, uVector, fIntPending);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15861 +15855 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPU pVCpu, uint8_t uVector)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitStartupIpi(pVCpu, uVector);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15878 +15871 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInitIpi(PVMCPU pVCpu)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitInitIpi(pVCpu);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15895 +15887 @@
 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitIntWindow(PVMCPU pVCpu)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitIntWindow(pVCpu);
     if (pVCpu->iem.s.cActiveMappings)
@@ -15912 +15903 @@
 VMM_INT_DECL(VBOXSTRICTRC)  IEMExecVmxVmexitMtf(PVMCPU pVCpu)
 {
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
     VBOXSTRICTRC rcStrict = iemVmxVmexitMtf(pVCpu);
     if (pVCpu->iem.s.cActiveMappings)
@@ -16099 +16089 @@
 
     iemInitExec(pVCpu, false /*fBypassHandlers*/);
-    VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr,  uInstrId);
+    VBOXSTRICTRC rcStrict = iemVmxVmlaunchVmresume(pVCpu, cbInstr, uInstrId);
     if (pVCpu->iem.s.cActiveMappings)
         iemMemRollback(pVCpu);

trunk/src/VBox/VMM/VMMAll/IEMAllCImplVmxInstr.cpp.h

@@ -1668 +1668 @@
      *    NewPt  = 2 - 2 = 0
      */
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
     uint64_t const uCurTick        = TMCpuTickGetNoCheck(pVCpu);
     uint64_t const uVmentryTick    = pVCpu->cpum.GstCtx.hwvirt.vmx.uVmentryTick;
@@ -1847 +1848 @@
          * See Intel spec. 24.4.2 "Guest Non-Register State".
          */
+        IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
         uint64_t       fPendingDbgMask = pVCpu->cpum.GstCtx.dr[6];
         uint64_t const fBpHitMask = VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP0 | VMX_VMCS_GUEST_PENDING_DEBUG_XCPT_BP1
@@ -2768 +2770 @@
     return VINF_EM_RAW_EMULATE_INSTR;
 # else
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK);
+    IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4       /* Control registers */
+                            | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6                           /* Debug registers */
+                            | CPUMCTX_EXTRN_EFER                                              /* MSRs */
+                            | CPUMCTX_EXTRN_SYSENTER_MSRS
+                            | CPUMCTX_EXTRN_OTHER_MSRS    /* PAT */
+                            | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS    /* GPRs */
+                            | CPUMCTX_EXTRN_SREG_MASK                                         /* Segment registers */
+                            | CPUMCTX_EXTRN_TR                                                /* Task register */
+                            | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR    /* Table registers */
+                            | CPUMCTX_EXTRN_HWVIRT);                                          /* Hardware virtualization state */
 
     PVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
@@ -3789 +3800 @@
     Assert(pVmcs);
 
-    /* Check if the guest has enabled VMX-preemption timers in the first place. */
+    /* The VM-exit is subject to "Activate VMX-preemption timer" being set. */
     if (pVmcs->u32PinCtls & VMX_PIN_CTLS_PREEMPT_TIMER)
     {
+        /* Import the hardware virtualization state (for nested-guest VM-entry TSC-tick). */
+        IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
+
         /*
          * Calculate the current VMX-preemption timer value.
@@ -3832 +3846 @@
     Assert(fIntPending || uVector == 0);
 
-    /* The VM-exit is subject to "External interrupt exiting" is being set. */
+    /** @todo NSTVMX: r=ramshankar: Consider standardizing check basic/blanket
+     *        intercepts for VM-exits. Right now it is not clear which iemVmxVmexitXXX()
+     *        functions require prior checking of a blanket intercept and which don't.
+     *        It is better for the caller to check a blanket intercept performance wise
+     *        than making a function call. Leaving this as a todo because it is more
+     *        a performance issue. */
+
+    /* The VM-exit is subject to "External interrupt exiting" being set. */
     if (pVmcs->u32PinCtls & VMX_PIN_CTLS_EXT_INT_EXIT)
     {
@@ -4067 +4088 @@
             else if (uVector == X86_XCPT_DB)
             {
-                IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR6);
+                IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
                 uExitQual = pVCpu->cpum.GstCtx.dr[6] & VMX_VMCS_EXIT_QUAL_VALID_MASK;
             }
@@ -4220 +4241 @@
 DECLINLINE(uint16_t) iemVmxVirtApicClearPendingWrite(PVMCPU pVCpu)
 {
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_HWVIRT);
     uint8_t const offVirtApicWrite = pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite;
     pVCpu->cpum.GstCtx.hwvirt.vmx.offVirtApicWrite = 0;
@@ -4992 +5014 @@
     Assert(pVmcs);
 
+    /* Import the virtual-APIC write offset (part of the hardware-virtualization state). */
+    IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_HWVIRT);
+
     /*
      * Perform APIC-write emulation based on the virtual-APIC register written.
@@ -5656 +5681 @@
  * @param   pszInstr        The VMX instruction name (for logging purposes).
  */
-IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu,  const char *pszInstr)
+IEM_STATIC int iemVmxVmentryCheckGuestRipRFlags(PVMCPU pVCpu, const char *pszInstr)
 {
     /*
@@ -6763 +6788 @@
      */
     PCVMXVVMCS pVmcs = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
+
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
     uint64_t const uGstCr0 = (pVmcs->u64GuestCr0.u   & ~VMX_ENTRY_CR0_IGNORE_MASK)
                            | (pVCpu->cpum.GstCtx.cr0 &  VMX_ENTRY_CR0_IGNORE_MASK);
@@ -6783 +6810 @@
         if (!(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_LOAD_EFER_MSR))
         {
-            bool const fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
-            bool const fGstPaging     = RT_BOOL(uGstCr0 & X86_CR0_PG);
-            uint64_t const uHostEfer  = pVCpu->cpum.GstCtx.msrEFER;
+            IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_EFER);
+            uint64_t const uHostEfer      = pVCpu->cpum.GstCtx.msrEFER;
+            bool const     fGstInLongMode = RT_BOOL(pVmcs->u32EntryCtls & VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
+            bool const     fGstPaging     = RT_BOOL(uGstCr0 & X86_CR0_PG);
             if (fGstInLongMode)
             {