Changeset 77662 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg

Timestamp:

Mar 12, 2019 12:40:12 PM (6 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

129295

Message:

EFI: First step in UDK2018 merge. Does not build yet.

Location:

trunk/src/VBox/Devices/EFI/FirmwareNew

Files:

• . (modified) (1 prop)
• IntelFspWrapperPkg/Contributions.txt (deleted)
• IntelFspWrapperPkg/FspInitPei/FindPeiCore.c (modified) (1 diff)
• IntelFspWrapperPkg/FspInitPei/SecMain.c (modified) (1 diff)
• IntelFspWrapperPkg/FspInitPei/SecMain.h (modified) (2 diffs)
• IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c (modified) (2 diffs)
• IntelFspWrapperPkg/FspWrapperSecCore/FindPeiCore.c (modified) (1 diff)
• IntelFspWrapperPkg/FspWrapperSecCore/SecMain.c (modified) (1 diff)
• IntelFspWrapperPkg/FspWrapperSecCore/SecMain.h (modified) (2 diffs)
• IntelFspWrapperPkg/IntelFspWrapperPkg.dsc (modified) (3 diffs)
• IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c (modified) (6 diffs)
• IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c (modified) (1 diff)
• IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c (modified) (8 diffs)
• IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/PeiFspHobProcessLibSample.inf (modified) (1 diff)
• IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/SecEntry.S (modified) (2 diffs)
• IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/SecEntry.asm (modified) (1 diff)
• IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecTempRamSupport.c (modified) (1 diff)

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspInitPei/FindPeiCore.c

@@ -147 +147 @@
   Find and return Pei Core entry point.
 
-  It also find SEC and PEI Core file debug inforamtion. It will report them if
+  It also find SEC and PEI Core file debug information. It will report them if
   remote debug is enabled.
 

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspInitPei/SecMain.c

@@ -62 +62 @@
 
   @param[in] SizeOfRam           Size of the temporary memory available for use.
-  @param[in] TempRamBase         Base address of tempory ram
+  @param[in] TempRamBase         Base address of temporary ram
   @param[in] BootFirmwareVolume  Base address of the Boot Firmware Volume.
 **/

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspInitPei/SecMain.h

@@ -55 +55 @@
 
   @param[in] SizeOfRam           Size of the temporary memory available for use.
-  @param[in] TempRamBase         Base address of tempory ram
+  @param[in] TempRamBase         Base address of temporary ram
   @param[in] BootFirmwareVolume  Base address of the Boot Firmware Volume.
 **/
@@ -69 +69 @@
   Find and return Pei Core entry point.
 
-  It also find SEC and PEI Core file debug inforamtion. It will report them if
+  It also find SEC and PEI Core file debug information. It will report them if
   remote debug is enabled.
 

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspNotifyDxe/LoadBelow4G.c

@@ -1 +1 @@
 /** @file
 
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2015 - 2017, Intel Corporation. All rights reserved.<BR>
 
 This program and the accompanying materials
@@ -113 +113 @@
   ImageContext.ImageAddress = (PHYSICAL_ADDRESS)(UINTN)FfsBuffer;
   //
-  // Align buffer on section boundry
+  // Align buffer on section boundary
   //
   ImageContext.ImageAddress += ImageContext.SectionAlignment - 1;
-  ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)(ImageContext.SectionAlignment - 1));
+  ImageContext.ImageAddress &= ~((EFI_PHYSICAL_ADDRESS)ImageContext.SectionAlignment - 1);
   //
   // Load the image to our new buffer

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspWrapperSecCore/FindPeiCore.c

@@ -147 +147 @@
   Find and return Pei Core entry point.
 
-  It also find SEC and PEI Core file debug inforamtion. It will report them if
+  It also find SEC and PEI Core file debug information. It will report them if
   remote debug is enabled.
 

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspWrapperSecCore/SecMain.c

@@ -53 +53 @@
 
   @param[in] SizeOfRam           Size of the temporary memory available for use.
-  @param[in] TempRamBase         Base address of tempory ram
+  @param[in] TempRamBase         Base address of temporary ram
   @param[in] BootFirmwareVolume  Base address of the Boot Firmware Volume.
 **/

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/FspWrapperSecCore/SecMain.h

@@ -54 +54 @@
 
   @param[in] SizeOfRam           Size of the temporary memory available for use.
-  @param[in] TempRamBase         Base address of tempory ram
+  @param[in] TempRamBase         Base address of temporary ram
   @param[in] BootFirmwareVolume  Base address of the Boot Firmware Volume.
 **/
@@ -68 +68 @@
   Find and return Pei Core entry point.
 
-  It also find SEC and PEI Core file debug inforamtion. It will report them if
+  It also find SEC and PEI Core file debug information. It will report them if
   remote debug is enabled.
 

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/IntelFspWrapperPkg.dsc

@@ -2 +2 @@
 # Provides drivers and definitions to support fsp in EDKII bios.
 #
-# Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
 # This program and the accompanying materials are licensed and made available under
 # the terms and conditions of the BSD License that accompanies this distribution.
@@ -20 +20 @@
   OUTPUT_DIRECTORY               = Build/IntelFspWrapperPkg
   SUPPORTED_ARCHITECTURES        = IA32|X64
-  BUILD_TARGETS                  = DEBUG|RELEASE
+  BUILD_TARGETS                  = DEBUG|RELEASE|NOOPT
   SKUID_IDENTIFIER               = DEFAULT
 
@@ -84 +84 @@
   gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80080046
   gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+
+[BuildOptions]
+  *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/BaseFspApiLib/FspApiLib.c

@@ -2 +2 @@
   Provide FSP API related function.
 
-  Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -99 +99 @@
   BOOLEAN             InterruptState;
 
-  FspInitApi = (FSP_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspInitEntryOffset);
+  FspInitApi = (FSP_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspInitEntryOffset);
   InterruptState = SaveAndDisableInterrupts ();
   Status = Execute32BitCode ((UINTN)FspInitApi, (UINTN)FspInitParams);
@@ -126 +126 @@
   BOOLEAN             InterruptState;
 
-  NotifyPhaseApi = (FSP_NOTIFY_PHASE)(UINTN)(FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);
+  NotifyPhaseApi = (FSP_NOTIFY_PHASE)((UINTN)FspHeader->ImageBase + FspHeader->NotifyPhaseEntryOffset);
   InterruptState = SaveAndDisableInterrupts ();
   Status = Execute32BitCode ((UINTN)NotifyPhaseApi, (UINTN)NotifyPhaseParams);
@@ -153 +153 @@
   BOOLEAN             InterruptState;
 
-  FspMemoryInitApi = (FSP_MEMORY_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);
+  FspMemoryInitApi = (FSP_MEMORY_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspMemoryInitEntryOffset);
   InterruptState = SaveAndDisableInterrupts ();
   Status = Execute32BitCode ((UINTN)FspMemoryInitApi, (UINTN)FspMemoryInitParams);
@@ -180 +180 @@
   BOOLEAN             InterruptState;
 
-  TempRamExitApi = (FSP_TEMP_RAM_EXIT)(UINTN)(FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);
+  TempRamExitApi = (FSP_TEMP_RAM_EXIT)((UINTN)FspHeader->ImageBase + FspHeader->TempRamExitEntryOffset);
   InterruptState = SaveAndDisableInterrupts ();
   Status = Execute32BitCode ((UINTN)TempRamExitApi, (UINTN)TempRamExitParam);
@@ -207 +207 @@
   BOOLEAN             InterruptState;
 
-  FspSiliconInitApi = (FSP_SILICON_INIT)(UINTN)(FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);
+  FspSiliconInitApi = (FSP_SILICON_INIT)((UINTN)FspHeader->ImageBase + FspHeader->FspSiliconInitEntryOffset);
   InterruptState = SaveAndDisableInterrupts ();
   Status = Execute32BitCode ((UINTN)FspSiliconInitApi, (UINTN)FspSiliconInitParam);

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/BaseFspApiLib/X64/DispatchExecute.c

@@ -90 +90 @@
   )
 {
-  return AsmExecute32BitCode (Function, Param1, 0, &mGdt);
+  EFI_STATUS       Status;
+  IA32_DESCRIPTOR  Idtr;
+
+  //
+  // Idtr might be changed inside of FSP. 32bit FSP only knows the <4G address.
+  // If IDTR.Base is >4G, FSP can not handle. So we need save/restore IDTR here for X64 only.
+  // Interrupt is already disabled here, so it is safety to update IDTR.
+  //
+  AsmReadIdtr (&Idtr);
+  Status = AsmExecute32BitCode (Function, Param1, 0, &mGdt);
+  AsmWriteIdtr (&Idtr);
+
+  return Status;
 }
 

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/FspHobProcessLibSample.c

@@ -26 +26 @@
 #include <Guid/GuidHobFspEas.h>
 #include <Guid/MemoryTypeInformation.h>
+#include <Guid/PcdDataBaseHobGuid.h>
 #include <Ppi/Capsule.h>
 
@@ -46 +47 @@
   )
 {
-  EFI_STATUS                  Status;
   EFI_PEI_HOB_POINTERS        Hob;
   EFI_MEMORY_TYPE_INFORMATION *MemoryData;
@@ -53 +53 @@
 
   MemoryData = NULL;
-  Status     = (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES**)PeiServices, (VOID **) &Hob.Raw);
+  (*PeiServices)->GetHobList ((CONST EFI_PEI_SERVICES**)PeiServices, (VOID **) &Hob.Raw);
   while (!END_OF_HOB_LIST (Hob)) {
     if (Hob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION &&
@@ -156 +156 @@
   EFI_STATUS           Status;
   EFI_BOOT_MODE        BootMode;
-  PEI_CAPSULE_PPI      *Capsule;
+  EFI_PEI_CAPSULE_PPI  *Capsule;
   VOID                 *CapsuleBuffer;
   UINTN                CapsuleBufferLength;
@@ -247 +247 @@
     S3PeiMemBase = 0;
     S3PeiMemSize = 0;
-    Status = GetS3MemoryInfo (&S3PeiMemBase, &S3PeiMemSize);
+    Status = GetS3MemoryInfo (&S3PeiMemSize, &S3PeiMemBase);
     ASSERT_EFI_ERROR (Status);
     DEBUG((DEBUG_INFO, "S3 memory %Xh - %Xh bytes\n", S3PeiMemBase, S3PeiMemSize));
@@ -272 +272 @@
     if (BootMode == BOOT_ON_FLASH_UPDATE) {
       Status = PeiServicesLocatePpi (
-                 &gPeiCapsulePpiGuid,
+                 &gEfiPeiCapsulePpiGuid,
                  0,
                  NULL,
@@ -336 +336 @@
 
 /**
+  Process FSP HOB list
+
+  @param[in] FspHobList  Pointer to the HOB data structure produced by FSP.
+
+**/
+VOID
+ProcessFspHobList (
+  IN VOID                 *FspHobList
+  )
+{
+  EFI_PEI_HOB_POINTERS  FspHob;
+
+  FspHob.Raw = FspHobList;
+
+  //
+  // Add all the HOBs from FSP binary to FSP wrapper
+  //
+  while (!END_OF_HOB_LIST (FspHob)) {
+    if (FspHob.Header->HobType == EFI_HOB_TYPE_GUID_EXTENSION) {
+      //
+      // Skip FSP binary creates PcdDataBaseHobGuid
+      //
+      if (!CompareGuid(&FspHob.Guid->Name, &gPcdDataBaseHobGuid)) {
+        BuildGuidDataHob (
+          &FspHob.Guid->Name,
+          GET_GUID_HOB_DATA(FspHob),
+          GET_GUID_HOB_DATA_SIZE(FspHob)
+        );
+      }
+    }
+    FspHob.Raw = GET_NEXT_HOB (FspHob);
+  }
+}
+
+/**
   BIOS process FspBobList for other data (not Memory Resource Descriptor).
 
@@ -348 +383 @@
   )
 {
+  ProcessFspHobList (FspHobList);
+
   return EFI_SUCCESS;
 }

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/PeiFspHobProcessLibSample/PeiFspHobProcessLibSample.inf

@@ -71 +71 @@
   gFspReservedMemoryResourceHobGuid                       ## CONSUMES ## HOB
   gEfiMemoryTypeInformationGuid                           ## CONSUMES ## GUID
+  gPcdDataBaseHobGuid                                     ## CONSUMES ## HOB
 
 [Ppis]
-  gPeiCapsulePpiGuid                                      ## CONSUMES
+  gEfiPeiCapsulePpiGuid                                   ## CONSUMES

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/SecEntry.S

@@ -211 +211 @@
 
 TempRamInitDone:
+  cmp  $0x8000000E, %eax   #Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
+  je   CallSecFspInit      #If microcode not found, don't hang, but continue.
+
   cmp  $0x0, %eax
   jnz  FspApiFailed
@@ -216 +219 @@
   #   ECX: start of range
   #   EDX: end of range
+CallSecFspInit:
+  xorl    %eax, %eax
   movl    %edx, %esp
+
+  # Align the stack at DWORD
+  addl  $3, %esp
+  andl  $0xFFFFFFFC, %esp
+
   pushl   %edx
   pushl   %ecx

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/Ia32/SecEntry.asm

@@ -221 +221 @@
 
 TempRamInitDone:
-  cmp eax, 0
+  cmp eax, 8000000Eh      ;Check if EFI_NOT_FOUND returned. Error code for Microcode Update not found.
+  je  CallSecFspInit      ;If microcode not found, don't hang, but continue.
+
+  cmp eax, 0              ;Check if EFI_SUCCESS retuned.
   jnz FspApiFailed
 
   ;   ECX: start of range
   ;   EDX: end of range
+CallSecFspInit:
+  xor     eax, eax
   mov     esp, edx
+
+  ; Align the stack at DWORD
+  add  esp,  3
+  and  esp, 0FFFFFFFCh
+
   push    edx
   push    ecx

trunk/src/VBox/Devices/EFI/FirmwareNew/IntelFspWrapperPkg/Library/SecPeiFspPlatformSecLibSample/SecTempRamSupport.c

@@ -140 +140 @@
   //
   // SecSwitchStack function must be invoked after the memory migration
-  // immediatly, also we need fixup the stack change caused by new call into
-  // permenent memory.
+  // immediately, also we need fixup the stack change caused by new call into
+  // permanent memory.
   //
   SecSwitchStack (