Changeset 77662 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Library/BaseCacheMaintenanceLib

Timestamp:

Mar 12, 2019 12:40:12 PM (6 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

129295

Message:

EFI: First step in UDK2018 merge. Does not build yet.

Location:

trunk/src/VBox/Devices/EFI/FirmwareNew

Files:

• . (modified) (1 prop)
• MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf (modified) (2 diffs)
• MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni (modified) (1 diff)
• MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c (modified) (4 diffs)

trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf

@@ -5 +5 @@
 #  This library assumes there are no chipset dependencies required to maintain caches.
 #
-#  Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2007 - 2015, Intel Corporation. All rights reserved.<BR>
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
 #
@@ -24 +24 @@
   FILE_GUID                      = 123dd843-57c9-4158-8418-ce68b3944ce7
   MODULE_TYPE                    = BASE
-  VERSION_STRING                 = 1.0
+  VERSION_STRING                 = 1.1
   LIBRARY_CLASS                  = CacheMaintenanceLib
 

trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.uni

@@ -1 @@
-// /** @file
+// /** @file
 // Instance of Cache Maintenance Library using Base Library services.
 //

trunk/src/VBox/Devices/EFI/FirmwareNew/MdePkg/Library/BaseCacheMaintenanceLib/X86Cache.c

@@ -2 +2 @@
   Cache Maintenance Functions.
 
-  Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -17 +17 @@
 #include <Library/BaseLib.h>
 #include <Library/DebugLib.h>
-
-//
-// This size must be at or below the smallest cache size possible among all
-// supported processors
-//
-#define CACHE_LINE_SIZE             0x20
 
 /**
@@ -129 +123 @@
   )
 {
+  UINT32                            RegEbx;
+  UINT32                            RegEdx;
+  UINTN                             CacheLineSize;
   UINTN                             Start;
   UINTN                             End;
@@ -138 +135 @@
   ASSERT ((Length - 1) <= (MAX_ADDRESS - (UINTN)Address));
 
+  //
+  // If the CPU does not support CLFLUSH instruction,
+  // then promote flush range to flush entire cache.
+  //
+  AsmCpuid (0x01, NULL, &RegEbx, NULL, &RegEdx);
+  if ((RegEdx & BIT19) == 0) {
+    AsmWbinvd ();
+    return Address;
+  }
+
+  //
+  // Cache line size is 8 * Bits 15-08 of EBX returned from CPUID 01H
+  //
+  CacheLineSize = (RegEbx & 0xff00) >> 5;
+
   Start = (UINTN)Address;
   //
   // Calculate the cache line alignment
   //
-  End = (Start + Length + (CACHE_LINE_SIZE - 1)) & ~(CACHE_LINE_SIZE - 1);
-  Start &= ~((UINTN) CACHE_LINE_SIZE - 1);
+  End = (Start + Length + (CacheLineSize - 1)) & ~(CacheLineSize - 1);
+  Start &= ~((UINTN)CacheLineSize - 1);
 
   do {
-    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CACHE_LINE_SIZE;
+    Start = (UINTN)AsmFlushCacheLine ((VOID*)Start) + CacheLineSize;
   } while (Start != End);
   return Address;