VirtualBox

Ignore:
Timestamp:
Mar 12, 2019 12:40:12 PM (6 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
129295
Message:

EFI: First step in UDK2018 merge. Does not build yet.

Location:
trunk/src/VBox/Devices/EFI/FirmwareNew
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/EFI/FirmwareNew

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/CsmSupportLib.inf

    r48674 r77662  
    3838  MdePkg/MdePkg.dec
    3939  IntelFrameworkPkg/IntelFrameworkPkg.dec
     40  OvmfPkg/OvmfPkg.dec
     41
     42[Pcd]
     43  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId
    4044
    4145[Protocols]

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.c

    r48674 r77662  
    2020//
    2121STATIC EFI_HANDLE mLegacyInterruptHandle = NULL;
     22
     23//
     24// Legacy Interrupt Device number (0x01 on piix4, 0x1f on q35/mch)
     25//
     26STATIC UINT8      mLegacyInterruptDevice;
    2227
    2328//
    … …  
    7883{
    7984  *Bus      = LEGACY_INT_BUS;
    80   *Device   = LEGACY_INT_DEV;
     85  *Device   = mLegacyInterruptDevice;
    8186  *Function = LEGACY_INT_FUNC;
    8287
    … …  
    99104  return PCI_LIB_ADDRESS(
    100105          LEGACY_INT_BUS,
    101           LEGACY_INT_DEV,
     106          mLegacyInterruptDevice,
    102107          LEGACY_INT_FUNC,
    103108          PirqReg[PirqNumber]
    … …  
    174179  )
    175180{
     181  UINT16      HostBridgeDevId;
    176182  EFI_STATUS  Status;
    177183
    … …  
    180186  //
    181187  ASSERT_PROTOCOL_ALREADY_INSTALLED(NULL, &gEfiLegacyInterruptProtocolGuid);
     188
     189  //
     190  // Query Host Bridge DID to determine platform type, then set device number
     191  //
     192  HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
     193  switch (HostBridgeDevId) {
     194    case INTEL_82441_DEVICE_ID:
     195      mLegacyInterruptDevice = LEGACY_INT_DEV_PIIX4;
     196      break;
     197    case INTEL_Q35_MCH_DEVICE_ID:
     198      mLegacyInterruptDevice = LEGACY_INT_DEV_Q35;
     199      break;
     200    default:
     201      DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
     202        __FUNCTION__, HostBridgeDevId));
     203      ASSERT (FALSE);
     204      return EFI_UNSUPPORTED;
     205  }
    182206
    183207  //

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/LegacyInterrupt.h

    r48674 r77662  
    2121#include <Protocol/LegacyInterrupt.h>
    2222
     23#include <Library/PcdLib.h>
    2324#include <Library/PciLib.h>
    2425#include <Library/DebugLib.h>
    2526#include <Library/UefiBootServicesTableLib.h>
     27#include <OvmfPlatforms.h>
     28
    2629
    2730#define LEGACY_INT_BUS  0
    28 #define LEGACY_INT_DEV  1
     31#define LEGACY_INT_DEV_PIIX4  0x01
     32#define LEGACY_INT_DEV_Q35    0x1f
    2933#define LEGACY_INT_FUNC 0
    3034

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/LegacyPlatform.c

    r58459 r77662  
    257257
    258258  //
    259   // Initialize variable states.  Ths is important for selecting the VGA device
    260   // if multiple devices exist behind a single bridge.
     259  // Initialize variable states.  This is important for selecting the VGA
     260  // device if multiple devices exist behind a single bridge.
    261261  //
    262262  HandleCount = 0;

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.c

    r48674 r77662  
    22  Legacy Region Support
    33
    4   Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>
     4  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>
    55
    66  This program and the accompanying materials are
    … …  
    1717
    1818//
    19 // 440 PAM map.
    20 //
    21 // PAM Range       Offset  Bits  Operation
    22 // =============== ======  ====  ===============================================================
    23 // 0xC0000-0xC3FFF  0x5a   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    24 // 0xC4000-0xC7FFF  0x5a   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    25 // 0xC8000-0xCBFFF  0x5b   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    26 // 0xCC000-0xCFFFF  0x5b   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    27 // 0xD0000-0xD3FFF  0x5c   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    28 // 0xD4000-0xD7FFF  0x5c   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    29 // 0xD8000-0xDBFFF  0x5d   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    30 // 0xDC000-0xDFFFF  0x5d   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    31 // 0xE0000-0xE3FFF  0x5e   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    32 // 0xE4000-0xE7FFF  0x5e   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    33 // 0xE8000-0xEBFFF  0x5f   1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    34 // 0xEC000-0xEFFFF  0x5f   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    35 // 0xF0000-0xFFFFF  0x59   5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     19// 440/Q35 PAM map.
     20//
     21// PAM Range          Offset    Bits  Operation
     22//                  440   Q35
     23// ===============  ====  ====  ====  ===============================================================
     24// 0xC0000-0xC3FFF  0x5a  0x91  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     25// 0xC4000-0xC7FFF  0x5a  0x91  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     26// 0xC8000-0xCBFFF  0x5b  0x92  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     27// 0xCC000-0xCFFFF  0x5b  0x92  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     28// 0xD0000-0xD3FFF  0x5c  0x93  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     29// 0xD4000-0xD7FFF  0x5c  0x93  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     30// 0xD8000-0xDBFFF  0x5d  0x94  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     31// 0xDC000-0xDFFFF  0x5d  0x94  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     32// 0xE0000-0xE3FFF  0x5e  0x95  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     33// 0xE4000-0xE7FFF  0x5e  0x95  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     34// 0xE8000-0xEBFFF  0x5f  0x96  1:0   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     35// 0xEC000-0xEFFFF  0x5f  0x96  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
     36// 0xF0000-0xFFFFF  0x59  0x90  5:4   00 = DRAM Disabled, 01= Read Only, 10 = Write Only, 11 = Normal
    3637//
    3738STATIC LEGACY_MEMORY_SECTION_INFO   mSectionArray[] = {
    … …  
    5152};
    5253
    53 STATIC PAM_REGISTER_VALUE  mRegisterValues[] = {
    54   {REG_PAM1_OFFSET, 0x01, 0x02},
    55   {REG_PAM1_OFFSET, 0x10, 0x20},
    56   {REG_PAM2_OFFSET, 0x01, 0x02},
    57   {REG_PAM2_OFFSET, 0x10, 0x20},
    58   {REG_PAM3_OFFSET, 0x01, 0x02},
    59   {REG_PAM3_OFFSET, 0x10, 0x20},
    60   {REG_PAM4_OFFSET, 0x01, 0x02},
    61   {REG_PAM4_OFFSET, 0x10, 0x20},
    62   {REG_PAM5_OFFSET, 0x01, 0x02},
    63   {REG_PAM5_OFFSET, 0x10, 0x20},
    64   {REG_PAM6_OFFSET, 0x01, 0x02},
    65   {REG_PAM6_OFFSET, 0x10, 0x20},
    66   {REG_PAM0_OFFSET, 0x10, 0x20}
     54STATIC PAM_REGISTER_VALUE  mRegisterValues440[] = {
     55  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x01, 0x02},
     56  {PMC_REGISTER_PIIX4 (PIIX4_PAM1), 0x10, 0x20},
     57  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x01, 0x02},
     58  {PMC_REGISTER_PIIX4 (PIIX4_PAM2), 0x10, 0x20},
     59  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x01, 0x02},
     60  {PMC_REGISTER_PIIX4 (PIIX4_PAM3), 0x10, 0x20},
     61  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x01, 0x02},
     62  {PMC_REGISTER_PIIX4 (PIIX4_PAM4), 0x10, 0x20},
     63  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x01, 0x02},
     64  {PMC_REGISTER_PIIX4 (PIIX4_PAM5), 0x10, 0x20},
     65  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x01, 0x02},
     66  {PMC_REGISTER_PIIX4 (PIIX4_PAM6), 0x10, 0x20},
     67  {PMC_REGISTER_PIIX4 (PIIX4_PAM0), 0x10, 0x20}
    6768};
     69
     70STATIC PAM_REGISTER_VALUE  mRegisterValuesQ35[] = {
     71  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x01, 0x02},
     72  {DRAMC_REGISTER_Q35 (MCH_PAM1), 0x10, 0x20},
     73  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x01, 0x02},
     74  {DRAMC_REGISTER_Q35 (MCH_PAM2), 0x10, 0x20},
     75  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x01, 0x02},
     76  {DRAMC_REGISTER_Q35 (MCH_PAM3), 0x10, 0x20},
     77  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x01, 0x02},
     78  {DRAMC_REGISTER_Q35 (MCH_PAM4), 0x10, 0x20},
     79  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x01, 0x02},
     80  {DRAMC_REGISTER_Q35 (MCH_PAM5), 0x10, 0x20},
     81  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x01, 0x02},
     82  {DRAMC_REGISTER_Q35 (MCH_PAM6), 0x10, 0x20},
     83  {DRAMC_REGISTER_Q35 (MCH_PAM0), 0x10, 0x20}
     84};
     85
     86STATIC PAM_REGISTER_VALUE *mRegisterValues;
    6887
    6988//
    … …  
    112131  //
    113132  StartIndex = 0;
    114   for (Index = 0; Index < (sizeof(mSectionArray) / sizeof (mSectionArray[0])); Index++) {
     133  for (Index = 0; Index < ARRAY_SIZE (mSectionArray); Index++) {
    115134    if ((Start >= mSectionArray[Index].Start) && (Start < (mSectionArray[Index].Start + mSectionArray[Index].Length))) {
    116135      StartIndex = Index;
    … …  
    118137    }
    119138  }
    120   ASSERT (Index < (sizeof(mSectionArray) / sizeof (mSectionArray[0])));
     139  ASSERT (Index < ARRAY_SIZE (mSectionArray));
    121140
    122141  //
    123142  // Program PAM until end PAM is encountered
    124143  //
    125   for (Index = StartIndex; Index < (sizeof(mSectionArray) / sizeof (mSectionArray[0])); Index++) {
     144  for (Index = StartIndex; Index < ARRAY_SIZE (mSectionArray); Index++) {
    126145    if (ReadEnable != NULL) {
    127146      if (*ReadEnable) {
    128147        PciOr8 (
    129           PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
     148          mRegisterValues[Index].PAMRegPciLibAddress,
    130149          mRegisterValues[Index].ReadEnableData
    131150          );
    132151      } else {
    133152        PciAnd8 (
    134           PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
     153          mRegisterValues[Index].PAMRegPciLibAddress,
    135154          (UINT8) (~mRegisterValues[Index].ReadEnableData)
    136155          );
    … …  
    140159      if (*WriteEnable) {
    141160        PciOr8 (
    142           PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
     161          mRegisterValues[Index].PAMRegPciLibAddress,
    143162          mRegisterValues[Index].WriteEnableData
    144163          );
    145164      } else {
    146165        PciAnd8 (
    147           PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset),
     166          mRegisterValues[Index].PAMRegPciLibAddress,
    148167          (UINT8) (~mRegisterValues[Index].WriteEnableData)
    149168          );
    … …  
    159178    }
    160179  }
    161   ASSERT (Index < (sizeof(mSectionArray) / sizeof (mSectionArray[0])));
     180  ASSERT (Index < ARRAY_SIZE (mSectionArray));
    162181
    163182  return EFI_SUCCESS;
    … …  
    186205  *DescriptorCount = sizeof(mSectionArray) / sizeof (mSectionArray[0]);
    187206  for (Index = 0; Index < *DescriptorCount; Index++) {
    188     PamValue = PciRead8 (PCI_LIB_ADDRESS(PAM_PCI_BUS, PAM_PCI_DEV, PAM_PCI_FUNC, mRegisterValues[Index].PAMRegOffset));
     207    PamValue = PciRead8 (mRegisterValues[Index].PAMRegPciLibAddress);
    189208    mSectionArray[Index].ReadEnabled = FALSE;
    190209    if ((PamValue & mRegisterValues[Index].ReadEnableData) != 0) {
    … …  
    451470{
    452471  EFI_STATUS  Status;
     472  UINT16      HostBridgeDevId;
     473
     474  //
     475  // Query Host Bridge DID to determine platform type
     476  //
     477  HostBridgeDevId = PcdGet16 (PcdOvmfHostBridgePciDevId);
     478  switch (HostBridgeDevId) {
     479  case INTEL_82441_DEVICE_ID:
     480    mRegisterValues = mRegisterValues440;
     481    break;
     482  case INTEL_Q35_MCH_DEVICE_ID:
     483    mRegisterValues = mRegisterValuesQ35;
     484    break;
     485  default:
     486    DEBUG ((EFI_D_ERROR, "%a: Unknown Host Bridge Device ID: 0x%04x\n",
     487            __FUNCTION__, HostBridgeDevId));
     488    ASSERT (FALSE);
     489    return RETURN_UNSUPPORTED;
     490  }
    453491
    454492  //

  • trunk/src/VBox/Devices/EFI/FirmwareNew/OvmfPkg/Csm/CsmSupportLib/LegacyRegion.h

    r48674 r77662  
    22  Legacy Region Support
    33
    4   Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
     4  Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
    55
    66  This program and the accompanying materials are
    … …  
    2222
    2323#include <IndustryStandard/Pci.h>
     24#include <IndustryStandard/Q35MchIch9.h>
     25#include <IndustryStandard/I440FxPiix4.h>
    2426
    2527#include <Library/PciLib.h>
    … …  
    2830#include <Library/MemoryAllocationLib.h>
    2931#include <Library/UefiBootServicesTableLib.h>
    30 
    31 #define PAM_PCI_BUS        0
    32 #define PAM_PCI_DEV        0
    33 #define PAM_PCI_FUNC       0
    34 
    35 #define REG_PAM0_OFFSET    0x59    // Programmable Attribute Map 0
    36 #define REG_PAM1_OFFSET    0x5a    // Programmable Attribute Map 1
    37 #define REG_PAM2_OFFSET    0x5b    // Programmable Attribute Map 2
    38 #define REG_PAM3_OFFSET    0x5c    // Programmable Attribute Map 3
    39 #define REG_PAM4_OFFSET    0x5d    // Programmable Attribute Map 4
    40 #define REG_PAM5_OFFSET    0x5e    // Programmable Attribute Map 5
    41 #define REG_PAM6_OFFSET    0x5f    // Programmable Attribute Map 6
    4232
    4333#define PAM_BASE_ADDRESS   0xc0000
    … …  
    5848//
    5949typedef struct {
    60   UINT8   PAMRegOffset;
     50  UINTN   PAMRegPciLibAddress;
    6151  UINT8   ReadEnableData;
    6252  UINT8   WriteEnableData;
Note: See TracChangeset for help on using the changeset viewer.

© 2025 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette