Changeset 77662 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe

Timestamp:

Mar 12, 2019 12:40:12 PM (6 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

129295

Message:

EFI: First step in UDK2018 merge. Does not build yet.

Location:

trunk/src/VBox/Devices/EFI/FirmwareNew

Files:

• . (modified) (1 prop)
• UefiCpuPkg/CpuDxe/CpuDxe.c (modified) (17 diffs)
• UefiCpuPkg/CpuDxe/CpuDxe.h (modified) (5 diffs)
• UefiCpuPkg/CpuDxe/CpuDxe.inf (modified) (4 diffs)
• UefiCpuPkg/CpuDxe/CpuDxe.uni (modified) (2 diffs)
• UefiCpuPkg/CpuDxe/CpuDxeExtra.uni (modified) (2 diffs)
• UefiCpuPkg/CpuDxe/CpuGdt.c (modified) (8 diffs)
• UefiCpuPkg/CpuDxe/CpuGdt.h (added)
• UefiCpuPkg/CpuDxe/CpuMp.c (added)
• UefiCpuPkg/CpuDxe/CpuMp.h (added)
• UefiCpuPkg/CpuDxe/CpuPageTable.c (added)
• UefiCpuPkg/CpuDxe/CpuPageTable.h (added)
• UefiCpuPkg/CpuDxe/Ia32/CpuAsm.nasm (added)
• UefiCpuPkg/CpuDxe/X64/CpuAsm.nasm (added)

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuDxe.c

@@ -1 +1 @@
 /** @file
-  CPU DXE Module.
-
-  Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+  CPU DXE Module to produce CPU ARCH Protocol.
+
+  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -14 +14 @@
 
 #include "CpuDxe.h"
+#include "CpuMp.h"
+#include "CpuPageTable.h"
+
+#define CACHE_ATTRIBUTE_MASK   (EFI_MEMORY_UC | EFI_MEMORY_WC | EFI_MEMORY_WT | EFI_MEMORY_WB | EFI_MEMORY_UCE | EFI_MEMORY_WP)
+#define MEMORY_ATTRIBUTE_MASK  (EFI_MEMORY_RP | EFI_MEMORY_XP | EFI_MEMORY_RO)
 
 //
@@ -21 +26 @@
 EFI_HANDLE                mCpuHandle = NULL;
 BOOLEAN                   mIsFlushingGCD;
-UINT64                    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
-UINT64                    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
+BOOLEAN                   mIsAllocatingPageTable = FALSE;
+UINT64                    mValidMtrrAddressMask;
+UINT64                    mValidMtrrBitsMask;
+UINT64                    mTimerPeriod = 0;
 
 FIXED_MTRR    mFixedMtrrTable[] = {
   {
-    MTRR_LIB_IA32_MTRR_FIX64K_00000,
+    MSR_IA32_MTRR_FIX64K_00000,
     0,
     0x10000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX16K_80000,
+    MSR_IA32_MTRR_FIX16K_80000,
     0x80000,
     0x4000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX16K_A0000,
+    MSR_IA32_MTRR_FIX16K_A0000,
     0xA0000,
     0x4000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_C0000,
+    MSR_IA32_MTRR_FIX4K_C0000,
     0xC0000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_C8000,
+    MSR_IA32_MTRR_FIX4K_C8000,
     0xC8000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_D0000,
+    MSR_IA32_MTRR_FIX4K_D0000,
     0xD0000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_D8000,
+    MSR_IA32_MTRR_FIX4K_D8000,
     0xD8000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_E0000,
+    MSR_IA32_MTRR_FIX4K_E0000,
     0xE0000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_E8000,
+    MSR_IA32_MTRR_FIX4K_E8000,
     0xE8000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_F0000,
+    MSR_IA32_MTRR_FIX4K_F0000,
     0xF0000,
     0x1000
   },
   {
-    MTRR_LIB_IA32_MTRR_FIX4K_F8000,
+    MSR_IA32_MTRR_FIX4K_F8000,
     0xF8000,
     0x1000
@@ -293 +300 @@
   )
 {
+  UINT64          BeginValue;
+  UINT64          EndValue;
+
   if (TimerValue == NULL) {
     return EFI_INVALID_PARAMETER;
@@ -304 +314 @@
 
   if (TimerPeriod != NULL) {
+    if (mTimerPeriod == 0) {
       //
-      // BugBug: Hard coded. Don't know how to do this generically
+      // Read time stamp counter before and after delay of 100 microseconds
       //
-      *TimerPeriod = 1000000000;
+      BeginValue = AsmReadTsc ();
+      MicroSecondDelay (100);
+      EndValue   = AsmReadTsc ();
+      //
+      // Calculate the actual frequency
+      //
+      mTimerPeriod = DivU64x64Remainder (
+                       MultU64x32 (
+                         1000 * 1000 * 1000,
+                         100
+                         ),
+                       EndValue - BeginValue,
+                       NULL
+                       );
+    }
+    *TimerPeriod = mTimerPeriod;
   }
 
@@ -313 +339 @@
 }
 
+/**
+  A minimal wrapper function that allows MtrrSetAllMtrrs() to be passed to
+  EFI_MP_SERVICES_PROTOCOL.StartupAllAPs() as Procedure.
+
+  @param[in] Buffer  Pointer to an MTRR_SETTINGS object, to be passed to
+                     MtrrSetAllMtrrs().
+**/
+VOID
+EFIAPI
+SetMtrrsFromBuffer (
+  IN VOID *Buffer
+  )
+{
+  MtrrSetAllMtrrs (Buffer);
+}
 
 /**
@@ -350 +391 @@
   RETURN_STATUS             Status;
   MTRR_MEMORY_CACHE_TYPE    CacheType;
-
-  if (!IsMtrrSupported ()) {
-    return EFI_UNSUPPORTED;
-  }
+  EFI_STATUS                MpStatus;
+  EFI_MP_SERVICES_PROTOCOL  *MpService;
+  MTRR_SETTINGS             MtrrSettings;
+  UINT64                    CacheAttributes;
+  UINT64                    MemoryAttributes;
+  MTRR_MEMORY_CACHE_TYPE    CurrentCacheType;
 
   //
@@ -362 +405 @@
   //
   if (mIsFlushingGCD) {
-    DEBUG((EFI_D_INFO, "  Flushing GCD\n"));
+    DEBUG((DEBUG_INFO, "  Flushing GCD\n"));
     return EFI_SUCCESS;
   }
 
-  switch (Attributes) {
-  case EFI_MEMORY_UC:
-    CacheType = CacheUncacheable;
-    break;
-
-  case EFI_MEMORY_WC:
-    CacheType = CacheWriteCombining;
-    break;
-
-  case EFI_MEMORY_WT:
-    CacheType = CacheWriteThrough;
-    break;
-
-  case EFI_MEMORY_WP:
-    CacheType = CacheWriteProtected;
-    break;
-
-  case EFI_MEMORY_WB:
-    CacheType = CacheWriteBack;
-    break;
-
-  case EFI_MEMORY_UCE:
-  case EFI_MEMORY_RP:
-  case EFI_MEMORY_XP:
-  case EFI_MEMORY_RUNTIME:
-    return EFI_UNSUPPORTED;
-
-  default:
+  //
+  // During memory attributes updating, new pages may be allocated to setup
+  // smaller granularity of page table. Page allocation action might then cause
+  // another calling of CpuSetMemoryAttributes() recursively, due to memory
+  // protection policy configured (such as PcdDxeNxMemoryProtectionPolicy).
+  // Since this driver will always protect memory used as page table by itself,
+  // there's no need to apply protection policy requested from memory service.
+  // So it's safe to just return EFI_SUCCESS if this time of calling is caused
+  // by page table memory allocation.
+  //
+  if (mIsAllocatingPageTable) {
+    DEBUG((DEBUG_VERBOSE, "  Allocating page table memory\n"));
+    return EFI_SUCCESS;
+  }
+
+  CacheAttributes = Attributes & CACHE_ATTRIBUTE_MASK;
+  MemoryAttributes = Attributes & MEMORY_ATTRIBUTE_MASK;
+
+  if (Attributes != (CacheAttributes | MemoryAttributes)) {
     return EFI_INVALID_PARAMETER;
   }
-  //
-  // call MTRR libary function
-  //
-  Status = MtrrSetMemoryAttribute (
-             BaseAddress,
-             Length,
-             CacheType
-             );
-
-  return (EFI_STATUS) Status;
+
+  if (CacheAttributes != 0) {
+    if (!IsMtrrSupported ()) {
+      return EFI_UNSUPPORTED;
+    }
+
+    switch (CacheAttributes) {
+    case EFI_MEMORY_UC:
+      CacheType = CacheUncacheable;
+      break;
+
+    case EFI_MEMORY_WC:
+      CacheType = CacheWriteCombining;
+      break;
+
+    case EFI_MEMORY_WT:
+      CacheType = CacheWriteThrough;
+      break;
+
+    case EFI_MEMORY_WP:
+      CacheType = CacheWriteProtected;
+      break;
+
+    case EFI_MEMORY_WB:
+      CacheType = CacheWriteBack;
+      break;
+
+    default:
+      return EFI_INVALID_PARAMETER;
+    }
+    CurrentCacheType = MtrrGetMemoryAttribute(BaseAddress);
+    if (CurrentCacheType != CacheType) {
+      //
+      // call MTRR libary function
+      //
+      Status = MtrrSetMemoryAttribute (
+                 BaseAddress,
+                 Length,
+                 CacheType
+                 );
+
+      if (!RETURN_ERROR (Status)) {
+        MpStatus = gBS->LocateProtocol (
+                          &gEfiMpServiceProtocolGuid,
+                          NULL,
+                          (VOID **)&MpService
+                          );
+        //
+        // Synchronize the update with all APs
+        //
+        if (!EFI_ERROR (MpStatus)) {
+          MtrrGetAllMtrrs (&MtrrSettings);
+          MpStatus = MpService->StartupAllAPs (
+                                  MpService,          // This
+                                  SetMtrrsFromBuffer, // Procedure
+                                  FALSE,              // SingleThread
+                                  NULL,               // WaitEvent
+                                  0,                  // TimeoutInMicrosecsond
+                                  &MtrrSettings,      // ProcedureArgument
+                                  NULL                // FailedCpuList
+                                  );
+          ASSERT (MpStatus == EFI_SUCCESS || MpStatus == EFI_NOT_STARTED);
+        }
+      }
+      if (EFI_ERROR(Status)) {
+        return Status;
+      }
+    }
+  }
+
+  //
+  // Set memory attribute by page table
+  //
+  return AssignMemoryPageAttributes (NULL, BaseAddress, Length, MemoryAttributes, NULL);
 }
 
@@ -428 +526 @@
 
     PhysicalAddressBits = (UINT8) RegEax;
-
-    mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
-    mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
   } else {
-    mValidMtrrBitsMask    = MTRR_LIB_MSR_VALID_MASK;
-    mValidMtrrAddressMask = MTRR_LIB_CACHE_VALID_ADDRESS;
-  }
+    PhysicalAddressBits = 36;
+  }
+
+  mValidMtrrBitsMask    = LShiftU64 (1, PhysicalAddressBits) - 1;
+  mValidMtrrAddressMask = mValidMtrrBitsMask & 0xfffffffffffff000ULL;
 }
 
@@ -602 +699 @@
 **/
 VOID
-RefreshGcdMemoryAttributes (
+RefreshMemoryAttributesFromMtrr (
   VOID
   )
@@ -623 +720 @@
   UINT8                               DefaultMemoryType;
 
-  if (!IsMtrrSupported ()) {
-    return;
-  }
-
   FirmwareVariableMtrrCount = GetFirmwareVariableMtrrCount ();
   ASSERT (FirmwareVariableMtrrCount <= MTRR_NUMBER_OF_VARIABLE_MTRR);
 
-  mIsFlushingGCD = TRUE;
   MemorySpaceMap = NULL;
 
@@ -781 +873 @@
     FreePool (MemorySpaceMap);
   }
+}
+
+/**
+ Check if paging is enabled or not.
+**/
+BOOLEAN
+IsPagingAndPageAddressExtensionsEnabled (
+  VOID
+  )
+{
+  IA32_CR0  Cr0;
+  IA32_CR4  Cr4;
+
+  Cr0.UintN = AsmReadCr0 ();
+  Cr4.UintN = AsmReadCr4 ();
+
+  return ((Cr0.Bits.PG != 0) && (Cr4.Bits.PAE != 0));
+}
+
+/**
+  Refreshes the GCD Memory Space attributes according to MTRRs and Paging.
+
+  This function refreshes the GCD Memory Space attributes according to MTRRs
+  and page tables.
+
+**/
+VOID
+RefreshGcdMemoryAttributes (
+  VOID
+  )
+{
+  mIsFlushingGCD = TRUE;
+
+  if (IsMtrrSupported ()) {
+    RefreshMemoryAttributesFromMtrr ();
+  }
+
+  if (IsPagingAndPageAddressExtensionsEnabled ()) {
+    RefreshGcdMemoryAttributesFromPaging ();
+  }
 
   mIsFlushingGCD = FALSE;
@@ -826 +958 @@
 }
 
+/**
+  Ensure the compatibility of a memory space descriptor with the MMIO aperture.
+
+  The memory space descriptor can come from the GCD memory space map, or it can
+  represent a gap between two neighboring memory space descriptors. In the
+  latter case, the GcdMemoryType field is expected to be
+  EfiGcdMemoryTypeNonExistent.
+
+  If the memory space descriptor already has type
+  EfiGcdMemoryTypeMemoryMappedIo, and its capabilities are a superset of the
+  required capabilities, then no action is taken -- it is by definition
+  compatible with the aperture.
+
+  Otherwise, the intersection of the memory space descriptor is calculated with
+  the aperture. If the intersection is the empty set (no overlap), no action is
+  taken; the memory space descriptor is compatible with the aperture.
+
+  Otherwise, the type of the descriptor is investigated again. If the type is
+  EfiGcdMemoryTypeNonExistent (representing a gap, or a genuine descriptor with
+  such a type), then an attempt is made to add the intersection as MMIO space
+  to the GCD memory space map, with the specified capabilities. This ensures
+  continuity for the aperture, and the descriptor is deemed compatible with the
+  aperture.
+
+  Otherwise, the memory space descriptor is incompatible with the MMIO
+  aperture.
+
+  @param[in] Base         Base address of the aperture.
+  @param[in] Length       Length of the aperture.
+  @param[in] Capabilities Capabilities required by the aperture.
+  @param[in] Descriptor   The descriptor to ensure compatibility with the
+                          aperture for.
+
+  @retval EFI_SUCCESS            The descriptor is compatible. The GCD memory
+                                 space map may have been updated, for
+                                 continuity within the aperture.
+  @retval EFI_INVALID_PARAMETER  The descriptor is incompatible.
+  @return                        Error codes from gDS->AddMemorySpace().
+**/
+EFI_STATUS
+IntersectMemoryDescriptor (
+  IN  UINT64                                Base,
+  IN  UINT64                                Length,
+  IN  UINT64                                Capabilities,
+  IN  CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Descriptor
+  )
+{
+  UINT64                                    IntersectionBase;
+  UINT64                                    IntersectionEnd;
+  EFI_STATUS                                Status;
+
+  if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo &&
+      (Descriptor->Capabilities & Capabilities) == Capabilities) {
+    return EFI_SUCCESS;
+  }
+
+  IntersectionBase = MAX (Base, Descriptor->BaseAddress);
+  IntersectionEnd = MIN (Base + Length,
+                      Descriptor->BaseAddress + Descriptor->Length);
+  if (IntersectionBase >= IntersectionEnd) {
+    //
+    // The descriptor and the aperture don't overlap.
+    //
+    return EFI_SUCCESS;
+  }
+
+  if (Descriptor->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {
+    Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
+                    IntersectionBase, IntersectionEnd - IntersectionBase,
+                    Capabilities);
+
+    DEBUG ((EFI_ERROR (Status) ? DEBUG_ERROR : DEBUG_VERBOSE,
+      "%a: %a: add [%Lx, %Lx): %r\n", gEfiCallerBaseName, __FUNCTION__,
+      IntersectionBase, IntersectionEnd, Status));
+    return Status;
+  }
+
+  DEBUG ((DEBUG_ERROR, "%a: %a: desc [%Lx, %Lx) type %u cap %Lx conflicts "
+    "with aperture [%Lx, %Lx) cap %Lx\n", gEfiCallerBaseName, __FUNCTION__,
+    Descriptor->BaseAddress, Descriptor->BaseAddress + Descriptor->Length,
+    (UINT32)Descriptor->GcdMemoryType, Descriptor->Capabilities,
+    Base, Base + Length, Capabilities));
+  return EFI_INVALID_PARAMETER;
+}
+
+/**
+  Add MMIO space to GCD.
+  The routine checks the GCD database and only adds those which are
+  not added in the specified range to GCD.
+
+  @param Base         Base address of the MMIO space.
+  @param Length       Length of the MMIO space.
+  @param Capabilities Capabilities of the MMIO space.
+
+  @retval EFI_SUCCES The MMIO space was added successfully.
+**/
+EFI_STATUS
+AddMemoryMappedIoSpace (
+  IN  UINT64                            Base,
+  IN  UINT64                            Length,
+  IN  UINT64                            Capabilities
+  )
+{
+  EFI_STATUS                            Status;
+  UINTN                                 Index;
+  UINTN                                 NumberOfDescriptors;
+  EFI_GCD_MEMORY_SPACE_DESCRIPTOR       *MemorySpaceMap;
+
+  Status = gDS->GetMemorySpaceMap (&NumberOfDescriptors, &MemorySpaceMap);
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_ERROR, "%a: %a: GetMemorySpaceMap(): %r\n",
+      gEfiCallerBaseName, __FUNCTION__, Status));
+    return Status;
+  }
+
+  for (Index = 0; Index < NumberOfDescriptors; Index++) {
+    Status = IntersectMemoryDescriptor (Base, Length, Capabilities,
+               &MemorySpaceMap[Index]);
+    if (EFI_ERROR (Status)) {
+      goto FreeMemorySpaceMap;
+    }
+  }
+
+  DEBUG_CODE (
+    //
+    // Make sure there are adjacent descriptors covering [Base, Base + Length).
+    // It is possible that they have not been merged; merging can be prevented
+    // by allocation and different capabilities.
+    //
+    UINT64                          CheckBase;
+    EFI_STATUS                      CheckStatus;
+    EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;
+
+    for (CheckBase = Base;
+         CheckBase < Base + Length;
+         CheckBase = Descriptor.BaseAddress + Descriptor.Length) {
+      CheckStatus = gDS->GetMemorySpaceDescriptor (CheckBase, &Descriptor);
+      ASSERT_EFI_ERROR (CheckStatus);
+      ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
+      ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
+    }
+    );
+
+FreeMemorySpaceMap:
+  FreePool (MemorySpaceMap);
+
+  return Status;
+}
+
+/**
+  Add and allocate CPU local APIC memory mapped space.
+
+  @param[in]ImageHandle     Image handle this driver.
+
+**/
+VOID
+AddLocalApicMemorySpace (
+  IN EFI_HANDLE               ImageHandle
+  )
+{
+  EFI_STATUS              Status;
+  EFI_PHYSICAL_ADDRESS    BaseAddress;
+
+  BaseAddress = (EFI_PHYSICAL_ADDRESS) GetLocalApicBaseAddress();
+  Status = AddMemoryMappedIoSpace (BaseAddress, SIZE_4KB, EFI_MEMORY_UC);
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Try to allocate APIC memory mapped space, does not check return
+  // status because it may be allocated by other driver, or DXE Core if
+  // this range is built into Memory Allocation HOB.
+  //
+  Status = gDS->AllocateMemorySpace (
+                  EfiGcdAllocateAddress,
+                  EfiGcdMemoryTypeMemoryMappedIo,
+                  0,
+                  SIZE_4KB,
+                  &BaseAddress,
+                  ImageHandle,
+                  NULL
+                  );
+  if (EFI_ERROR (Status)) {
+    DEBUG ((DEBUG_INFO, "%a: %a: AllocateMemorySpace() Status - %r\n",
+                         gEfiCallerBaseName, __FUNCTION__, Status));
+  }
+}
 
 /**
@@ -848 +1166 @@
   EFI_EVENT   IdleLoopEvent;
 
+  InitializePageTableLib();
+
   InitializeFloatingPointUnits ();
 
@@ -864 +1184 @@
   //
   InitInterruptDescriptorTable ();
-
-  //
-  // Enable the local APIC for Virtual Wire Mode.
-  //
-  ProgramVirtualWireMode ();
 
   //
@@ -884 +1199 @@
   //
   RefreshGcdMemoryAttributes ();
+
+  //
+  // Add and allocate local APIC memory mapped space
+  //
+  AddLocalApicMemorySpace (ImageHandle);
 
   //
@@ -898 +1218 @@
   ASSERT_EFI_ERROR (Status);
 
+  InitializeMpSupport ();
+
   return Status;
 }

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuDxe.h

@@ -1 +1 @@
 /** @file
-  CPU DXE Module.
-
-  Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR>
+  CPU DXE Module to produce CPU ARCH Protocol and CPU MP Protocol.
+
+  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -19 +19 @@
 
 #include <Protocol/Cpu.h>
+#include <Protocol/MpService.h>
+#include <Register/Msr.h>
+
+#include <Ppi/SecPlatformInformation.h>
+#include <Ppi/SecPlatformInformation2.h>
 
 #include <Library/UefiDriverEntryPoint.h>
@@ -33 +38 @@
 #include <Library/UefiLib.h>
 #include <Library/CpuExceptionHandlerLib.h>
+#include <Library/HobLib.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Library/MpInitLib.h>
+#include <Library/TimerLib.h>
+
 #include <Guid/IdleLoopEvent.h>
 #include <Guid/VectorHandoffTable.h>
@@ -43 +53 @@
                                        )
 
+#define EFI_MEMORY_PAGETYPE_MASK      (EFI_MEMORY_RP  | \
+                                       EFI_MEMORY_XP  | \
+                                       EFI_MEMORY_RO    \
+                                       )
 
 /**
@@ -252 +266 @@
   );
 
+/**
+  Update GCD memory space attributes according to current page table setup.
+**/
+VOID
+RefreshGcdMemoryAttributesFromPaging (
+  VOID
+  );
+
+extern BOOLEAN mIsAllocatingPageTable;
+
 #endif
 

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuDxe.inf

@@ -1 +1 @@
 ## @file
-#  Simple CPU driver installs CPU Architecture Protocol.
+#  CPU driver installs CPU Architecture Protocol and CPU MP protocol.
 #
-#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>
+#  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
+#
 #  This program and the accompanying materials
 #  are licensed and made available under the terms and conditions of the BSD License
@@ -20 +22 @@
   MODULE_TYPE                    = DXE_DRIVER
   VERSION_STRING                 = 1.0
-
   ENTRY_POINT                    = InitializeCpu
 
@@ -42 +43 @@
   UefiLib
   CpuExceptionHandlerLib
+  HobLib
+  ReportStatusCodeLib
+  MpInitLib
+  TimerLib
 
 [Sources]
@@ -47 +52 @@
   CpuDxe.h
   CpuGdt.c
+  CpuGdt.h
+  CpuMp.c
+  CpuMp.h
+  CpuPageTable.h
+  CpuPageTable.c
 
 [Sources.IA32]
-  Ia32/CpuAsm.asm | MSFT
-  Ia32/CpuAsm.asm | INTEL
-  Ia32/CpuAsm.S   | GCC
+  Ia32/CpuAsm.asm
+  Ia32/CpuAsm.nasm
+  Ia32/CpuAsm.S
 
 [Sources.X64]
-  X64/CpuAsm.asm | MSFT
-  X64/CpuAsm.asm | INTEL
-  X64/CpuAsm.S   | GCC
+  X64/CpuAsm.asm
+  X64/CpuAsm.nasm
+  X64/CpuAsm.S
 
 [Protocols]
   gEfiCpuArchProtocolGuid                       ## PRODUCES
+  gEfiMpServiceProtocolGuid                     ## PRODUCES
+  gEfiSmmBase2ProtocolGuid                      ## SOMETIMES_CONSUMES
 
 [Guids]
   gIdleLoopEventGuid                            ## CONSUMES           ## Event
   gEfiVectorHandoffTableGuid                    ## SOMETIMES_CONSUMES ## SystemTable
+
+[Ppis]
+  gEfiSecPlatformInformation2PpiGuid            ## UNDEFINED # HOB
+  gEfiSecPlatformInformationPpiGuid             ## UNDEFINED # HOB
+
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES
+  gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard                       ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuStackSwitchExceptionList              ## CONSUMES
+  gUefiCpuPkgTokenSpaceGuid.PcdCpuKnownGoodStackSize                    ## CONSUMES
 
 [Depex]

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuDxe.uni

@@ -1 @@
-// /** @file
-// Simple CPU driver installs CPU Architecture Protocol.
+// /** @file
+// CPU driver installs CPU Architecture Protocol and CPU MP Protocol.
 //
-// Simple CPU driver installs CPU Architecture Protocol.
+// CPU driver installs CPU Architecture Protocol and CPU MP Protocol.
 //
-// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2008 - 2016, Intel Corporation. All rights reserved.<BR>
 //
 // This program and the accompanying materials
@@ -17 +17 @@
 
 
-#string STR_MODULE_ABSTRACT             #language en-US "Installs CPU Architecture Protocol"
+#string STR_MODULE_ABSTRACT             #language en-US "CPU driver installs CPU Architecture Protocol and CPU MP Protocol."
 
-#string STR_MODULE_DESCRIPTION          #language en-US "Simple CPU driver installs CPU Architecture Protocol."
+#string STR_MODULE_DESCRIPTION          #language en-US "CPU driver installs CPU Architecture Protocol and CPU MP Protocol."
 

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuDxeExtra.uni

@@ -1 @@
-// /** @file
+// /** @file
 // CpuDxe Localized Strings and Content
 //
-// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+// Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
 //
 // This program and the accompanying materials
@@ -16 +16 @@
 #string STR_PROPERTIES_MODULE_NAME 
 #language en-US 
-"CPU Architectural DXE Driver"
+"CPU Architectural and CPU Multi-processor DXE Driver"
 
 

trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/CpuDxe/CpuGdt.c

@@ -3 +3 @@
   requiring a minimal assembly interrupt entry point.
 
-  Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+  Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
   This program and the accompanying materials
   are licensed and made available under the terms and conditions of the BSD License
@@ -15 +15 @@
 
 #include "CpuDxe.h"
-
-
-//
-// Local structure definitions
-//
-
-#pragma pack (1)
-
-//
-// Global Descriptor Entry structures
-//
-
-typedef struct _GDT_ENTRY {
-  UINT16 Limit15_0;
-  UINT16 Base15_0;
-  UINT8  Base23_16;
-  UINT8  Type;
-  UINT8  Limit19_16_and_flags;
-  UINT8  Base31_24;
-} GDT_ENTRY;
-
-typedef
-struct _GDT_ENTRIES {
-  GDT_ENTRY Null;
-  GDT_ENTRY Linear;
-  GDT_ENTRY LinearCode;
-  GDT_ENTRY SysData;
-  GDT_ENTRY SysCode;
-  GDT_ENTRY LinearCode64;
-  GDT_ENTRY Spare4;
-  GDT_ENTRY Spare5;
-} GDT_ENTRIES;
-
-#define NULL_SEL          OFFSET_OF (GDT_ENTRIES, Null)
-#define LINEAR_SEL        OFFSET_OF (GDT_ENTRIES, Linear)
-#define LINEAR_CODE_SEL   OFFSET_OF (GDT_ENTRIES, LinearCode)
-#define SYS_DATA_SEL      OFFSET_OF (GDT_ENTRIES, SysData)
-#define SYS_CODE_SEL      OFFSET_OF (GDT_ENTRIES, SysCode)
-#define LINEAR_CODE64_SEL OFFSET_OF (GDT_ENTRIES, LinearCode64)
-#define SPARE4_SEL        OFFSET_OF (GDT_ENTRIES, Spare4)
-#define SPARE5_SEL        OFFSET_OF (GDT_ENTRIES, Spare5)
-
-#if defined (MDE_CPU_IA32)
-#define CPU_CODE_SEL LINEAR_CODE_SEL
-#define CPU_DATA_SEL LINEAR_SEL
-#elif defined (MDE_CPU_X64)
-#define CPU_CODE_SEL LINEAR_CODE64_SEL
-#define CPU_DATA_SEL LINEAR_SEL
-#else
-#error CPU type not supported for CPU GDT initialization!
-#endif
+#include "CpuGdt.h"
 
 //
@@ -86 +36 @@
   //
   {
-    0x0FFFF,        // limit 0xFFFFF
-    0x0,            // base 0
-    0x0,
-    0x092,          // present, ring 0, data, expand-up, writable
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x092,          // present, ring 0, data, read/write
     0x0CF,          // page-granular, 32-bit
     0x0,
@@ -97 +47 @@
   //
   {
-    0x0FFFF,        // limit 0xFFFFF
-    0x0,            // base 0
-    0x0,
-    0x09A,          // present, ring 0, data, expand-up, writable
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x09F,          // present, ring 0, code, execute/read, conforming, accessed
     0x0CF,          // page-granular, 32-bit
     0x0,
@@ -108 +58 @@
   //
   {
-    0x0FFFF,        // limit 0xFFFFF
-    0x0,            // base 0
-    0x0,
-    0x092,          // present, ring 0, data, expand-up, writable
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x093,          // present, ring 0, data, read/write, accessed
     0x0CF,          // page-granular, 32-bit
     0x0,
@@ -119 +69 @@
   //
   {
-    0x0FFFF,        // limit 0xFFFFF
-    0x0,            // base 0
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x09A,          // present, ring 0, code, execute/read
+    0x0CF,          // page-granular, 32-bit
     0x0,
-    0x09A,          // present, ring 0, data, expand-up, writable
+  },
+  //
+  // SPARE4_SEL
+  //
+  {
+    0x0,            // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x0,            // type
+    0x0,            // limit 19:16, flags
+    0x0,            // base 31:24
+  },
+  //
+  // LINEAR_DATA64_SEL
+  //
+  {
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x092,          // present, ring 0, data, read/write
     0x0CF,          // page-granular, 32-bit
     0x0,
@@ -130 +102 @@
   //
   {
-    0x0FFFF,        // limit 0xFFFFF
-    0x0,            // base 0
-    0x0,
-    0x09B,          // present, ring 0, code, expand-up, writable
-    0x0AF,          // LimitHigh (CS.L=1, CS.D=0)
+    0x0FFFF,        // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x09A,          // present, ring 0, code, execute/read
+    0x0AF,          // page-granular, 64-bit code
     0x0,            // base (high)
-  },
-  //
-  // SPARE4_SEL
-  //
-  {
-    0x0,            // limit 0
-    0x0,            // base 0
-    0x0,
-    0x0,            // present, ring 0, data, expand-up, writable
-    0x0,            // page-granular, 32-bit
-    0x0,
   },
   //
@@ -152 +113 @@
   //
   {
-    0x0,            // limit 0
-    0x0,            // base 0
-    0x0,
-    0x0,            // present, ring 0, data, expand-up, writable
-    0x0,            // page-granular, 32-bit
-    0x0,
+    0x0,            // limit 15:0
+    0x0,            // base 15:0
+    0x0,            // base 23:16
+    0x0,            // type
+    0x0,            // limit 19:16, flags
+    0x0,            // base 31:24
   },
 };