VirtualBox

Changeset 78632 in vbox for trunk/src


Ignore:
Timestamp:
May 21, 2019 1:56:11 PM (6 years ago)
Author:
vboxsync
Message:

Forward ported 130474,130475,130477,130479. bugref:9453

Location:
trunk
Files:
17 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
        1010/branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
         11/branches/VBox-6.0:130474-130475,130477,130479
        1112/branches/aeichner/vbox-chromium-cleanup:129816,129818-129851,129853-129861,129871-129872,129876,129880,129882,130013-130015,130036,130094-130095
        1213/branches/andy/draganddrop:90781-91268

  • trunk/src/VBox

    • Property svn:mergeinfo

      •  

        old new  
        99/branches/VBox-5.1/src/VBox:112367,116543,116550,116568,116573
        1010/branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124263,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812,127158-127159,127162-127167,127180
         11/branches/VBox-6.0/src/VBox:130474-130475,130477,130479
        1112/branches/aeichner/vbox-chromium-cleanup/src/VBox:129818-129851,129853-129861,129871-129872,129876,129880,129882,130013-130015,130094-130095
        1213/branches/andy/draganddrop/src/VBox:90781-91268

  • trunk/src/VBox/Frontends

    • Property svn:mergeinfo

      •  

        old new  
        88/branches/VBox-4.3/trunk/src/VBox/Frontends:91223
        99/branches/VBox-5.2/src/VBox/Frontends:120213,124288
         10/branches/VBox-6.0/src/VBox/Frontends:130474-130475,130477,130479
        1011/branches/andy/draganddrop/src/VBox/Frontends:90781-91268
        1112/branches/andy/guestctrl20/src/VBox/Frontends:78916,78930

  • trunk/src/VBox/Frontends/VBoxManage/VBoxManageHelp.cpp

    r78512 r78632  
    523523                     "                            [--l1d-flush-on-sched on|off]\n"
    524524                     "                            [--l1d-flush-on-vm-entry on|off]\n"
     525                     "                            [--mds-clear-on-sched on|off]\n"
     526                     "                            [--mds-clear-on-vm-entry on|off]\n"
    525527                     "                            [--nested-hw-virt on|off]\n"
    526528                     "                            [--cpu-profile \"host|Intel 80[86|286|386]\"]\n"

  • trunk/src/VBox/Frontends/VBoxManage/VBoxManageModifyVM.cpp

    r78064 r78632  
    8080    MODIFYVM_L1D_FLUSH_ON_SCHED,
    8181    MODIFYVM_L1D_FLUSH_ON_VM_ENTRY,
     82    MODIFYVM_MDS_CLEAR_ON_SCHED,
     83    MODIFYVM_MDS_CLEAR_ON_VM_ENTRY,
    8284    MODIFYVM_NESTED_HW_VIRT,
    8385    MODIFYVM_CPUS,
    … …  
    269271    { "--l1d-flush-on-sched",       MODIFYVM_L1D_FLUSH_ON_SCHED,        RTGETOPT_REQ_BOOL_ONOFF },
    270272    { "--l1d-flush-on-vm-entry",    MODIFYVM_L1D_FLUSH_ON_VM_ENTRY,     RTGETOPT_REQ_BOOL_ONOFF },
     273    { "--mds-clear-on-sched",       MODIFYVM_MDS_CLEAR_ON_SCHED,        RTGETOPT_REQ_BOOL_ONOFF },
     274    { "--mds-clear-on-vm-entry",    MODIFYVM_MDS_CLEAR_ON_VM_ENTRY,     RTGETOPT_REQ_BOOL_ONOFF },
    271275    { "--nested-hw-virt",           MODIFYVM_NESTED_HW_VIRT,            RTGETOPT_REQ_BOOL_ONOFF },
    272276    { "--cpuid-set",                MODIFYVM_SETCPUID,                  RTGETOPT_REQ_UINT32_OPTIONAL_PAIR | RTGETOPT_FLAG_HEX },
    … …  
    828832                break;
    829833
     834            case MODIFYVM_MDS_CLEAR_ON_SCHED:
     835                CHECK_ERROR(sessionMachine, SetCPUProperty(CPUPropertyType_MDSClearOnEMTScheduling, ValueUnion.f));
     836                break;
     837
     838            case MODIFYVM_MDS_CLEAR_ON_VM_ENTRY:
     839                CHECK_ERROR(sessionMachine, SetCPUProperty(CPUPropertyType_MDSClearOnVMEntry, ValueUnion.f));
     840                break;
     841
    830842            case MODIFYVM_NESTED_HW_VIRT:
    831843                CHECK_ERROR(sessionMachine, SetCPUProperty(CPUPropertyType_HWVirt, ValueUnion.f));

  • trunk/src/VBox/Main/idl/VirtualBox.xidl

    r78534 r78632  
    10781078        causing many VM exits, so it is only recommended for situation where there
    10791079        is a real need to be paranoid.
     1080      </desc>
     1081    </const>
     1082    <const name="MDSClearOnEMTScheduling" value="13">
     1083      <desc>
     1084        If set and the host is affected by CVE-2018-12126, CVE-2018-12127, or
     1085        CVE-2018-12130, clears the relevant MDS buffers when the EMT is scheduled
     1086        to do ring-0 guest execution.  There could be a small performance penalty
     1087        for certain typs of workloads. For security reasons this setting will be
     1088        enabled by default.
     1089      </desc>
     1090    </const>
     1091    <const name="MDSClearOnVMEntry"     value="14">
     1092      <desc>
     1093        If set and the host is affected by CVE-2018-12126, CVE-2018-12127, or
     1094        CVE-2018-12130, clears the relevant MDS buffers on every VM entry.  This
     1095        setting may slow down workloads causing many VM exits, so it is only
     1096        recommended for situation where there is a real need to be paranoid.
    10801097      </desc>
    10811098    </const>

  • trunk/src/VBox/Main/include/MachineImpl.h

    r78296 r78632  
    290290        BOOL                mL1DFlushOnSched;
    291291        BOOL                mL1DFlushOnVMEntry;
     292        BOOL                mMDSClearOnSched;
     293        BOOL                mMDSClearOnVMEntry;
    292294        BOOL                mNestedHWVirt;
    293295        ULONG               mCPUCount;

  • trunk/src/VBox/Main/src-client/ConsoleImpl2.cpp

    r78509 r78632  
    11911191        hrc = pMachine->GetCPUProperty(CPUPropertyType_L1DFlushOnVMEntry, &fL1DFlushOnVMEntry); H();
    11921192        InsertConfigInteger(pHM, "L1DFlushOnVMEntry", fL1DFlushOnVMEntry);
     1193
     1194        BOOL fMDSClearOnSched = true;
     1195        hrc = pMachine->GetCPUProperty(CPUPropertyType_MDSClearOnEMTScheduling, &fMDSClearOnSched); H();
     1196        InsertConfigInteger(pHM, "MDSClearOnSched", fMDSClearOnSched);
     1197
     1198        BOOL fMDSClearOnVMEntry = false;
     1199        hrc = pMachine->GetCPUProperty(CPUPropertyType_MDSClearOnVMEntry, &fMDSClearOnVMEntry); H();
     1200        InsertConfigInteger(pHM, "MDSClearOnVMEntry", fMDSClearOnVMEntry);
    11931201
    11941202        /* Reset overwrite. */

  • trunk/src/VBox/Main/src-server/MachineImpl.cpp

    r78565 r78632  
    198198    mL1DFlushOnSched = true;
    199199    mL1DFlushOnVMEntry = false;
     200    mMDSClearOnSched = true;
     201    mMDSClearOnVMEntry = false;
    200202    mNestedHWVirt = false;
    201203    mHPETEnabled = false;
    … …  
    20362038            break;
    20372039
     2040        case CPUPropertyType_MDSClearOnEMTScheduling:
     2041            *aValue = mHWData->mMDSClearOnSched;
     2042            break;
     2043
     2044        case CPUPropertyType_MDSClearOnVMEntry:
     2045            *aValue = mHWData->mMDSClearOnVMEntry;
     2046            break;
     2047
    20382048        default:
    20392049            return E_INVALIDARG;
    … …  
    21252135            mHWData.backup();
    21262136            mHWData->mL1DFlushOnVMEntry = !!aValue;
     2137            break;
     2138
     2139        case CPUPropertyType_MDSClearOnEMTScheduling:
     2140            i_setModified(IsModified_MachineData);
     2141            mHWData.backup();
     2142            mHWData->mMDSClearOnSched = !!aValue;
     2143            break;
     2144
     2145        case CPUPropertyType_MDSClearOnVMEntry:
     2146            i_setModified(IsModified_MachineData);
     2147            mHWData.backup();
     2148            mHWData->mMDSClearOnVMEntry = !!aValue;
    21272149            break;
    21282150
    … …  
    88858907        mHWData->mL1DFlushOnSched             = data.fL1DFlushOnSched;
    88868908        mHWData->mL1DFlushOnVMEntry           = data.fL1DFlushOnVMEntry;
     8909        mHWData->mMDSClearOnSched             = data.fMDSClearOnSched;
     8910        mHWData->mMDSClearOnVMEntry           = data.fMDSClearOnVMEntry;
    88878911        mHWData->mNestedHWVirt                = data.fNestedHWVirt;
    88888912        mHWData->mCPUCount                    = data.cCPUs;
    … …  
    1021210236        data.fL1DFlushOnSched       = !!mHWData->mL1DFlushOnSched;
    1021310237        data.fL1DFlushOnVMEntry     = !!mHWData->mL1DFlushOnVMEntry;
     10238        data.fMDSClearOnSched       = !!mHWData->mMDSClearOnSched;
     10239        data.fMDSClearOnVMEntry     = !!mHWData->mMDSClearOnVMEntry;
    1021410240        data.fNestedHWVirt          = !!mHWData->mNestedHWVirt;
    1021510241        data.cCPUs                  = mHWData->mCPUCount;

  • trunk/src/VBox/Main/xml/Settings.cpp

    r78509 r78632  
    30893089    fL1DFlushOnSched(true),
    30903090    fL1DFlushOnVMEntry(false),
     3091    fMDSClearOnSched(true),
     3092    fMDSClearOnVMEntry(false),
    30913093    fNestedHWVirt(false),
    30923094    enmLongMode(HC_ARCH_BITS == 64 ? Hardware::LongMode_Enabled : Hardware::LongMode_Disabled),
    … …  
    32243226            && fL1DFlushOnSched          == h.fL1DFlushOnSched
    32253227            && fL1DFlushOnVMEntry        == h.fL1DFlushOnVMEntry
     3228            && fMDSClearOnSched          == h.fMDSClearOnSched
     3229            && fMDSClearOnVMEntry        == h.fMDSClearOnVMEntry
    32263230            && fNestedHWVirt             == h.fNestedHWVirt
    32273231            && cCPUs                     == h.cCPUs
    … …  
    42504254                pelmCPUChild->getAttributeValue("vmentry", hw.fL1DFlushOnVMEntry);
    42514255            }
     4256            pelmCPUChild = pelmHwChild->findChildElement("MDSClearOn");
     4257            if (pelmCPUChild)
     4258            {
     4259                pelmCPUChild->getAttributeValue("scheduling", hw.fMDSClearOnSched);
     4260                pelmCPUChild->getAttributeValue("vmentry", hw.fMDSClearOnVMEntry);
     4261            }
    42524262            pelmCPUChild = pelmHwChild->findChildElement("NestedHWVirt");
    42534263            if (pelmCPUChild)
    … …  
    56415651            if (hw.fL1DFlushOnVMEntry)
    56425652                pelmChild->setAttribute("vmentry", hw.fL1DFlushOnVMEntry);
     5653        }
     5654        if (!hw.fMDSClearOnSched || hw.fMDSClearOnVMEntry)
     5655        {
     5656            xml::ElementNode *pelmChild = pelmCPU->createChild("MDSClearOn");
     5657            if (!hw.fMDSClearOnSched)
     5658                pelmChild->setAttribute("scheduling", hw.fMDSClearOnSched);
     5659            if (hw.fMDSClearOnVMEntry)
     5660                pelmChild->setAttribute("vmentry", hw.fMDSClearOnVMEntry);
    56435661        }
    56445662    }
    … …  
    74457463            || hardwareMachine.fSpecCtrlByHost
    74467464            || !hardwareMachine.fL1DFlushOnSched
    7447             || hardwareMachine.fL1DFlushOnVMEntry)
     7465            || hardwareMachine.fL1DFlushOnVMEntry
     7466            || !hardwareMachine.fMDSClearOnSched
     7467            || hardwareMachine.fMDSClearOnVMEntry)
    74487468        {
    74497469            m->sv = SettingsVersion_v1_16;

  • trunk/src/VBox/VMM/VMMR0/CPUMR0.cpp

    r78431 r78632  
    268268
    269269        /*
    270          * Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host feature structure.
     270         * Copy MSR_IA32_ARCH_CAPABILITIES bits over into the host and guest feature
     271         * structure and as well as the guest MSR.
    271272         */
    272273        pVM->cpum.s.HostFeatures.fArchRdclNo             = 0;
    … …  
    274275        pVM->cpum.s.HostFeatures.fArchRsbOverride        = 0;
    275276        pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = 0;
     277        pVM->cpum.s.HostFeatures.fArchMdsNo              = 0;
    276278        uint32_t const cStdRange = ASMCpuId_EAX(0);
    277279        if (   ASMIsValidStdRange(cStdRange)
    … …  
    283285            {
    284286                uint64_t const fArchVal = ASMRdMsr(MSR_IA32_ARCH_CAPABILITIES);
    285                 pVM->cpum.s.HostFeatures.fArchRdclNo             = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
    286                 pVM->cpum.s.HostFeatures.fArchIbrsAll            = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
    287                 pVM->cpum.s.HostFeatures.fArchRsbOverride        = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
    288                 pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
     287                pVM->cpum.s.GuestFeatures.fArchRdclNo
     288                    = pVM->cpum.s.HostFeatures.fArchRdclNo             = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RDCL_NO);
     289                pVM->cpum.s.GuestFeatures.fArchIbrsAll
     290                    = pVM->cpum.s.HostFeatures.fArchIbrsAll            = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_IBRS_ALL);
     291                pVM->cpum.s.GuestFeatures.fArchRsbOverride
     292                    = pVM->cpum.s.HostFeatures.fArchRsbOverride        = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_RSBO);
     293                pVM->cpum.s.GuestFeatures.fArchVmmNeedNotFlushL1d
     294                    = pVM->cpum.s.HostFeatures.fArchVmmNeedNotFlushL1d = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D);
     295                pVM->cpum.s.GuestFeatures.fArchMdsNo
     296                    = pVM->cpum.s.HostFeatures.fArchMdsNo              = RT_BOOL(fArchVal & MSR_IA32_ARCH_CAP_F_MDS_NO);
     297
     298                if (pVM->cpum.s.GuestFeatures.fArchCap)
     299                    for (VMCPUID i = 0; i < pVM->cCpus; i++)
     300                        pVM->aCpus[i].cpum.s.GuestMsrs.msr.ArchCaps = fArchVal;
    289301            }
    290302            else

  • trunk/src/VBox/VMM/VMMR0/HMR0A.asm

    r78220 r78632  
    260260; @param    2   Which IBPB flag to test for (CPUMCTX_WSF_IBPB_ENTRY or CPUMCTX_WSF_IBPB_EXIT)
    261261; @param    3   Which FLUSH flag to test for (CPUMCTX_WSF_L1D_ENTRY)
    262 %macro INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER 3
     262; @param    4   Which MDS flag to test for (CPUMCTX_WSF_MDS_ENTRY)
     263%macro INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER 4
    263264    ; Only one test+jmp when disabled CPUs.
    264     test    byte [%1 + CPUMCTX.fWorldSwitcher], (%2 | %3)
     265    test    byte [%1 + CPUMCTX.fWorldSwitcher], (%2 | %3 | %4)
    265266    jz      %%no_barrier_needed
    266267
    … …  
    282283    mov     ecx, MSR_IA32_FLUSH_CMD
    283284    wrmsr
     285    jmp     %%no_mds_buffer_flushing    ; MDS flushing is included in L1D_FLUSH.
    284286%%no_cache_flush_barrier:
     287
     288    ; MDS buffer flushing.
     289    test    byte [%1 + CPUMCTX.fWorldSwitcher], %4
     290    jz      %%no_mds_buffer_flushing
     291    sub     xSP, xSP
     292    mov     [xSP], ds
     293    verw    [xSP]
     294    add     xSP, xSP
     295%%no_mds_buffer_flushing:
    285296
    286297%%no_barrier_needed:
    … …  
    14881499
    14891500    ; Fight spectre and similar.
    1490     INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY
     1501    INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY, CPUMCTX_WSF_MDS_ENTRY
    14911502
    14921503    ; Load guest general purpose registers.
    … …  
    17971808
    17981809    ; Fight spectre and similar.
    1799     INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY
     1810    INDIRECT_BRANCH_PREDICTION_AND_L1_CACHE_BARRIER xSI, CPUMCTX_WSF_IBPB_ENTRY, CPUMCTX_WSF_L1D_ENTRY, CPUMCTX_WSF_MDS_ENTRY
    18001811
    18011812    ; Load guest general purpose registers.
    … …  
    18551866ENDPROC VMXR0StartVM64
    18561867%endif ; RT_ARCH_AMD64
     1868
     1869
     1870;;
     1871; Clears the MDS buffers using VERW.
     1872ALIGNCODE(16)
     1873BEGINPROC hmR0MdsClear
     1874        sub     xSP, xCB
     1875        mov     [xSP], ds
     1876        verw    [xSP]
     1877        add     xSP, xCB
     1878        ret
     1879ENDPROC   hmR0MdsClear
    18571880
    18581881

  • trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

    r78622 r78632  
    89348934        if (pVCpu->CTX_SUFF(pVM)->hm.s.fL1dFlushOnSched)
    89358935            ASMWrMsr(MSR_IA32_FLUSH_CMD, MSR_IA32_FLUSH_CMD_F_L1D);
     8936        else if (pVCpu->CTX_SUFF(pVM)->hm.s.fMdsClearOnSched)
     8937            hmR0MdsClear();
    89368938    }
    89378939    return rc;

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r77032 r78632  
    8383    /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
    8484    /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
    85     /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
     85    /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Nehalem-EP */
    8686    /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
    8787    /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
    … …  
    135135    /* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
    136136    /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
    137     /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* unconfirmed */
    138     /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* unconfirmed, Broadwell-E */
     137    /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
     138    /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* Broadwell-E */
    139139    /* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
    140140    /* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    142142    /* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
    143143    /* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
    144     /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* server cpu */
     144    /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* server cpu; skylake <= 4, cascade lake > 5 */
    145145    /* [86(0x56)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* Xeon D-1540, Broadwell-DE */
    146146    /* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
    … …  
    167167    /*[108(0x6c)] = */ kCpumMicroarch_Intel_Unknown,
    168168    /*[109(0x6d)] = */ kCpumMicroarch_Intel_Unknown,
    169     /*[110(0x6e)] = */ kCpumMicroarch_Intel_Unknown,
     169    /*[110(0x6e)] = */ kCpumMicroarch_Intel_Atom_Airmount,      /* or silvermount? */
    170170    /*[111(0x6f)] = */ kCpumMicroarch_Intel_Unknown,
    171171    /*[112(0x70)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    174174    /*[115(0x73)] = */ kCpumMicroarch_Intel_Unknown,
    175175    /*[116(0x74)] = */ kCpumMicroarch_Intel_Unknown,
    176     /*[117(0x75)] = */ kCpumMicroarch_Intel_Unknown,
     176    /*[117(0x75)] = */ kCpumMicroarch_Intel_Atom_Airmount,      /* or silvermount? */
    177177    /*[118(0x76)] = */ kCpumMicroarch_Intel_Unknown,
    178178    /*[119(0x77)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    199199    /*[140(0x8c)] = */ kCpumMicroarch_Intel_Unknown,
    200200    /*[141(0x8d)] = */ kCpumMicroarch_Intel_Unknown,
    201     /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
     201    /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
    202202    /*[143(0x8f)] = */ kCpumMicroarch_Intel_Unknown,
    203203    /*[144(0x90)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    215215    /*[156(0x9c)] = */ kCpumMicroarch_Intel_Unknown,
    216216    /*[157(0x9d)] = */ kCpumMicroarch_Intel_Unknown,
    217     /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
     217    /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
    218218    /*[159(0x9f)] = */ kCpumMicroarch_Intel_Unknown,
    219219};
    … …  
    370370                {
    371371                    CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
    372                     if (   enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
    373                         && bStepping >= 0xa)
    374                         enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
     372                    if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
     373                    {
     374                        if (bStepping >= 0xa && bStepping <= 0xc)
     375                            enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
     376                        else if (bStepping >= 0xc)
     377                            enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
     378                    }
     379                    else if (   enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
     380                             && bModel == 0x55
     381                             && bStepping >= 5)
     382                        enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
    375383                    return enmMicroArch;
    376384                }
    … …  
    520528        CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
    521529        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
     530        CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
     531        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
    522532        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
    523533        CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
    … …  
    18931903            pFeatures->fFlushCmd            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
    18941904            pFeatures->fArchCap             = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
     1905            pFeatures->fMdsClear            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
    18951906        }
    18961907
    … …  
    24922503    CPUMISAEXTCFG   enmInvpcid;
    24932504    CPUMISAEXTCFG   enmFlushCmdMsr;
     2505    CPUMISAEXTCFG   enmMdsClear;
     2506    CPUMISAEXTCFG   enmArchCapMsr;
    24942507
    24952508    CPUMISAEXTCFG   enmAbm;
    … …  
    32913304                               ;
    32923305                pCurLeaf->uEdx &= 0
     3306                               | (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
    32933307                               //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT(26)
    32943308                               //| X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT(27)
    32953309                               | (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
    3296                                //| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT(29)
     3310                               | (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
    32973311                               ;
    32983312
    … …  
    33233337                    PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
    33243338                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD,  X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
     3339                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR,   X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
     3340                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP,    X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
    33253341                }
     3342
     3343                /* Dependencies. */
     3344                if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
     3345                    pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
    33263346
    33273347                /* Force standard feature bits. */
    … …  
    33383358                if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
    33393359                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
     3360                if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
     3361                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
     3362                if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
     3363                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
    33403364                break;
    33413365            }
    … …  
    43154339    AssertLogRelRCReturn(rc, rc);
    43164340
     4341    /** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
     4342     * Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
     4343     * the guest.  Requires FlushCmdMsr to be present too.
     4344     */
     4345    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     4346    AssertLogRelRCReturn(rc, rc);
     4347
     4348    /** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
     4349     * Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
     4350     */
     4351    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     4352    AssertLogRelRCReturn(rc, rc);
     4353
    43174354
    43184355    /* AMD: */
    … …  
    48914928                if (pVM->cpum.s.HostFeatures.fArchCap)
    48924929                {
    4893                     pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
    4894 
    48954930                    /* Install the architectural capabilities MSR. */
    48964931                    pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
    … …  
    50715106            pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
    50725107            if (pLeaf)
    5073                 pLeaf->uEdx &= ~(  X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP
    5074                                  | X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
     5108                pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP);
    50755109            pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
    50765110            Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
    … …  
    63876421static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
    63886422{
     6423    DBGFREGSUBFIELD_RO("MD_CLEAR\0"     "Supports MDS related buffer clearing",         10, 1, 0),
    63896424    DBGFREGSUBFIELD_RO("IBRS_IBPB\0"    "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB",   26, 1, 0),
    63906425    DBGFREGSUBFIELD_RO("STIBP\0"        "Supports IA32_SPEC_CTRL.STIBP",                27, 1, 0),

  • trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

    r76886 r78632  
    609609{
    610610    PCCPUMMSRRANGE papToAdd[10];
    611     uint32_t      cToAdd = 0;
     611    uint32_t       cToAdd = 0;
    612612
    613613    /*
    … …  
    630630        };
    631631        papToAdd[cToAdd++] = &s_FlushCmd;
     632    }
     633
     634    /*
     635     * The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
     636     * documented in relation to such.
     637     */
     638    if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
     639    {
     640        static CPUMMSRRANGE const s_ArchCaps =
     641        {
     642            /*.uFirst =*/       MSR_IA32_ARCH_CAPABILITIES,
     643            /*.uLast =*/        MSR_IA32_ARCH_CAPABILITIES,
     644            /*.enmRdFn =*/      kCpumMsrRdFn_Ia32ArchCapabilities,
     645            /*.enmWrFn =*/      kCpumMsrWrFn_ReadOnly,
     646            /*.offCpumCpu =*/   UINT16_MAX,
     647            /*.fReserved =*/    0,
     648            /*.uValue =*/       0,
     649            /*.fWrIgnMask =*/   0,
     650            /*.fWrGpMask =*/    UINT64_MAX,
     651            /*.szName = */      "IA32_ARCH_CAPABILITIES"
     652        };
     653        papToAdd[cToAdd++] = &s_ArchCaps;
    632654    }
    633655

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r78254 r78632  
    233233                              "|L1DFlushOnSched"
    234234                              "|L1DFlushOnVMEntry"
     235                              "|MDSClearOnSched"
     236                              "|MDSClearOnVMEntry"
    235237                              "|TPRPatchingEnabled"
    236238                              "|64bitEnabled"
    … …  
    425427
    426428    /** @cfgm{/HM/L1DFlushOnSched, bool, true}
    427      * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     429     * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
    428430    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
    429431    AssertLogRelRCReturn(rc, rc);
    430432
    431433    /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
    432      * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     434     * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
    433435    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
    434436    AssertLogRelRCReturn(rc, rc);
    … …  
    442444    rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
    443445    AssertLogRelRCReturn(rc, rc);
     446
     447    /** @cfgm{/HM/MDSClearOnSched, bool, true}
     448     * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
     449     * ignored on CPUs that aren't affected. */
     450    rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
     451    AssertLogRelRCReturn(rc, rc);
     452
     453    /** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
     454     * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
     455     * ignored on CPUs that aren't affected. */
     456    rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
     457    AssertLogRelRCReturn(rc, rc);
     458
     459    /* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
     460    if (pVM->hm.s.fMdsClearOnVmEntry)
     461        pVM->hm.s.fMdsClearOnSched = false;
    444462
    445463    /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
    … …  
    10941112
    10951113    /*
     1114     * Check if MDS flush is needed/possible.
     1115     * On atoms and knight family CPUs, we will only allow clearing on scheduling.
     1116     */
     1117    if (   !pVM->cpum.ro.HostFeatures.fMdsClear
     1118        || pVM->cpum.ro.HostFeatures.fArchMdsNo)
     1119        pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
     1120    else if (   (   pVM->cpum.ro.HostFeatures.enmMicroarch >=  kCpumMicroarch_Intel_Atom_Airmount
     1121                 && pVM->cpum.ro.HostFeatures.enmMicroarch <   kCpumMicroarch_Intel_Atom_End)
     1122             || (   pVM->cpum.ro.HostFeatures.enmMicroarch >=  kCpumMicroarch_Intel_Phi_KnightsLanding
     1123                 && pVM->cpum.ro.HostFeatures.enmMicroarch <   kCpumMicroarch_Intel_Phi_End))
     1124    {
     1125        if (!pVM->hm.s.fMdsClearOnSched)
     1126             pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
     1127        pVM->hm.s.fMdsClearOnVmEntry = false;
     1128    }
     1129    else if (   pVM->cpum.ro.HostFeatures.enmMicroarch <  kCpumMicroarch_Intel_Core7_Nehalem
     1130             || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
     1131        pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
     1132
     1133    /*
    10961134     * Sync options.
    10971135     */
    … …  
    11121150        if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
    11131151            pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_L1D_ENTRY;
     1152        if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
     1153            pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_MDS_ENTRY;
    11141154        if (iCpu == 0)
    1115             LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool\n",
     1155            LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
    11161156                    pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
    1117                     pVM->hm.s.fL1dFlushOnSched));
     1157                    pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
    11181158    }
    11191159

  • trunk/src/VBox/VMM/include/HMInternal.h

    r78222 r78632  
    472472    /** Set if host manages speculation control settings. */
    473473    bool                        fSpecCtrlByHost;
     474    /** Set if MDS related buffers should be cleared on VM entry. */
     475    bool                        fMdsClearOnVmEntry;
     476    /** Set if MDS related buffers should be cleared on EMT scheduling. */
     477    bool                        fMdsClearOnSched;
     478    /** Alignment padding. */
     479    bool                        afPaddingMinus1[6];
    474480
    475481    /** Maximum ASID allowed. */
    … …  
    11941200                                              PFNHMSVMVMRUN pfnVMRun);
    11951201# endif
     1202DECLASM(void)               hmR0MdsClear(void);
    11961203#endif /* IN_RING0 */
    11971204
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