VirtualBox

Changeset 78632 in vbox for trunk/src/VBox/VMM/VMMR3


Ignore:
Timestamp:
May 21, 2019 1:56:11 PM (6 years ago)
Author:
vboxsync
Message:

Forward ported 130474,130475,130477,130479. bugref:9453

Location:
trunk
Files:
5 edited

Legend:

Unmodified
Added
Removed

  • trunk

    • Property svn:mergeinfo

      •  

        old new  
        99/branches/VBox-5.1:112367,115992,116543,116550,116568,116573
        1010/branches/VBox-5.2:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124260,124263,124271,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812
         11/branches/VBox-6.0:130474-130475,130477,130479
        1112/branches/aeichner/vbox-chromium-cleanup:129816,129818-129851,129853-129861,129871-129872,129876,129880,129882,130013-130015,130036,130094-130095
        1213/branches/andy/draganddrop:90781-91268

  • trunk/src/VBox

    • Property svn:mergeinfo

      •  

        old new  
        99/branches/VBox-5.1/src/VBox:112367,116543,116550,116568,116573
        1010/branches/VBox-5.2/src/VBox:119536,120083,120099,120213,120221,120239,123597-123598,123600-123601,123755,124263,124273,124277-124279,124284-124286,124288-124290,125768,125779-125780,125812,127158-127159,127162-127167,127180
         11/branches/VBox-6.0/src/VBox:130474-130475,130477,130479
        1112/branches/aeichner/vbox-chromium-cleanup/src/VBox:129818-129851,129853-129861,129871-129872,129876,129880,129882,130013-130015,130094-130095
        1213/branches/andy/draganddrop/src/VBox:90781-91268

  • trunk/src/VBox/VMM/VMMR3/CPUMR3CpuId.cpp

    r77032 r78632  
    8383    /* [24(0x18)] = */ kCpumMicroarch_Intel_Unknown,
    8484    /* [25(0x19)] = */ kCpumMicroarch_Intel_Unknown,
    85     /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem,
     85    /* [26(0x1a)] = */ kCpumMicroarch_Intel_Core7_Nehalem, /* Nehalem-EP */
    8686    /* [27(0x1b)] = */ kCpumMicroarch_Intel_Unknown,
    8787    /* [28(0x1c)] = */ kCpumMicroarch_Intel_Atom_Bonnell, /* Diamonville, Pineview, */
    … …  
    135135    /* [76(0x4c)] = */ kCpumMicroarch_Intel_Atom_Airmount,
    136136    /* [77(0x4d)] = */ kCpumMicroarch_Intel_Atom_Silvermont,
    137     /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* unconfirmed */
    138     /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* unconfirmed, Broadwell-E */
     137    /* [78(0x4e)] = */ kCpumMicroarch_Intel_Core7_Skylake,
     138    /* [79(0x4f)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* Broadwell-E */
    139139    /* [80(0x50)] = */ kCpumMicroarch_Intel_Unknown,
    140140    /* [81(0x51)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    142142    /* [83(0x53)] = */ kCpumMicroarch_Intel_Unknown,
    143143    /* [84(0x54)] = */ kCpumMicroarch_Intel_Unknown,
    144     /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* server cpu */
     144    /* [85(0x55)] = */ kCpumMicroarch_Intel_Core7_Skylake,      /* server cpu; skylake <= 4, cascade lake > 5 */
    145145    /* [86(0x56)] = */ kCpumMicroarch_Intel_Core7_Broadwell,    /* Xeon D-1540, Broadwell-DE */
    146146    /* [87(0x57)] = */ kCpumMicroarch_Intel_Phi_KnightsLanding,
    … …  
    167167    /*[108(0x6c)] = */ kCpumMicroarch_Intel_Unknown,
    168168    /*[109(0x6d)] = */ kCpumMicroarch_Intel_Unknown,
    169     /*[110(0x6e)] = */ kCpumMicroarch_Intel_Unknown,
     169    /*[110(0x6e)] = */ kCpumMicroarch_Intel_Atom_Airmount,      /* or silvermount? */
    170170    /*[111(0x6f)] = */ kCpumMicroarch_Intel_Unknown,
    171171    /*[112(0x70)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    174174    /*[115(0x73)] = */ kCpumMicroarch_Intel_Unknown,
    175175    /*[116(0x74)] = */ kCpumMicroarch_Intel_Unknown,
    176     /*[117(0x75)] = */ kCpumMicroarch_Intel_Unknown,
     176    /*[117(0x75)] = */ kCpumMicroarch_Intel_Atom_Airmount,      /* or silvermount? */
    177177    /*[118(0x76)] = */ kCpumMicroarch_Intel_Unknown,
    178178    /*[119(0x77)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    199199    /*[140(0x8c)] = */ kCpumMicroarch_Intel_Unknown,
    200200    /*[141(0x8d)] = */ kCpumMicroarch_Intel_Unknown,
    201     /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
     201    /*[142(0x8e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
    202202    /*[143(0x8f)] = */ kCpumMicroarch_Intel_Unknown,
    203203    /*[144(0x90)] = */ kCpumMicroarch_Intel_Unknown,
    … …  
    215215    /*[156(0x9c)] = */ kCpumMicroarch_Intel_Unknown,
    216216    /*[157(0x9d)] = */ kCpumMicroarch_Intel_Unknown,
    217     /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping 0xA is CoffeeLake, 9 is KabyLake. */
     217    /*[158(0x9e)] = */ kCpumMicroarch_Intel_Core7_KabyLake, /* Stepping >= 0xB is Whiskey Lake, 0xA is CoffeeLake. */
    218218    /*[159(0x9f)] = */ kCpumMicroarch_Intel_Unknown,
    219219};
    … …  
    370370                {
    371371                    CPUMMICROARCH enmMicroArch = g_aenmIntelFamily06[bModel];
    372                     if (   enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake
    373                         && bStepping >= 0xa)
    374                         enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
     372                    if (enmMicroArch == kCpumMicroarch_Intel_Core7_KabyLake)
     373                    {
     374                        if (bStepping >= 0xa && bStepping <= 0xc)
     375                            enmMicroArch = kCpumMicroarch_Intel_Core7_CoffeeLake;
     376                        else if (bStepping >= 0xc)
     377                            enmMicroArch = kCpumMicroarch_Intel_Core7_WhiskeyLake;
     378                    }
     379                    else if (   enmMicroArch == kCpumMicroarch_Intel_Core7_Skylake
     380                             && bModel == 0x55
     381                             && bStepping >= 5)
     382                        enmMicroArch = kCpumMicroarch_Intel_Core7_CascadeLake;
    375383                    return enmMicroArch;
    376384                }
    … …  
    520528        CASE_RET_STR(kCpumMicroarch_Intel_Core7_KabyLake);
    521529        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CoffeeLake);
     530        CASE_RET_STR(kCpumMicroarch_Intel_Core7_WhiskeyLake);
     531        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CascadeLake);
    522532        CASE_RET_STR(kCpumMicroarch_Intel_Core7_CannonLake);
    523533        CASE_RET_STR(kCpumMicroarch_Intel_Core7_IceLake);
    … …  
    18931903            pFeatures->fFlushCmd            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD);
    18941904            pFeatures->fArchCap             = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
     1905            pFeatures->fMdsClear            = RT_BOOL(pSxfLeaf0->uEdx & X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR);
    18951906        }
    18961907
    … …  
    24922503    CPUMISAEXTCFG   enmInvpcid;
    24932504    CPUMISAEXTCFG   enmFlushCmdMsr;
     2505    CPUMISAEXTCFG   enmMdsClear;
     2506    CPUMISAEXTCFG   enmArchCapMsr;
    24942507
    24952508    CPUMISAEXTCFG   enmAbm;
    … …  
    32913304                               ;
    32923305                pCurLeaf->uEdx &= 0
     3306                               | (pConfig->enmMdsClear ? X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR : 0)
    32933307                               //| X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB         RT_BIT(26)
    32943308                               //| X86_CPUID_STEXT_FEATURE_EDX_STIBP             RT_BIT(27)
    32953309                               | (pConfig->enmFlushCmdMsr ? X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD : 0)
    3296                                //| X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP           RT_BIT(29)
     3310                               | (pConfig->enmArchCapMsr ? X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP : 0)
    32973311                               ;
    32983312
    … …  
    33233337                    PORTABLE_DISABLE_FEATURE_BIT(    1, pCurLeaf->uEcx, PREFETCHWT1, X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1);
    33243338                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, FLUSH_CMD,  X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD, pConfig->enmFlushCmdMsr);
     3339                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, MD_CLEAR,   X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR, pConfig->enmMdsClear);
     3340                    PORTABLE_DISABLE_FEATURE_BIT_CFG(3, pCurLeaf->uEdx, ARCHCAP,    X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP, pConfig->enmArchCapMsr);
    33253341                }
     3342
     3343                /* Dependencies. */
     3344                if (!(pCurLeaf->uEdx & X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD))
     3345                    pCurLeaf->uEdx &= ~X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
    33263346
    33273347                /* Force standard feature bits. */
    … …  
    33383358                if (pConfig->enmFlushCmdMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
    33393359                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD;
     3360                if (pConfig->enmMdsClear == CPUMISAEXTCFG_ENABLED_ALWAYS)
     3361                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR;
     3362                if (pConfig->enmArchCapMsr == CPUMISAEXTCFG_ENABLED_ALWAYS)
     3363                    pCurLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
    33403364                break;
    33413365            }
    … …  
    43154339    AssertLogRelRCReturn(rc, rc);
    43164340
     4341    /** @cfgm{/CPUM/IsaExts/MdsClear, isaextcfg, true}
     4342     * Whether to advertise the VERW and MDS related IA32_FLUSH_CMD MSR bits to
     4343     * the guest.  Requires FlushCmdMsr to be present too.
     4344     */
     4345    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "MdsClear", &pConfig->enmMdsClear, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     4346    AssertLogRelRCReturn(rc, rc);
     4347
     4348    /** @cfgm{/CPUM/IsaExts/ArchCapMSr, isaextcfg, true}
     4349     * Whether to expose the MSR_IA32_ARCH_CAPABILITIES MSR to the guest.
     4350     */
     4351    rc = cpumR3CpuIdReadIsaExtCfg(pVM, pIsaExts, "ArchCapMsr", &pConfig->enmArchCapMsr, CPUMISAEXTCFG_ENABLED_SUPPORTED);
     4352    AssertLogRelRCReturn(rc, rc);
     4353
    43174354
    43184355    /* AMD: */
    … …  
    48914928                if (pVM->cpum.s.HostFeatures.fArchCap)
    48924929                {
    4893                     pLeaf->uEdx |= X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP;
    4894 
    48954930                    /* Install the architectural capabilities MSR. */
    48964931                    pMsrRange = cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES);
    … …  
    50715106            pLeaf = cpumR3CpuIdGetExactLeaf(&pVM->cpum.s, UINT32_C(0x00000007), 0);
    50725107            if (pLeaf)
    5073                 pLeaf->uEdx &= ~(  X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP
    5074                                  | X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP);
     5108                pLeaf->uEdx &= ~(X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB | X86_CPUID_STEXT_FEATURE_EDX_STIBP);
    50755109            pVM->cpum.s.GuestFeatures.fSpeculationControl = 0;
    50765110            Log(("CPUM: ClearGuestCpuIdFeature: Disabled speculation control!\n"));
    … …  
    63876421static DBGFREGSUBFIELD const g_aLeaf7Sub0EdxSubFields[] =
    63886422{
     6423    DBGFREGSUBFIELD_RO("MD_CLEAR\0"     "Supports MDS related buffer clearing",         10, 1, 0),
    63896424    DBGFREGSUBFIELD_RO("IBRS_IBPB\0"    "IA32_SPEC_CTRL.IBRS and IA32_PRED_CMD.IBPB",   26, 1, 0),
    63906425    DBGFREGSUBFIELD_RO("STIBP\0"        "Supports IA32_SPEC_CTRL.STIBP",                27, 1, 0),

  • trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp

    r76886 r78632  
    609609{
    610610    PCCPUMMSRRANGE papToAdd[10];
    611     uint32_t      cToAdd = 0;
     611    uint32_t       cToAdd = 0;
    612612
    613613    /*
    … …  
    630630        };
    631631        papToAdd[cToAdd++] = &s_FlushCmd;
     632    }
     633
     634    /*
     635     * The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
     636     * documented in relation to such.
     637     */
     638    if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
     639    {
     640        static CPUMMSRRANGE const s_ArchCaps =
     641        {
     642            /*.uFirst =*/       MSR_IA32_ARCH_CAPABILITIES,
     643            /*.uLast =*/        MSR_IA32_ARCH_CAPABILITIES,
     644            /*.enmRdFn =*/      kCpumMsrRdFn_Ia32ArchCapabilities,
     645            /*.enmWrFn =*/      kCpumMsrWrFn_ReadOnly,
     646            /*.offCpumCpu =*/   UINT16_MAX,
     647            /*.fReserved =*/    0,
     648            /*.uValue =*/       0,
     649            /*.fWrIgnMask =*/   0,
     650            /*.fWrGpMask =*/    UINT64_MAX,
     651            /*.szName = */      "IA32_ARCH_CAPABILITIES"
     652        };
     653        papToAdd[cToAdd++] = &s_ArchCaps;
    632654    }
    633655

  • trunk/src/VBox/VMM/VMMR3/HM.cpp

    r78254 r78632  
    233233                              "|L1DFlushOnSched"
    234234                              "|L1DFlushOnVMEntry"
     235                              "|MDSClearOnSched"
     236                              "|MDSClearOnVMEntry"
    235237                              "|TPRPatchingEnabled"
    236238                              "|64bitEnabled"
    … …  
    425427
    426428    /** @cfgm{/HM/L1DFlushOnSched, bool, true}
    427      * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     429     * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
    428430    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
    429431    AssertLogRelRCReturn(rc, rc);
    430432
    431433    /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
    432      * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
     434     * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
    433435    rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
    434436    AssertLogRelRCReturn(rc, rc);
    … …  
    442444    rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
    443445    AssertLogRelRCReturn(rc, rc);
     446
     447    /** @cfgm{/HM/MDSClearOnSched, bool, true}
     448     * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
     449     * ignored on CPUs that aren't affected. */
     450    rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
     451    AssertLogRelRCReturn(rc, rc);
     452
     453    /** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
     454     * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
     455     * ignored on CPUs that aren't affected. */
     456    rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
     457    AssertLogRelRCReturn(rc, rc);
     458
     459    /* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
     460    if (pVM->hm.s.fMdsClearOnVmEntry)
     461        pVM->hm.s.fMdsClearOnSched = false;
    444462
    445463    /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
    … …  
    10941112
    10951113    /*
     1114     * Check if MDS flush is needed/possible.
     1115     * On atoms and knight family CPUs, we will only allow clearing on scheduling.
     1116     */
     1117    if (   !pVM->cpum.ro.HostFeatures.fMdsClear
     1118        || pVM->cpum.ro.HostFeatures.fArchMdsNo)
     1119        pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
     1120    else if (   (   pVM->cpum.ro.HostFeatures.enmMicroarch >=  kCpumMicroarch_Intel_Atom_Airmount
     1121                 && pVM->cpum.ro.HostFeatures.enmMicroarch <   kCpumMicroarch_Intel_Atom_End)
     1122             || (   pVM->cpum.ro.HostFeatures.enmMicroarch >=  kCpumMicroarch_Intel_Phi_KnightsLanding
     1123                 && pVM->cpum.ro.HostFeatures.enmMicroarch <   kCpumMicroarch_Intel_Phi_End))
     1124    {
     1125        if (!pVM->hm.s.fMdsClearOnSched)
     1126             pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
     1127        pVM->hm.s.fMdsClearOnVmEntry = false;
     1128    }
     1129    else if (   pVM->cpum.ro.HostFeatures.enmMicroarch <  kCpumMicroarch_Intel_Core7_Nehalem
     1130             || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
     1131        pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
     1132
     1133    /*
    10961134     * Sync options.
    10971135     */
    … …  
    11121150        if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
    11131151            pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_L1D_ENTRY;
     1152        if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
     1153            pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_MDS_ENTRY;
    11141154        if (iCpu == 0)
    1115             LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool\n",
     1155            LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
    11161156                    pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
    1117                     pVM->hm.s.fL1dFlushOnSched));
     1157                    pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
    11181158    }
    11191159
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