Changeset 78691 in vbox for trunk/src/VBox

Timestamp:

May 23, 2019 11:23:39 AM (6 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

130767

Message:

VMM/HMVMXR0: Nested VMX: bugref:9180 Try fix CR0/CR4 read shadows because we merge in the host/hypervisor CR0/CR4 mask with the guest-hypervisor's CR0/CR4 mask. Still needs fixing while importing the nested-guest CR0/CR4. Have to figure that out.

File:

• trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp (modified) (6 diffs)

trunk/src/VBox/VMM/VMMR0/HMVMXR0.cpp

@@ -4830 +4830 @@
         else
         {
-            PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
+            /*
+             * With nested-guests, we may have extended the guest/host mask here (since we
+             * merged in the outer guest's mask, see hmR0VmxMergeVmcsNested). This means, the
+             * mask can include more bits (to read from the nested-guest CR0 read-shadow) than
+             * the guest hypervisor originally supplied. Thus, we should, in essence, copy
+             * those bits from the nested-guest CR0 into the nested-guest CR0 read shadow.
+             */
             HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR0);
             uint64_t       u64GuestCr0  = pVCpu->cpum.GstCtx.cr0;
-            uint64_t const u64ShadowCr0 = pVmcsNstGst->u64Cr0ReadShadow.u;
+            uint64_t const u64ShadowCr0 = CPUMGetGuestVmxMaskedCr0(pVCpu, &pVCpu->cpum.GstCtx);
             Assert(!RT_HI_U32(u64GuestCr0));
             Assert(u64GuestCr0 & X86_CR0_NE);
@@ -4843 +4849 @@
 
             /* Commit the CR0 and CR0 read shadow to the nested-guest VMCS. */
-            int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0, u64GuestCr0);   /** @todo NSTVMX: Fix to 64-bit when we drop 32-bit. */
+            /** @todo NSTVMX: Fix to 64-bit when we drop 32-bit. */
+            int rc = VMXWriteVmcs32(VMX_VMCS_GUEST_CR0,              u64GuestCr0);
             rc    |= VMXWriteVmcsHstN(VMX_VMCS_CTRL_CR0_READ_SHADOW, u64ShadowCr0);
             AssertRCReturn(rc, rc);
@@ -4988 +4995 @@
         PCPUMCTX     pCtx        = &pVCpu->cpum.GstCtx;
         PVMXVMCSINFO pVmcsInfo   = pVmxTransient->pVmcsInfo;
-        PCVMXVVMCS   pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
 
         /*
@@ -4996 +5002 @@
         uint64_t const fZapCr4 = pVM->hm.s.vmx.Msrs.u64Cr4Fixed0 | pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
 
+        /*
+         * With nested-guests, we may have extended the guest/host mask here (since we
+         * merged in the outer guest's mask, see hmR0VmxMergeVmcsNested). This means, the
+         * mask can include more bits (to read from the nested-guest CR4 read-shadow) than
+         * the guest hypervisor originally supplied. Thus, we should, in essence, copy
+         * those bits from the nested-guest CR4 into the nested-guest CR4 read shadow.
+         */
         HMVMX_CPUMCTX_ASSERT(pVCpu, CPUMCTX_EXTRN_CR4);
         uint64_t       u64GuestCr4  = pCtx->cr4;
-        uint64_t const u64ShadowCr4 = !pVmxTransient->fIsNestedGuest ? pCtx->cr4 : pVmcsNstGst->u64Cr4ReadShadow.u;
+        uint64_t const u64ShadowCr4 = !pVmxTransient->fIsNestedGuest
+                                    ? pCtx->cr4
+                                    : CPUMGetGuestVmxMaskedCr4(pVCpu, pCtx);
         Assert(!RT_HI_U32(u64GuestCr4));
 
@@ -5070 +5085 @@
 
         /* Commit the CR4 and CR4 read shadow to the guest VMCS. */
-        rc  = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4, u64GuestCr4);  /** @todo Fix to 64-bit when we drop 32-bit. */
+        /** @todo Fix to 64-bit when we drop 32-bit. */
+        rc  = VMXWriteVmcs32(VMX_VMCS_GUEST_CR4,              u64GuestCr4);
         rc |= VMXWriteVmcsHstN(VMX_VMCS_CTRL_CR4_READ_SHADOW, u64ShadowCr4);
         AssertRCReturn(rc, rc);
@@ -7547 +7563 @@
                     VMXLOCAL_BREAK_RC(rc);
                     u64Val = u32Val;
+#if 1
                     u64Val = (u64Val    & ~pVmcsInfo->u64Cr0Mask)
                            | (u64Shadow &  pVmcsInfo->u64Cr0Mask);
+#else
+                    if (!CPUMIsGuestInVmxNonRootMode(pCtx))
+                    {
+                        u64Val = (u64Val    & ~pVmcsInfo->u64Cr0Mask)
+                               | (u64Shadow &  pVmcsInfo->u64Cr0Mask);
+                    }
+                    else
+                    {
+                        /** @todo NSTVMX: We need to do some unfudging here because we altered the
+                         *        guest/host mask before running the nested-guest. */
+                        PCVMXVVMCS pVmcsNstGst = pVCpu->cpum.GstCtx.hwvirt.vmx.CTX_SUFF(pVmcs);
+                        Assert(pVmcsNstGst);
+
+                        uint64_t const uGstCr0Mask = pVmcsNstGst->u64Cr0Mask.u;
+                        uint64_t const uHstCr0Mask = hmR0VmxGetFixedCr0Mask(pVCpu);
+                    }
+#endif
                     VMMRZCallRing3Disable(pVCpu);   /* May call into PGM which has Log statements. */
                     CPUMSetGuestCR0(pVCpu, u64Val);